Nano-wall Integrated Circuit Structure with High Integrated Density

Abstract

A nano-wall integrated circuit structure with high integration density is disclosed, which relates to the fields of microelectronic technology and integrated circuits (IC). Based on the different device physical principles with MOSFETs in traditional ICs, the nano-wall integrated circuit unit structure (Nano-Wall FET, referred to as NWaFET) with high integration density can improve the integration of the IC, significantly shorten the channel length, improve the flexibility of the device channel width-to-length ratio adjustment, and save chip area.

Claims

1. A nano-wall integrated circuit structure (NWaFET), comprising: a well semiconductor region having a first conductivity type, a heavily doped drain region on the well semiconductor region, wherein the heavily doped drain region has a second conductivity type and includes an upper portion and a lower portion, and the lower portion is wider than the upper portion and has bottom and side surfaces surrounded by the well semiconductor region, a lightly doped drain region above the heavily doped drain region, the lightly doped drain region having the second conductivity type; a heavily doped, first conductivity type channel semiconductor region above the lightly doped drain region; a heavily doped, second conductivity type source region above the channel semiconductor region, wherein the heavily doped source region comprises a narrow bandgap pseudocrystalline, narrow bandgap polycrystalline or single crystal silicon semiconductor; an insulating gate dielectric and a gate electrode on a first side surface of each of the upper portion of the heavily doped drain region, the lightly doped drain region, the channel semiconductor region, and the heavily doped source region; and an insulating material on a second side surface of each of the heavily doped source region, the channel semiconductor region, the lightly doped drain region, and the upper portion of the heavily doped drain region, and a drain electrode in contact with the heavily doped drain region, in the insulating material and isolated from the heavily doped source region, the channel semiconductor region, and the lightly doped drain region, wherein: the insulating gate dielectric and the gate electrode have a lowermost surface that is higher than a first interface between the heavily doped drain region and the well semiconductor region and lower than a second interface between the lightly doped drain region and the heavily doped drain region, the gate electrode comprises heavily doped polycrystalline silicon, a refractory metal silicide, a refractory metal, or a combination thereof; the insulated gate dielectric isolates the gate electrode from the heavily doped source region, the channel semiconductor region, the lightly doped drain region, and the heavily doped drain region, and a contact surface between the drain electrode and the heavily doped drain region is lower than the second interface.

2. The nano-wall integrated circuit structure of claim 1, wherein the channel semiconductor region has a thickness that is less than 12 nm.

3. The nano-wall integrated circuit structure of claim 2, wherein the channel semiconductor region has a doping concentration that is at least 2 orders of magnitude higher than that of the lightly doped drain region.

4. The nano-wall integrated circuit structure of claim 3, wherein the first conductivity type is P-type, and the second conductivity type is N-type.

5. The nano-wall integrated circuit structure of claim 4, wherein the lowermost surfaces of the insulating gate dielectric and the gate electrode are higher than the first interface and lower than the second interface.

6. The nano-wall integrated circuit structure of claim 5, further comprising a lightly doped source region above the channel semiconductor region and below the heavily doped source region, wherein the insulating gate dielectric and the gate electrode are on a first side surface of each of the upper portion of the heavily doped drain region, the lightly doped drain region, the channel semiconductor region, the lightly doped source region, and the heavily doped source region, the insulating gate dielectric isolates the gate electrode from the heavily doped drain region, the lightly doped drain region, the channel semiconductor region, the lightly doped source region, and the heavily doped source region, and the drain electrode is isolated from the lightly doped drain region, the channel semiconductor region, the lightly doped source region, and the heavily doped source region by the insulating material.

7. The nano-wall integrated circuit structure of claim 6, wherein the lightly doped source region comprises a narrow bandgap pseudocrystalline, narrow bandgap polycrystalline or single crystal silicon semiconductor, and the lightly doped source region has a doping concentration that is lower than that of the heavily doped source region and the channel semiconductor region.

8. The nano-wall integrated circuit structure of claim 4, the lowermost surface of the insulating gate dielectric and the gate electrode is higher than the second interface and lower than a third interface between the channel semiconductor region and the lightly doped drain region.

9. The nano-wall integrated circuit structure of claim 8, further comprising a lightly doped source region above the channel semiconductor region and below the heavily doped source region, wherein the insulating gate dielectric and the gate electrode are on a first side surface of each of the upper portion of the heavily doped drain region, the lightly doped drain region, the channel semiconductor region, the lightly doped source region, and the heavily doped source region, the insulating gate dielectric isolates the gate electrode from the heavily doped drain region, the lightly doped drain region, the channel semiconductor region, the lightly doped source region, and the heavily doped source region, and the drain electrode is isolated from the lightly doped drain region, the channel semiconductor region, the lightly doped source region, and the heavily doped source region by the insulating material.

10. The nano-wall integrated circuit structure of claim 9, wherein the lightly doped source region comprises a narrow bandgap pseudocrystalline, narrow bandgap polycrystalline or single crystal silicon semiconductor, and the lightly doped source region has a doping concentration that is lower than that of the heavily doped source region and the channel semiconductor region.

11. The nano-wall integrated circuit structure of claim 3, wherein the first conductivity type is N-type, and the second conductivity type is P-type

12. The nano-wall integrated circuit structure of claim 11, wherein the lowermost surfaces of the insulating gate dielectric and the gate electrode are higher than the first interface and lower than the second interface.

13. The nano-wall integrated circuit structure of claim 12, further comprising a lightly doped source region above the channel semiconductor region and below the heavily doped source region, wherein the insulating gate dielectric and the gate electrode are on a first side surface of each of the upper portion of the heavily doped drain region, the lightly doped drain region, the channel semiconductor region, the lightly doped source region, and the heavily doped source region, the insulating gate dielectric isolates the gate electrode from the heavily doped drain region, the lightly doped drain region, the channel semiconductor region, the lightly doped source region, and the heavily doped source region, and the drain electrode is isolated from the lightly doped drain region, the channel semiconductor region, the lightly doped source region, and the heavily doped source region by the insulating material.

14. The nano-wall integrated circuit structure of claim 13, wherein the lightly doped source region comprises a narrow bandgap pseudocrystalline, narrow bandgap polycrystalline or single crystal silicon semiconductor, and the lightly doped source region has a doping concentration that is lower than that of the heavily doped source region and the channel semiconductor region.

15. The nano-wall integrated circuit structure of claim 11, wherein the lowermost surface of the insulating gate dielectric and the gate electrode is higher than the second interface and lower than the third interface.

16. The nano-wall integrated circuit structure of claim 15, further comprising a lightly doped source region above the channel semiconductor region and below the heavily doped source region, wherein the insulating gate dielectric and the gate electrode are on a first side surface of each of the upper portion of the heavily doped drain region, the lightly doped drain region, the channel semiconductor region, the lightly doped source region, and the heavily doped source region, the insulating gate dielectric isolates the gate electrode from the heavily doped drain region, the lightly doped drain region, the channel semiconductor region, the lightly doped source region, and the heavily doped source region, and the drain electrode is isolated from the lightly doped drain region, the channel semiconductor region, the lightly doped source region, and the heavily doped source region by the insulating material.

17. The nano-wall integrated circuit structure of claim 16, wherein the lightly doped source region comprises a narrow bandgap pseudocrystalline, narrow bandgap polycrystalline or single crystal silicon semiconductor, and the lightly doped source region has a doping concentration that is lower than that of the heavily doped source region and the channel semiconductor region.

Description

DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1 is the oblique cross-sectional view of a deep gate trench NMOSFET unit with a nano-wall integrated circuit structure with high integration density without N-lightly doped source region of one embodiment of this invention.

[0028] FIG. 2 is the oblique cross-sectional view of a shallow gate trench NMOSFET unit with a nano-wall integrated circuit structure with high integration density without N-lightly doped source region of one embodiment of this invention.

[0029] FIG. 3 is the oblique cross-sectional view of a deep gate trench NMOSFET unit with a nano-wall integrated circuit structure with high integration density with N-lightly doped source region of one embodiment of this invention.

[0030] FIG. 4 is the oblique cross-sectional view of a shallow gate trench NMOSFET unit with a nano-wall integrated circuit structure with high integration density with N-lightly doped source region of one embodiment of this invention.

[0031] FIG. 5 is the oblique cross-sectional view of a deep gate trench PMOSFET unit with a nano-wall integrated circuit structure with high integration density without P-lightly doped source region of one embodiment of this invention.

[0032] FIG. 6 is the oblique cross-sectional view of a shallow gate trench PMOSFET unit with a nano-wall integrated circuit structure with high integration density without P-lightly doped source region of one embodiment of this invention.

[0033] FIG. 7 is the oblique cross-sectional view of a deep gate trench PMOSFET unit with a nano-wall integrated circuit structure with high integration density with P− lightly doped source region of one embodiment of this invention.

[0034] FIG. 8 is the oblique cross-sectional view of a shallow gate trench PMOSFET unit with a nano-wall integrated circuit structure with high integration density with P− lightly doped source region of one embodiment of this invention.

[0035] FIG. 9 is the top view of a structure NMOSFET unit of a nano-wall integrated circuit structure with high integration density of one or more embodiments of this invention.

[0036] FIG. 10 is the top view of a structure PMOSFET unit of a nano-wall integrated circuit structure with high integration density of one or more embodiments of this invention.

[0037] FIG. 11 is the cross-sectional view of a deep gate trench NMOSFET unit with a nano-wall integrated circuit structure with high integration density without N− lightly doped source region of one embodiment of this invention.

[0038] FIG. 12 is the cross-sectional view of a deep gate trench PMOSFET unit with a nano-wall integrated circuit structure with high integration density without N− lightly doped source region of one embodiment of this invention.

[0039] FIGS. 13A-D are the top view of a multiple combination of the gate electrode 106 and the PN functional region of a nano-wall integrated circuit structure with high integration density of one or more embodiments of this invention.

[0040] FIG. 14 is the cross-sectional view of the simulation structure of Example 1.

[0041] FIG. 15 is the transient response curves obtained by simulation of Example 1.

[0042] FIG. 16 is the cross-sectional view of the simulation structure of Example 2.

[0043] FIG. 17 is the transfer characteristic curves obtained by simulation of Example 2.

[0044] FIG. 18 is the output characteristic curves obtained by simulation of Example 2.

[0045] FIG. 19 is the frequency response curve obtained by simulation of Example 2.

[0046] FIG. 20 is the cross-sectional view of the simulation structure of Example 3.

[0047] FIG. 21 is the transfer characteristic curves obtained by simulation of Example 3.

[0048] FIG. 22 is the output characteristic curves obtained by simulation of Example 3.

[0049] FIG. 23 is the curve of the DIBL value with the change of the doping concentration of the P+ channel region obtained by the simulation of Example 4.

[0050] FIG. 24 is the cross-sectional view of the simulation structure of Example 5.

[0051] FIG. 25 is the transfer characteristic curves obtained by simulation of Example 5.

[0052] FIG. 26 is the output characteristic curves obtained by simulation of Example 5.

EXAMPLES

Example 1

[0053] A computer three-dimensional simulation was performed based on the CMOS inverter structure using the technical embodiments 6 and 8 of this invention, and the simulation structure is shown in FIG. 14. For the NMOSFET, the N+ heavily doped source region is silicon, the depth or thickness is 20 nm, and the doping concentration is 1×10.sup.20 cm.sup.−3. The depth or thickness of the N− lightly doped source region is 20 nm, and the doping concentration is 1×10.sup.16 cm.sup.−3. The depth or thickness of the P+ channel region is 10 nm, and the doping concentration is 1×10.sup.18 cm.sup.−3. The depth or thickness of the N− lightly doped drain region is 20 nm, and the doping concentration is 1×10.sup.16 cm.sup.−3. The depth or thickness of the N+ heavily doped drain region is 20 nm, and the doping concentration is 1×10.sup.20 cm.sup.−3. For the PMOSFET, the depth or thickness of the P+ heavily doped source region is 20 nm, and the doping concentration is 1×10.sup.20 cm.sup.−3. The depth or thickness of the P− lightly doped source region is 20 nm, and the doping concentration is 1×10.sup.16 cm.sup.−3. The depth or thickness of the N+ channel region is 10 nm, and the doping concentration is 1×10.sup.18 cm.sup.−3. The depth or thickness of the P− lightly doped drain region is 20 nm, and the doping concentration is 1×10.sup.16 cm.sup.−3. The depth or thickness of the P+ heavily doped drain region is 20 nm, and the doping concentration is 1×10.sup.20 cm.sup.−3. The gate material is polysilicon, and the depth is 2 nm below the bottom surface of the N− lightly doped drain region. The gate dielectric is silicon dioxide with a thickness of 1 nm; the channel width of the NMOSFET is 20 nm, and the channel width-to-length ratio is 2:1. The channel width of the PMOSFET is three times the width of the channel of the NMOSFET, that is, 60 nm, and the channel width-to-length ratio is 6:1. The lead metal of the two transistor drains is Ti, and the depth is 10 nm below the bottom surface of the N− lightly doped drain region. The input voltage of transient simulation is a periodically changing square wave signal, the input low level is 0V, the input high level is 1.5V, and the level transition time from high to low and from low to high is 1×10.sup.−11 s.

[0054] The simulation results are shown in the attached drawings of the specification, and FIG. 15 is the transient response curves obtained by the simulation. It can be seen from the simulation results that the common gate of NMOSFET and PMOSFET can realize the function of CMOS inverter IC. Without careful optimization, NWaFET devices with a channel length of 10 nm have achieved inverter IC switching times of less than 10 ps.

Example 2

[0055] A computer three-dimensional simulation was performed based on the NMOSFET structure using the technical embodiment 4 of this invention, and the cross-sectional view of the simulation structure is shown in FIG. 16. The N+ heavily doped source region material is silicon, the depth or thickness is 10 nm, and the doping concentration is 1×10.sup.20 cm.sup.−3. The depth or thickness of the N− lightly doped source region is 20 nm, and the doping concentration is 1×10.sup.17 cm.sup.−3. The depth or thickness of the P+ channel is 0.543 nm, and the doping concentration is 2×10.sup.20 cm.sup.−3. The depth or thickness of the N− lightly doped drain region is 20 nm, and the doping concentration is 1×10.sup.17 cm.sup.−3. The depth or thickness of the N+ heavily doped drain region is 10 nm, and the doping concentration is 1×10.sup.20 cm.sup.−3. The gate material is polysilicon, and the depth is 2 nm below the bottom surface of the P+ channel region. The gate dielectric material is silicon dioxide with a thickness of 1.1 nm. The gate is arranged on one side of the PN functional area, the corresponding channel width is 5 nm, and the channel width-to-length ratio is about 9.2:1.

[0056] The simulation results are shown in the attached drawings of the specification, and FIG. 17 is the transfer characteristic curves obtained by the simulation, and FIG. 18 is the output characteristic curves obtained by the simulation. It can be seen from the simulation results that the NMOSFET structure using the technical embodiment 4 of this invention can obtain transistor characteristics as expected when the channel length is 0.543 nm, and the calculated threshold voltage is 0.36V when the source-drain voltage V.sub.ds is 0.05V. The on-off ratio can reach 1×10.sup.6. FIG. 19 shows the frequency response curve obtained by the simulation. It can be seen from the simulation result that the cut off frequency f.sub.t of the device is 2.33 THz.

Example 3

[0057] A computer three-dimensional simulation was performed based on the NMOSFET structure using the technical embodiment 2 of this invention, and the cross-sectional view of the simulation structure is shown in FIG. 20. The N+ heavily doped source region material is SiGe, the depth or thickness is 10 nm, and the doping concentration is 1×10.sup.20 cm.sup.−3. The depth or thickness of the P+ channel is 7 nm, and the doping concentration is 5×10.sup.19 cm.sup.−3. The depth or thickness of the N− lightly doped drain region is 10 nm, and the doping concentration is 1×10.sup.15 cm.sup.−3. The depth or thickness of the N+ heavily doped drain region is 10 nm, and the doping concentration is 1×10.sup.20 cm.sup.−3. The gate material is polysilicon, and the depth is flush with the bottom surface of the P+ channel region. The gate dielectric material is silicon dioxide, and the thickness is 2 nm. The gate is arranged on three sides of the PN functional area, the corresponding channel width is 21 nm, and the channel width-to-length ratio is 3:1.

[0058] The simulation results are shown in the attached drawings of the specification, and FIG. 21 is the transfer characteristic curves obtained by the simulation, and FIG. 22 is the output characteristic curves obtained by the simulation. It can be seen from the simulation results that the NMOSFET structure using the technical embodiment 2 of this invention can obtain transistor characteristics as expected, and the calculated threshold voltage is 0.7V when the source-drain voltage V.sub.ds is 1.2V. The on-off ratio can reach 1×10.sup.8.

Example 4

[0059] A computer three-dimensional simulation was performed based on the NMOSFET structure using the technical embodiment 4 of this invention, and the cross-sectional view of the simulation structure is shown in FIG. 16. The N+ heavily doped source region material is silicon, the depth or thickness is 10 nm, and the doping concentration is 1×10.sup.20 cm.sup.−3. The depth or thickness of the N− lightly doped source region is 10 nm, and the doping concentration is 1×10.sup.17 cm.sup.3. The depth or thickness of the P+ channel is 0.543 nm. The depth or thickness of the N− lightly doped drain region is 10 nm, and the doping concentration is 1×10.sup.17 cm.sup.−3. The depth or thickness of the N+ heavily doped drain region is 10 nm, and the doping concentration is 1×10.sup.20 cm.sup.−3. The gate material is polysilicon, and the depth is 2 nm below the bottom surface of the P+ channel region. The gate dielectric material is silicon dioxide with a thickness of 1.1 nm. The gate is arranged on four sides of the PN functional area, the corresponding channel width is 20 nm, and the channel width-to-length ratio is about 36.8:1.

[0060] FIG. 23 shows the change of DIBL value when the doping concentration of the P+ channel region increases from 1×10.sup.19 cm.sup.−3 to 3×10.sup.20 cm.sup.−3. When the doping concentration of the P+ channel region increases, it can be observed that the DIBL value gradually decreases, indicating that the highly doped channel region of the NWaFET structure can effectively suppress the DIBL effect.

Example 5

[0061] A computer three-dimensional simulation was performed based on the NMOSFET structure using the technical embodiment 8 of this invention, and the cross-sectional view of the simulation structure is shown in FIG. 24. The P+ heavily doped source region material is silicon, the depth or thickness is 10 nm, and the doping concentration is 1×10.sup.20 cm.sup.−3. The depth or thickness of the P− lightly doped source region is 20 nm, and the doping concentration is 1×10.sup.16 cm.sup.−3. The depth or thickness of the N+ channel is 10 nm. The depth or thickness of the P− lightly doped drain region is 20 nm, and the doping concentration is 1×10.sup.17 cm.sup.−3. The depth or thickness of the P+ heavily doped drain region is 10 nm, and the doping concentration is 1×10.sup.20 cm.sup.−3. The gate material is polysilicon, and the depth is 5 nm below the bottom surface of the N+ channel region. The gate dielectric material is silicon dioxide with a thickness of 3 nm. The gate is arranged on four sides of the PN functional area, the corresponding channel width is 40 nm, and the channel width-to-length ratio is about 4:1.

[0062] The simulation results are shown in the attached drawings of the specification, and FIG. 25 is the transfer characteristic curves obtained by the simulation, and FIG. 26 is the output characteristic curves obtained by the simulation. It can be seen from the simulation results that the NMOSFET structure using the technical embodiment 8 of this invention can obtain transistor characteristics as expected, and the calculated threshold voltage is −0.9V when the source-drain voltage V.sub.ds is −2V. The on-off ratio can reach 1×10.sup.8.