Assemblies Which Include Ruthenium-Containing Conductive Gates

Abstract

Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material. Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material. Some embodiments include methods of forming integrated assemblies.

Claims

1-34. (canceled)

35. A method of forming an integrated assembly, comprising: forming a stack comprising alternating first and second materials; the second material being an insulative material; forming openings through the stack; forming channel-material-pillars in some of the openings and leaving other openings empty; removing the first material to leave voids; forming conductive liners along the empty openings; and while the conductive liners remain, filling the voids with conductive material.

36. The method of claim 21 wherein the conductive liners comprise ruthenium.

37. The method of claim 21 wherein the conductive material comprises ruthenium.

38. The method of claim 21 wherein the forming of the conductive liners further comprises forming the conductive liners along the voids.

39. The method of claim 21 wherein the filling of the voids further comprises filing the empty openings with the conductive material.

40. The method of claim 21 further comprising recessing the conductive material in the voids.

41. The method of claim 40 wherein the recessing occurs while the conductive liners remain in the empty openings.

42. The method of claim 21 further comprising removing the conductive liners from the empty openings.

43. The method of claim 21 wherein the forming of the conductive liners further comprises forming the conductive liners along the voids; and further comprising recessing the conductive liners within the voids.

44. The method of claim 21 wherein the forming of the conductive liners further comprises; forming a first liner along a periphery of the empty opening; and forming a second liner along a periphery of the first liner, at least one of the first and second liners being conductive.

45. The method of claim 21 wherein the forming of the conductive liners further comprises; forming a first liner along a periphery of the empty opening; and forming a second liner along a periphery of the first liner, at least one of the first and second liners being insulative.

46. A method of forming an integrated assembly, comprising: forming a stack comprising alternating first and second materials; the second material being an insulative material; forming openings through the stack; forming channel-material-pillars in some of the openings and leaving other openings empty; removing the first material to leave voids; forming a first liner along a periphery of the empty openings; forming a second liner along a periphery of the first liner; and while the first and second liners remain, filling the voids with conductive material.

47. The method of claim 46 wherein at least one of the first and second liners is conductive.

48. The method of claim 46 wherein at least one of the first and second liners is insulative.

49. The method of claim 46 wherein both of the first and second liners is conductive.

50. The method of claim 46 wherein at least one of the first and second liners comprises ruthenium.

51. The method of claim 46 wherein the conductive material comprises ruthenium.

52. A method of forming an integrated assembly, comprising: forming a stack comprising alternating first and second materials; the second material being an insulative material; forming openings through the stack; forming channel-material-pillars in some of the openings and leaving other openings empty; removing the first material to leave voids; and filling the voids and the empty openings with material comprising ruthenium.

53. The method of claim 52 further comprising recessing the material comprising ruthenium in the voids.

54. The method of claim 52 further comprising forming an insulative liner in the empty openings before the filling of the empty openings.

55. The method of claim 52 further comprising forming an insulative liner in the voids before the filling of the voids.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 shows a block diagram of a prior art memory device having a memory array with memory cells.

[0017] FIG. 2 shows a schematic diagram of the prior art memory array of FIG. 1 in the form of a 3D NAND memory device.

[0018] FIG. 3 shows a cross-sectional view of the prior art 3D NAND memory device of FIG. 2 in an X-X′ direction.

[0019] FIG. 4 is a schematic diagram of a prior art NAND memory array.

[0020] FIGS. 5-12 are diagrammatic cross-sectional side views of a region of an integrated assembly at example process stages of an example method for forming an example memory array. FIG. 5A is a diagrammatic top-down view along the line 5A-5A of FIG. 5, and FIG. 5 is along the line 5-5 of FIG. 5A.

[0021] FIGS. 13-15 are diagrammatic cross-sectional side views of a region of an integrated assembly at example process stages of an example method for forming an example memory array. The process stage of FIG. 13 may follow that of FIG. 7.

[0022] FIGS. 16-20 are diagrammatic cross-sectional side views of a region of an integrated assembly at example process stages of an example method for forming an example memory array. The process stage of FIG. 16 may follow that of FIG. 7.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

[0023] Some embodiments include integrated memory (e.g., three-dimensional NAND) having ruthenium incorporated into conductive wordline material and/or incorporated into conductive gates of memory devices. Example embodiments are described with reference to FIGS. 5-20.

[0024] Referring to FIG. 5, a construction (i.e., assembly, architecture, etc.) 10 includes a stack 12 of alternating first and second levels 14 and 16. The first levels 14 comprise a first material 18, and the second levels 16 comprise a second material 20. The first and second materials 18 and 20 may be any suitable materials. In some embodiments, the first material 18 may comprise, consist essentially of, or consist of silicon nitride; and the second material 20 may comprise, consist essentially of, or consist of silicon dioxide. The second material 20 may be electrically insulative, and in some embodiments may be referred to as an insulative material (or as an insulative second material). In such embodiments, the second levels 20 may be referred to as insulative levels.

[0025] The levels 14 and 16 may be of any suitable thicknesses; and may be the same thickness as one another, or may be different thicknesses relative to one another. In some embodiments, the levels 14 and 16 may have vertical thicknesses within a range of from about 3 nanometers (nm) to about 400 nm; within a range of from about 3 nm to about 50 nm, etc.

[0026] Some of the material 18 of the first levels 14 is ultimately replaced with conductive material of wordlines/memory cell gates. Accordingly, the levels 14 may be considered correspond to be memory cell levels (or wordline levels) of a NAND configuration. The NAND configuration will include strings of memory cells (i.e., NAND strings), with the number of memory cells in the strings being determined by the number of vertically-stacked levels 14. The NAND strings may comprise any suitable number of memory cell levels. For instance, the NAND strings may have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, etc. Accordingly, the vertical stack 12 may extend outwardly beyond the illustrated region of the stack to include more vertically-stacked levels than those specifically illustrated in the diagram of FIG. 5.

[0027] The stack 12 is shown to be supported over a base 22. The base 22 may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base 22 may be referred to as a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base 22 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

[0028] A space is provided between the stack 12 and the base 22 to indicate that other components and materials may be provided between the stack 12 and the base 22. Such other components and materials may comprise additional levels of the stack, a source line level, source-side select gates (SGSs), etc.

[0029] Structures 28 are formed to extend through the stack 12.

[0030] The structures 28 include channel material structures (or channel structures) 29, which comprise channel material 30. In some embodiments, the stack 12 may be considered to be a vertically-extending stack, and the structures 29 may be considered to be vertically-extending channel material structures which pass through the stack 12. In some embodiments, the structures 29 may be referred to as channel-material-pillars.

[0031] The channel material 30 is semiconductor material; and may comprise any suitable composition or combination of compositions. For instance, the channel material 30 may comprise one or more of silicon, germanium, III/V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; with the term III/V semiconductor material referring to semiconductor materials comprising elements selected from groups III and V of the periodic table (with groups III and V being old nomenclature, and now being referred to as groups 13 and 15).

[0032] Tunneling material (sometimes referred to as gate dielectric material) 32, charge-storage material 34 and charge-blocking material 36 are between the channel material 30 and the vertically-stacked levels 16/18. The tunneling material, charge-storage material and charge-blocking material may comprise any suitable compositions or combinations of compositions.

[0033] In some embodiments, the tunneling material 32 may comprise, for example, one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, etc.

[0034] In some embodiments, the charge-storage material 34 may comprise charge-trapping materials, such as silicon nitride, silicon oxynitride, conductive nanodots, etc. In alternative embodiments, the charge-storage material 34 may be configured to include floating gate material (such as, for example, polycrystalline silicon).

[0035] In some embodiments, the charge-blocking material 36 may comprise one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, etc.

[0036] In some embodiments, the tunneling material 32 may be considered to comprise tunneling regions 15 alongside the wordline levels 14, the charge-storage material 34 may be considered to comprise charge-storage regions 17 alongside the wordline levels 14, and the charge-blocking material 36 may be considered to comprise charge-blocking regions 19 alongside the wordline levels 14.

[0037] In the illustrated embodiment, the channel material 30 is configured as annular rings (visible relative to FIG. 5A) within each of the structures 28. Insulative material 38 fills such annular rings. The insulative material 38 may comprise any suitable composition(s); and may, for example, comprise, consist essentially of, or consist of silicon dioxide. The illustrated channel structures 29 may be considered to comprise hollow channel configurations, in that the insulative material 38 is provided within “hollows” in the annular ring-shaped channel configurations. In other embodiments (not shown), the channel material may be configured as a solid pillar configuration.

[0038] The structures 28 may be considered to comprise all of the materials 30, 32, 34, 36 and 38 in combination. The top view of FIG. 5A shows that the structures 28 may be arranged in a hexagonally-packed pattern.

[0039] In some embodiments, formation of the structures 28 may be considered to include forming the tunneling material 32 adjacent the channel material 30 of the channel-material-pillars 29, forming the charge-storage material 34 adjacent the tunneling material 32, and forming the charge-blocking material 36 adjacent the charge-storage material 34.

[0040] Slits (trenches) 40 are formed to extend through the stack 12.

[0041] Referring to FIG. 6, the first material 18 (FIG. 5) of the first levels 14 is removed to form voids (cavities) 42 along the first levels 14.

[0042] Referring to FIG. 7, dielectric barrier material 44 is formed within the voids 42 to line the voids.

[0043] The dielectric barrier material 44 may comprise any suitable composition(s); and in some embodiments may comprise one or more high-k materials (with the term high-k meaning a dielectric constant greater than that of silicon dioxide). Example compositions which may be incorporated into the dielectric barrier material are hafnium oxide, zirconium oxide, aluminum oxide, hafnium silicate, zirconium silicate, titanium oxide, gadolinium oxide, niobium oxide, tantalum oxide, etc.

[0044] Referring to FIG. 8, first conductive material 46 is formed within the voids 42 and over the dielectric barrier material 44 (i.e., is formed within the voids 42 after such voids are lined with the dielectric barrier material 44). The first conductive material 46 may comprise, consist essentially of, or consist of ruthenium.

[0045] The ruthenium-containing material 46 may advantageously adhere well to the high-k dielectric material of the dielectric barrier material 44.

[0046] In the shown embodiment, the ruthenium-containing material 46 only partially fills the voids 46, and accordingly lines the voids. In some embodiments, the dielectric barrier material 44 may be considered to form first liners 43, and the ruthenium-containing material 46 may be considered to form second liners 45 which are over and directly against the first liners.

[0047] Referring to FIG. 9, conductive core material 48 is formed within the voids 42, and fills the voids. The conductive core material 48 is formed over and directly against the ruthenium-containing material 46; and in some embodiments may be considered to be formed directly against the second liners (i.e., the ruthenium-containing liners) 45.

[0048] The conductive core material 48 may comprise any suitable electrically conductive composition(s), such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the conductive core material 48 does not comprise ruthenium. In some embodiments, the conductive core material 48 may comprise, consist essentially of, or consist of one or more metals; and may, for example, comprise, consist essentially of, or consist of one or both of tungsten and molybdenum.

[0049] Referring to FIG. 10, the conductive core material 48 is recessed within the voids 42 in locations along the slits 40 with a first etch (e.g., a wet etch utilizing ammonium hydroxide). In some embodiments, the conductive core material 48 may be removed selectively relative to the ruthenium-containing material 46. For purposes of interpreting this disclosure and the claims that follow, a first material is considered to be removed selectively relative to a second material if the first material is removed under conditions which etch the first material faster than the second material. This can include, but is not limited to, applications having etches which are 100% selective for the first material relative to the second material.

[0050] Referring to FIG. 11, the ruthenium-containing material 46 is recessed within the voids 42 in locations along the slits 40 with a second etch which is different from the first etch of FIG. 10. In some embodiments, the second etch may utilize an oxidative plasma; such as, for example, a plasma utilizing one or both of O.sub.2 and O.sub.3.

[0051] Referring to FIG. 12, insulative material 50 is formed within the slits 40. The insulative material 50 may comprise any suitable composition(s), and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

[0052] The levels 14 are conductive levels at the processing stage of FIG. 12; and may be referred to as wordline levels, memory cell levels, etc.

[0053] The insulative levels 16 and wordline levels 14 alternate with one another at the processing stage of FIG. 12, and together form a vertical stack 52. The structures 28 extend through the vertical stack 52. Accordingly, the channel structures 29 extend through the stack 52.

[0054] The conductive materials 48 and 46 may be together considered to form conductive wordline material 54 (which may be also referred to as conductive gate material).

[0055] The wordline levels 14 comprise conductive gates 56 (only some of which are labeled) adjacent the channel material structures 29. The conductive gates 56 may be considered to comprise the conductive gate material 54, with such conductive gate material including ruthenium from the ruthenium-containing material 46. The conductive gates 56, together with regions of the dielectric-barrier material 44, charge-blocking material 36, charge-storage material 34, tunneling material 32 and channel material 30 form memory cells 58. Such memory cells are incorporated into a three-dimensional NAND memory array 60 analogous to the NAND memory arrays described above with reference to FIGS. 1-4. The memory cells 58 are all substantially identical to one another (with the term “substantially identical” meaning identical to within reasonable tolerances of fabrication and measurement).

[0056] In operation, the charge-storage material 34 may be configured to store information in the memory cells 58. The value (with the term “value” representing one bit or multiple bits) of information stored in an individual memory cell may be based on the amount of charge (e.g., the number of electrons) stored in a charge-storage region of the memory cell. The amount of charge within an individual charge-storage region may be controlled (e.g., increased or decreased), at least in part, based on the value of voltage applied to an associated gate 56, and/or based on the value of voltage applied to an associated channel material 30.

[0057] The tunneling material 32 forms tunneling regions of the memory cells 58. Such tunneling regions may be configured to allow desired migration (e.g., transportation) of charge (e.g., electrons) between the charge-storage material 34 and the channel material 30. The tunneling regions may be configured (i.e., engineered) to achieve a selected criterion, such as, for example, but not limited to, an equivalent oxide thickness (EOT). The EOT quantifies the electrical properties of the tunneling regions (e.g., capacitance) in terms of a representative physical thickness. For example, EOT may be defined as the thickness of a theoretical silicon dioxide layer that would be required to have the same capacitance density as a given dielectric, ignoring leakage current and reliability considerations.

[0058] The charge-blocking material 36 is adjacent to the charge-storage material 34, and may provide a mechanism to block charge from flowing from the charge-storage material 34 to the associated gates 56.

[0059] The dielectric-barrier material 44 is provided between the charge-blocking material 36 and the associated gates 56, and may be utilized to inhibit back-tunneling of charge carriers from the gates 56 toward the charge-storage material 34. In some embodiments, the dielectric-barrier material 44 may be considered to form dielectric-barrier regions within the memory cells 58.

[0060] In some embodiments, the memory cells 58 may be considered to comprise tunneling regions 15, charge-storage regions 17, and charge-blocking regions 19. The charge-storage regions 17 are between the conductive wordline material 54 and the channel structures 29, and the charge-blocking regions 19 are between the charge-storage regions 17 and the conductive wordline material 54.

[0061] An advantage of including the ruthenium-containing material 46 within the conductive wordline material 54 is that such may reduce back tunneling from the gates 56 to the charge-storage regions 17 as compared to conventional configurations lacking the ruthenium-containing material. Another advantage of including the ruthenium-containing material may be that such provides lower sheet resistance as compared to conventional materials, which may enable the conductive wordlines of levels 14 to be formed thinner than conventional wordlines; improving scalability as compared to conventional architectures.

[0062] In some embodiments, the conductive core material 48 of FIG. 12 may be considered to have an outer periphery 49. The ruthenium-containing material 46 may be considered to be a second conductive material adjacent the outer periphery 49 of the conductive core material 48.

[0063] Another example embodiment method for fabricating example memory cells is described with reference to FIGS. 13-15.

[0064] Referring to FIG. 13, the assembly 10 is shown at a process stage which may follow that of FIG. 7. The ruthenium-containing material 46 entirely fills the voids 42.

[0065] Referring to FIG. 14, the ruthenium-containing material 46 is removed from within the slits 40, and is recessed within the voids 42 in locations adjacent the slits 40. The recessing of the ruthenium-containing material may utilize an oxidative plasma of the type described above with reference to FIG. 11.

[0066] Referring to FIG. 15, the insulative material 50 is formed within the slits 40.

[0067] The assembly 10 of FIG. 15 includes the stack 52 of alternating conductive wordline levels 14 and insulative levels 16. The conductive wordline levels 14 comprise conductive wordline material (conductive gate material) 54 which comprises only the ruthenium-containing material 46. In some embodiments, the conductive wordline material (conductive gate material) 54 may comprise, consist essentially of, or consist of ruthenium.

[0068] The conductive wordline levels 14 are incorporated into a NAND memory array 60 analogous to that described above with reference to FIG. 12. The memory array includes a plurality of memory cells 58. Regions of the conductive material 54 form gates 56 of the memory cells.

[0069] The utilization of wordline material 54 comprising only ruthenium (i.e., consisting of ruthenium) may enable sheet resistance of the wordline levels to be substantially reduced relative to conventional NAND configurations, which may enable higher integration to be achieved utilizing the NAND memory configurations described herein as compared to conventional NAND memory configurations.

[0070] Another example embodiment method for fabricating example memory cells is described with reference to FIGS. 16-20.

[0071] Referring to FIG. 16, the assembly 10 is shown at a process stage which may follow that of FIG. 7. The ruthenium-containing material 46 lines the voids 42, and another conductive material 62 is formed to further line the voids. The conductive material 62 may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of one or more metal nitrides (e.g., titanium nitride, tungsten nitride, etc.).

[0072] Referring to FIG. 17, the conductive core material 48 is formed over the conductive material 62, and fills the voids 42. In some embodiments, the conductive material 62 may be referred to as a second conductive material which is directly adjacent the conductive core material, and the conductive material 46 may referred to as a third conductive material which is directly adjacent the second conductive material. Alternatively, the conductive material 46 may be referred to as a first conductive material and the conductive material 62 may referred to as a second conductive material. In some embodiments, the conductive material 46 may be considered to be a first conductive material having a first outer surface 61, and the material 62 may be considered to be a second conductive material which is formed adjacent to the first outer surface 61. The second conductive material 62 may be considered to comprise a second outer surface 63, and the conductive core material may be considered to be formed adjacent such second outer surface.

[0073] Referring to FIG. 18, the conductive materials 48 and 62 are recessed within the voids 42 in locations adjacent the slits 40 utilizing a first etch. Such recessing may utilize the same processing described above relative to FIG. 10 (e.g., a wet etch), and may utilize etching which is selective for materials 48 and 62 relative to the ruthenium-containing material 46.

[0074] Referring to FIG. 19, the ruthenium-containing material 46 is recessed with a second etch analogous to that described above with reference to FIG. 11 (e.g., an oxidative plasma etch).

[0075] Referring to FIG. 20, the insulative material 50 is formed within the slits 40.

[0076] The assembly 10 of FIG. 20 includes the stack 52 of alternating conductive wordline levels 14 and insulative levels 16. The conductive wordline levels 14 comprise conductive wordline material (conductive gate material) 54 which comprises the three conductive materials 46, 48 and 62; with the material 46 being a ruthenium-containing material.

[0077] The conductive wordline levels 14 are incorporated into a NAND memory array 60 analogous to that described above with reference to FIG. 12. The memory array includes a plurality of memory cells 58. Regions of the conductive material 54 form gates 56 of the memory cells.

[0078] The assemblies and structures discussed above may be utilized within integrated circuits (with the term “integrated circuit” meaning an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0079] Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0080] The terms “dielectric” and “insulative” may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term “dielectric” in some instances, and the term “insulative” (or “electrically insulative”) in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

[0081] The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The descriptions provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.

[0082] The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings.

[0083] When a structure is referred to above as being “on”, “adjacent” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on”, “directly adjacent” or “directly against” another structure, there are no intervening structures present. The terms “directly under”, “directly over”, etc., do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

[0084] Structures (e.g., layers, materials, etc.) may be referred to as “extending vertically” to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

[0085] Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material.

[0086] Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material.

[0087] Some embodiments include a method of forming an integrated assembly. A stack is formed to comprise alternating first and second materials. The second material is an insulative material. Channel-material-pillars are formed to extend through the stack. The first material is removed to leave voids. Conductive gate material is formed within the voids. The conductive gate material comprises ruthenium.

[0088] In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.