Enhancement mode III-nitride devices having an Al.SUB.1.-.SUB.x.Si.SUB.x.O gate insulator

Abstract

A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous Al.sub.1-xSi.sub.xO layer with 0.2<x<0.8; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.

Claims

1. A transistor comprising: a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous Al.sub.1-xSi.sub.xO layer with 0.2<x<0.8, wherein the amorphous Al.sub.1-xSi.sub.xO layer includes a nanocrystalline Al.sub.1-xSi.sub.xO portion on a side adjacent the III-N channel layer; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.

2. The transistor of claim 1, wherein a thickness of the amorphous Al.sub.1-xSi.sub.xO layer is between about 1 nm and 100 nm.

3. The transistor of claim 1, wherein the gate electrode comprises a semiconductor material.

4. The transistor of claim 1, wherein the gate electrode comprises titanium nitride (TiN), indium nitride (InN), p-type poly silicon, tungsten nitride (WN), or indium tin oxide (ITO).

5. The transistor of claim 4, wherein a composition of the gate electrode is selected such that at room temperature, a threshold voltage of the transistor is greater than 2 V and a threshold voltage hysteresis is less than 0.5 V.

6. The transistor of claim 5, wherein the transistor is configured such that in operation, an off state blocking voltage of the transistor is greater than 600V.

7. The transistor of claim 1, wherein a recess in a first portion of the transistor extends through the insulator layer and the III-N barrier layer.

8. The transistor of claim 7, wherein the gate insulator is at least partially in the recess and contacts the III-N channel layer in the recess.

9. The transistor of claim 8, wherein the gate electrode is at least partially in the recess.

10. The transistor of claim 1, wherein a thickness of the nanocrystalline Al.sub.1-xSi.sub.xO portion is less than 40% of a thickness of the amorphous Al.sub.1-xSi.sub.xO layer.

11. The transistor of claim 1, wherein the amorphous Al.sub.1-xSi.sub.xO layer includes nitrogen.

12. A method of fabricating a III-N device, comprising: providing a material structure comprising a III-N barrier layer on a III-N channel layer, and an insulator layer on the III-N barrier layer; forming a recess in a first portion of the device, the forming of the recess comprising removing the insulator layer and the III-N barrier layer in the first portion of the device to expose the III-N channel layer in the first portion of the device; forming an amorphous Al.sub.1-xSi.sub.xO layer at least partially in the recess, wherein the amorphous Al.sub.1-xSi.sub.xO layer is formed over the channel layer in the first portion of the device; and forming a gate electrode on the amorphous Al.sub.1-xSi.sub.xO layer at least partially in the recess, wherein the gate electrode comprises a compound semiconductor material and a metal; wherein forming the amorphous Al.sub.1-xSi.sub.xO layer includes forming a nanocrystalline Al.sub.1-xSi.sub.xO portion on a side adjacent the III-N channel layer.

13. The method of claim 12, wherein the forming of the amorphous Al.sub.1-xSi.sub.xO layer is performed using a metal organic chemical vapor deposition (MOCVD) growth reactor.

14. The method of claim 12, further comprising annealing the III-N device at an elevated temperature.

15. The method of claim 14, wherein the forming of the amorphous Al.sub.1-xSi.sub.xO layer and the annealing of the III-N device is performed sequentially without exposure to air in a MOCVD growth reactor.

16. The method of claim 14, wherein the annealing of the III-N device is performed at a temperature greater than 800° C.

17. The method of claim 12, wherein the gate electrode includes titanium nitride (TiN), indium nitride (InN), p-type poly silicon, tungsten nitride (WN), or indium tin oxide (ITO).

18. The method of claim 12, further comprising annealing the III-N device in forming gas after the forming of the gate electrode.

19. The method of claim 18, wherein the annealing is performed at a temperature greater than 350° C.

20. The method of claim 12, wherein the forming of the amorphous Al.sub.1-xSi.sub.xO layer is performed at a deposition temperature greater than 500° C.

21. The method of claim 12, wherein a thickness of the nanocrystalline Al.sub.1-xSi.sub.xO portion is less than 40% of a thickness of the amorphous Al.sub.1-xSi.sub.xO layer.

22. The method of claim 12, wherein forming the amorphous Al.sub.1-xSi.sub.xO layer includes incorporating nitrogen into the amorphous Al.sub.1-xSi.sub.xO layer to form an Al.sub.1-xSi.sub.xON layer.

Description

DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a cross-sectional view of an example of a III-N device.

(2) FIGS. 2A-2B are flow diagrams of an example of a partial process for forming a III-N device.

(3) FIG. 3A-3B are flow diagrams of an example of a partial process for forming a III-N device.

(4) FIG. 4 is a cross-sectional view of an example of a III-N device.

(5) FIG. 5 is a cross-sectional view of another example of a III-N device.

(6) FIG. 6 is a cross-sectional view of another example of a III-N device.

(7) FIG. 7 is a cross-sectional view of yet another example of a III-N device.

(8) FIG. 8 is diagram showing Flat-Band voltage of gate insulator materials with Al.sub.1-xSi.sub.xO and Al.sub.1-xSi.sub.xN compared to gate electrode materials with different work functions (eV).

(9) FIG. 9A is a diagram showing low field voltage (V.sub.LF) of a III-N device with Al.sub.1-xSi.sub.xO and Al.sub.1-xSi.sub.xN for varying Si composition.

(10) FIG. 9B indicates the measurement definition of V.sub.LF from FIG. 9A.

(11) FIG. 10 shows change in threshold voltage and hysteresis for different compositions of Al.sub.1-xSi.sub.xO.

(12) Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

(13) Described herein are enhancement-mode III-N devices, and methods for forming the devices. The devices include a III-N heterostructure with a two-dimensional electron gas (2DEG) channel therein. A recess is formed in the III-N material structure in a gate region of the device. An amorphous Al.sub.1-xSi.sub.xO gate insulator layer is formed in the recess, and a gate electrode is formed on the gate insulator layer. As described in detail below, the amorphous Al.sub.1-xSi.sub.xO gate insulator layer allows for higher threshold voltages with less hysteresis and substantially improved reliability as compared to other enhancement-mode III-N transistors which utilize a gate insulator.

(14) FIG. 1 is a cross sectional view of an example III-N device 100. The III-N device 100 can be a III-N transistor or switch, and in particular a high-voltage III-N enhancement-mode field effect transistor.

(15) The III-N device 100 includes a substrate layer 110. The substrate layer 110 can be a substrate made of, for example, Silicon (Si), Silicon Carbide (SiC), Sapphire (Al.sub.2O.sub.3), Aluminum Nitride (AlN), Gallium Nitride (GaN), or any other suitable substrate upon which III-N materials can be formed.

(16) A buffer layer 112 is formed on the substrate layer 110. The buffer layer 112 can be a III-N buffer layer, e.g., a GaN layer, an Al.sub.xGa.sub.1-xN layer, or the like. The buffer layer 112 can be rendered insulating or substantially free of n-type mobile carriers, e.g., by including dislocations or point defects in the buffer layer 112, and/or by doping the buffer layer 112 with compensating elements, e.g., Iron (Fe), Carbon (C), and/or Magnesium (Mg). The buffer layer 112 can have a substantially uniform composition throughout the layer. In some implementations, one or more compositions vary throughout the buffer layer 112. For example, the buffer layer 112 can be graded, e.g., by grading an Al composition in the buffer layer 112. In some cases, the buffer layer 112 is substantially thicker than any of the other III-N layers in the III-N device 100.

(17) The III-N device 100 includes a channel layer 114 formed on the buffer layer 112. The channel layer 114 can be a III-N layer, e.g., an undoped GaN layer or a slightly or unintentionally doped GaN layer. In some examples, the channel layer 114 is a III-N layer without Al composition, for example GaN or In.sub.zGa.sub.1-zN.

(18) A barrier layer 116 is formed on the channel layer 114. The barrier layer 116 and the channel layer 114 can have different compositions or III-N materials from one another. The compositions or III-N materials are selected such that the barrier layer 116 can have a larger bandgap than the channel layer 114. In some examples, the barrier layer 116 is an Al-based III-N layer, e.g., an Al.sub.xGa.sub.1-xN layer, an Al.sub.yIn.sub.1-yN layer, or an AlInGaN layer. The barrier layer can be an undoped GaN layer. The barrier layer 116 can be n-doped or can contain no significant concentration of doping impurities. In the case that the barrier layer 116 is undoped, polarization fields can exist between the channel layer 114 and the barrier layer 116, such that a fixed charge is induced at or adjacent to the interface between layers 114 and 116.

(19) The energy band edge discontinuity in the conduction band of the III-N material structure, resulting from the bandgap difference and/or the difference in electron affinity between layers 114 and 116, in combination with the doping of the barrier layer 116 or introduced polarization, can induce a conductive channel 119 in the channel layer 114, e.g., near an interface between the channel layer 114 and the barrier layer 116, as illustrated in FIG. 1. The conductive channel 119 can include a 2-dimensional electron gas (2DEG) channel, e.g., between source contact 121 and gate contact 123, as well as between gate contact 123 and drain contact 122. As shown in FIG. 1, when the device 100 is in the OFF state (i.e., the gate contact 123 is biased relative to the source contact 121 at a voltage lower than the device threshold voltage), the conductive channel 119 is depleted of mobile charge below the gate electrode 123, and so the 2DEG is discontinuous between the source contact 121 and the drain contact 122. When the device 100 is in the ON state (i.e., the gate contact 123 is biased relative to the source contact 121 at a voltage higher than the device threshold voltage), the conductive channel 119 below the gate electrode 123 is populated with mobile charge (not shown in FIG. 1), and the 2DEG is continuous from the source all the way to the drain. In some implementations, the source and drain contacts 121 and 122, respectively, form ohmic contacts electrically coupled to, electrically connected to, or contacting the 2DEG channel. The gate contact 123 can modulate a portion of the 2DEG channel in a gate region, e.g., directly beneath the gate contact 123.

(20) The III-N device 100 can also include an insulator layer 118. The insulator layer 118 can be a passivation layer, preventing or suppressing dispersion by preventing or suppressing voltage fluctuations at the uppermost III-N surface. The insulator layer 118 can be made of Si.sub.xN.sub.y, Al.sub.2O.sub.3, SiO.sub.2, Al.sub.xSi.sub.yN, Al.sub.xSi.sub.yO, Al.sub.xSi.sub.yON or the like, and can be formed by metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), sputtering, atomic layer deposition (ALD), high density chemical vapor deposition, or any suitable deposition process. In a particular example, the insulator layer 118 is a Silicon Nitride (Si.sub.xN.sub.y) layer formed by MOCVD.

(21) The source contact 121, e.g., a source electrode, and the drain contact 122, e.g., a drain electrode, can be formed by metal stacks in contact with one of the III-N layers, e.g., the channel layer 114 or the barrier layer 116. A recess can be formed in the III-N layers to allow for improved contact of the metal stacks to the 2-DEG channel. The metal stacks can be Ti/Al/Ni/Au, Ti/Al, or the like. The source contact 121 and the drain contact 122 can be formed by metal evaporation and post-deposition annealing processes. Other ohmic contact processes can also be used including sputtering and dry etch processing.

(22) To shape the electric field in a high-voltage-field region of the III-N device 100, a recess or trench 124 is formed to reduce a peak electric field and increase a device breakdown voltage as well as the device threshold voltage, thereby allowing for high voltage operation. The recess 124 can also cause the device 100 to operate in enhancement mode (i.e., to be an E-mode device). The recess 124 can be formed by removing all of the insulator layer 118 and part or all of the barrier layer 116 in a trench shape. Part of the channel layer 114 may also be removed during the forming of the recess 124. The residual damage in the channel layer, as well as the depth and shape of the recess, permit achieving enhancement mode operation along with a low device on-resistance R.sub.on, as further described below.

(23) In some implementations, dry etching techniques, e.g., plasma etching, digital plasma etching, or reactive ion etching (RIE), are used to form a recess structure. The dry etching techniques can cause ion bombardment damage, which can reduce the channel carrier mobility. These techniques also have low etching selectivity with respect to III-Nitride materials. That is, it is difficult to selectively etch one composition of III-Nitride materials without substantially etching a different composition of III-Nitride materials using these techniques. Furthermore, it can be difficult to recover a surface with ion bombardment damage. Etching selectivity can also be important for III-N epitaxy layers, as each layer grown epitaxially on a substrate has thickness and composition variations from a center of a wafer to an edge of the wafer. In some cases, the dry etching techniques have little etching selectivity between a barrier layer and a channel layer. Thus, large threshold voltage variations can be caused by different etching depths.

(24) To realize an enhancement-mode transistor using a III-N device structure, it can be important to control etching depth in the recess. A device having the III-N material structure of device 100 but lacking the recess 124 typically operates in depletion mode (i.e., negative device threshold voltage). Including a recess 124 in the III-N material structure in the gate region of the device causes the device threshold voltage to shift to a more positive value. If the etching depth is not deep enough, such that the shift in threshold voltage is small, the III-N device may still remain a depletion mode device, exhibiting normally-on characteristics. If the etching depth is too deep and extends into the channel layer, current communications between the conductive channel underneath gate contact and conductive channels in the device access regions (i.e., the regions between the source and gate and between the gate and drain) can be cut off, even when the device is biased in the ON state. In this case, the III-N device may have a low current density or may not be operational in the ON state, even though normally-off E-mode operation can be realized. Although dry etching rates can be calibrated to reasonable accuracy, variations in barrier layer thickness between different wafers due to growth condition fluctuations of III-N epitaxial layers, as well as variations across a single wafer, may cause low manufacturing yield.

(25) Recess etch cross-sections are typically either rectangular or trapezoidal, i.e., recesses either have vertical sidewalls or sloping sidewalls, but not both. In a device such as device 100, having vertical sidewalls throughout the recess is not desirable, since conformal deposition of defect-free gate dielectric and gate metal can be challenging in III-N device structures having recesses with vertically shaped sidewalls.

(26) As indicated in FIG. 1, the recess 124 can have vertical sidewalls in the barrier layer 116 and slanted sidewalls in the insulator layer 118. The recess 124 can also have slanted sidewalls in the barrier layer 116 (not shown). A top surface of the channel layer 114 is exposed in the recess 124. The recess 124 extends from the top surface of the channel layer 114 through the barrier layer 116 and the insulator layer 118 to a top surface of the insulator layer 118.

(27) A gate insulator 120, e.g., a gate insulator layer or a gate dielectric layer, is grown or deposited conformally at least partially in the recess 124. The gate insulator 120 can be on the top surface of the channel layer 114. The gate insulator 120 can extend at least from the top surface of the channel layer 114 to the top surface of the insulator layer 118. The gate insulator 120 can have a similar profile as the recess sidewalls in the barrier layer 116 and the insulator layer 118.

(28) The gate insulator 120 can, for example, be formed of or include Aluminum Oxide (Al.sub.2O.sub.3), Silicon Dioxide (SiO.sub.2), Si.sub.xN.sub.y, Al.sub.1-xSi.sub.xON, or any other wide bandgap insulator. In some examples, the gate insulator 120 is an Al.sub.1-xSi.sub.xO layer, e.g., an amorphous Al.sub.1-xSi.sub.xO layer or a polycrystalline Al.sub.1-xSi.sub.xO layer, where x and (1−x) represent the relative fractional compositions of non-oxygen elements in the Al.sub.1-xSi.sub.xO layer. That is, (1−x) is the percent of non-oxygen elements in the Al.sub.1-xSi.sub.xO layer that are constituted by aluminum, x is the percent of non-oxygen elements in the Al.sub.1-xSi.sub.xO layer that are constituted by silicon, and (1−x)/x is the ratio of aluminum to silicon in the Al.sub.1-xSi.sub.xO layer. In a particular example, as discussed in further detail below, the gate insulator 120 includes an amorphous Al.sub.1-xSi.sub.xO layer that provides high threshold voltage and low gate leakage. In some implementations, an Al.sub.1-xSi.sub.xO layer also includes a low concentration of nitrogen. That is, during the formation of Al.sub.1-xSi.sub.xO layers, a low concentration of nitrogen can be incorporated into the layer, where the nitrogen concentration is substantially lower than the concentrations of Al, Si, and O in the layer. An Al.sub.1-xSi.sub.xO gate insulator layer can have improved enhancement mode device characteristics compared to other gate insulator layers, for example SiN, Al.sub.2O.sub.3, SiO.sub.2, or Al.sub.1-xSi.sub.xN. These and other advantages will be described in detail below. The amorphous Al.sub.1-xSi.sub.xO layer can have a thickness of between about 1 nm and 100 nm, for example between 1 nm and 60 nm. A post-deposition oxygen anneal can be performed on the gate insulator 120. The anneal process can be performed in a MOCVD growth reactor. The anneal process can be performed without exposure to air between the gate insulator deposition in a MOCVD growth reactor. The temperature of the anneal can be greater than 800° C. The time of the anneal can be for 10 min, or 20 min, or more.

(29) In some implementations, the gate insulator 120 is a ternary compound such as an Al.sub.1-xA.sub.xO layer, where A is an element from the fourth group of the periodic table, e.g., an amorphous Al.sub.1-xSi.sub.xO layer or a polycrystalline Al.sub.1-xSi.sub.xO layer. Gate insulator 120 could be a wideband gap quaternary insulator such as Al.sub.1-xSi.sub.xON. The gate insulator 120 could also be a wideband gap quaternary insulator such as Al.sub.xM.sub.yA.sub.zO, where M is a transition metal element, A is an element of the fourth group of the periodic table, and x, y, and z are the relative fractional compositions of non-oxygen elements in the Al.sub.xM.sub.yA.sub.zO layer. The quaternary insulator reduces to the ternary when either y or z is equal to zero. Although amorphous layers may be preferable, other mixed phase matrices could also be used.

(30) Next, the gate contact 123, e.g., a gate electrode, is formed conformally on the gate insulator 120 at least partially in the recess 124. Similarly to the gate insulator 120, the portion of the gate contact 123 that is in the recess and adjacent to the barrier layer 116 can be oriented vertically, and the portion of the gate contact 123 that is in the recess and adjacent to the insulator layer 118 can be slanted. In some implementations, the gate contact 123 includes extending portions that are outside the recess 124 and extend towards the source contact 121 and/or the drain contact 122, respectively. The extending portions are separated from the source contact 121 and the drain contact 122, respectively. The extending portions of the gate contact 123 can function as field plates for the III-N device 100. In some examples, the extending portions of the gate contact at least partially include the slanted portions of the gate contact and can function as slant field plates, which may improve device performance.

(31) The gate contact 123 can be formed as metal stacks, e.g., titanium/aluminum (Ti/Al) or nickel/gold (Ni/Au), and can be deposited by metal evaporation or sputtering or chemical vapor deposition. The gate contact 123 may alternatively be another conductive material or material stack including one or more materials having a large work function, such as a semiconductor material having a large work function (e.g., p-type poly-silicon, indium tin oxide, tungsten nitride, indium nitride, or titanium nitride). A post-gate deposition annealing process may optionally be performed after deposition of the gate contact 123. The post-gate deposition anneal may be performed in a gas ambient including oxygen or a forming gas (H.sub.2+N.sub.2). The post gate deposition anneal temperature can be greater than 300° C., or greater than 400° C. Finally, the gate contact 123 can be used as an etch mask to etch the gate insulator 120, such that the gate insulator 120 remains directly beneath the gate contact 123 but is etched away, or partially etched away (not shown), everywhere else.

(32) As illustrated in FIG. 1, when 0V (or any voltage less than the device threshold voltage) is applied to the gate contact 123 relative to the source contact 121, the conductive channel 119 is discontinuous in a region of the channel layer 114 directly beneath the recess 124 in the gate region of the III-N device 100. As a consequence of the discontinuity of the conductive channel 119, the device channel between the source and drain contacts is not conductive when 0 V is applied to the gate contact 123 relative to the source contact 121, but is readily conductive when a sufficiently positive voltage, e.g., above a device threshold voltage, is applied to the gate contact 123 relative to the source contact 121. Thus, the III-N device 100 can function as a high-voltage enhancement-mode device for high voltage applications. The III-N device 100 can be a transistor, a bidirectional switch or four quadrant switch (FQS), and/or any suitable semiconductor device.

(33) FIGS. 2A-2B and FIGS. 3A-3B show example processes 200A-200B and 300A-300B for forming a III-N device. The processes 200A-200B and 300A-300B can be utilized to form the III-N device 100, 400, 500 and 600 of FIG. 1, FIG. 4, FIG. 5 and FIG. 6 respectively.

(34) Referring to FIG. 2A, the process 200A includes forming a buffer layer on a substrate (202). The buffer layer and the substrate can be the buffer layer 112 and the substrate layer 110 of FIG. 1, respectively. The substrate can be a silicon wafer. The buffer layer can be formed by either directly growing the buffer layer on the substrate, or alternatively by growing the buffer layer on a first substrate, detaching the buffer layer from the first substrate, and bonding the buffer layer to the substrate. As noted above, forming the buffer layer (step 202) can also include doping the buffer layer with compensating elements.

(35) Next, a III-N channel layer is formed on the buffer layer (step 204). The III-N channel layer can be the channel layer 114 of FIG. 1. The III-N channel layer can be an undoped III-N layer, e.g., an undoped GaN layer. In a particular example, the III-N channel layer is an undoped GaN layer and is substantially free of Al.

(36) A III-N barrier layer is then formed on the channel layer (step 206). The III-N barrier layer can be the barrier layer 116 of FIG. 1. The III-N barrier layer includes different composition or III-N materials from the channel layer, such that the barrier layer has a larger bandgap than the channel layer and a conductive channel, e.g., a 2DEG channel, can be induced in the channel layer. In some examples, the barrier layer is an Al.sub.xGa.sub.1-xN layer. The barrier layer can have a thickness of about 30 nm. In a particular implementation, the III-N barrier layer is an Al.sub.xIn.sub.yGa.sub.1-x-yN layer, where x and y are the respective aluminum and indium fractional compositions, x+y is the gallium fractional composition, 0<x≤1, 0≤y<1, and 0≤x+y<1. In another embodiment, the III-N barrier layer can have an initial composition of Al.sub.xGa.sub.1-xN and a final composition of GaN and is substantially free of Al at the top surface of the III-N barrier layer.

(37) Next, an insulator layer is formed on the barrier layer (step 208). The insulator layer can be the insulator layer 118 of FIG. 1. As noted above, the insulator layer can be made of Si.sub.xN.sub.y, Al.sub.2O.sub.3, SiO.sub.2, Al.sub.xSi.sub.yN, Al.sub.xSi.sub.yO, Al.sub.xSi.sub.yON or the like, and can be deposited by MOCVD, LPCVD, PECVD, CVD, HDPCVD, sputtering, activated reactive sputtering, ALD, plasma assisted ALD, or any suitable deposition process. In a particular example, the insulator layer is a SiN.sub.x layer formed by MOCVD.

(38) Process 200A, as shown in FIG. 2A can have an optional step (210) to completely remove or partially remove the insulator layer in the active area of the device. The active area of the device is the area between the source contact 121 and the drain contact 122 as shown in FIG. 1. Partially removing the insulator layer can include exposing the top surface of the III-N barrier layer in a first region of the device which is 2 times greater or up to 50 times greater than the width of the recess 124 of FIG. 1. Partially removing the insulator layer (118) can define region 126, shown in FIG. 5.

(39) A recess is then formed to expose a top surface of the channel layer (step 212). The recess can be the recess 124 of FIG. 1. Formation of the recess can include using a wet etching technique or a dry etching technique or a combination of dry and wet etching techniques. The formed recess can have vertical or slanted sidewalls in the barrier layer 116 and slanted sidewalls in the insulator layer 118. The barrier layer can be removed in the recess region and the top surface of the channel layer 114 can be exposed in the recess. In some implementations, the recess 124 can extend into the channel layer 114. For example, the recess 124 can extend less than 10 nm into the channel layer 114. The recess 124 can extend from the top surface of the channel layer 114 through the barrier layer 116 and the insulator layer 118 to a top surface of the insulator layer. In some examples, the conductive channel is discontinuous in a region of the channel layer directly beneath the recess when no voltages are applied to any of the device electrodes (e.g., the source, the gate, or the drain).

(40) Referring now to FIG. 2B, process 200B can be performed as an alternative to process 200A. Process 200B can include the same process steps as process 200A, but without performing the process step of forming the insulating layer 208 after forming the barrier layer of process steps 206 and before forming the trench of process step 212. In some implementations of process 200B, forming the III-N barrier layer (206) includes forming an initial composition of Al.sub.xGa.sub.1-xN and a final composition of GaN. The final composition of GaN can act as a GaN cap to prevent oxidation of the III-N barrier layer and to suppress the formation of surface traps as a result of not forming the insulating layer 208 over the III-N barrier layer 206. An example device 600 formed using process 200B is illustrated in FIG. 6 and is described in further detail below.

(41) Referring now to FIG. 3A, process 300A is described below. Process 300A can be performed after process 200A and can be used to form the device 100 of FIG. 1. A gate insulator is formed on the top surface of the channel layer (step 302). The gate insulator can be the gate insulator 120 of FIG. 1. The gate insulator is formed conformally at least partially in the recess 124. The gate insulator can be in direct contact with the top surface of the channel layer 114 without barrier material there-between. The portion of the gate insulator contacting the barrier layer 116 can have the same profile as the recess in the barrier layer, and the portion of the gate insulator contacting the insulator layer can have the same profile as the recess in the insulator layer.

(42) In some implementations, to achieve high gate bias and low gate leakage, an amorphous aluminum silicon oxide (e.g., Al.sub.1-xSi.sub.xO which may optionally include a low concentration of nitrogen) layer is grown as the gate insulator. The III-N device with the amorphous Al.sub.1-xSi.sub.xO layer as the gate insulator can achieve a high breakdown electrical field, low interface traps, and high temperature stability, as discussed in further detail below. The III-N device with an Al.sub.1-xSi.sub.xO gate insulator in combination with a gate electrode formed of a semiconductor material such as TiN or InN can increase the threshold voltage of a III-N device compared to similar devices that include a Al.sub.2O.sub.3 gate insulator or a Al.sub.xSi.sub.yN gate insulator.

(43) The amorphous Al.sub.1-xSi.sub.xO layer can be grown by using CVD, LPCVD, MOCVD, molecular beam epitaxy (MBE), sputter deposition, or any suitable deposition process. In some examples, the grown amorphous Al.sub.1-xSi.sub.xO layer has a thickness of between 1 nm and 100 nm, for example between about 1 nm and 60 nm.

(44) During formation of the Al.sub.1-xSi.sub.xO layer, a number of growth or deposition conditions can be optimized to ensure that the resulting Al.sub.1-xSi.sub.xO layer is amorphous (rather than polycrystalline). For example, the growth or deposition temperature, chamber pressure, and/or Si/Al ratio in combination with the N.sub.2 and O.sub.2 ratio can be optimized to realize an amorphous Al.sub.1-xSi.sub.xO layer. Generally, decreasing the growth or deposition temperature and increasing the Si/Al ratio tends to cause the deposited Al.sub.1-xSi.sub.xO layer to be amorphous, rather than polycrystalline. For example, for a growth or deposition temperature of about 900° C. or higher, the resulting Al.sub.1-xSi.sub.xO can be amorphous if the Si/Al ratio is about ¼ or greater, whereas for a growth or deposition temperature of about 700° C. or higher, the resulting Al.sub.1-xSi.sub.xO can be amorphous if the Si/Al ratio is about 1/9 or greater. However, it has been found that increasing the growth or deposition temperature, and/or decreasing the Si/Al ratio, in an Al.sub.1-xSi.sub.xO gate insulator layer of a III-N enhancement-mode device causes the gate leakage in the device to decrease substantially as long as the Al.sub.1-xSi.sub.xO is amorphous (devices with polycrystalline layers have been found to exhibit substantially higher gate leakage). Breakdown voltage of the device with respect to the gate-source bias is reduced for a device that has a gate insulator with a polycrystalline structure compared to a device that has an amorphous Al.sub.1-xSi.sub.xO gate insulator layer. Under certain growth conditions, the amorphous Al.sub.1-xSi.sub.xO layer can include a nanocrystalline layer at the nitride-oxide interface. This is because the amorphous Al.sub.1-xSi.sub.xO layer is directly deposited on a single crystalline nitride surface that has a highly ordered atomic structure. The nanocrystalline layer, if present, can range from a few nanometers to up to 40% of the amorphous Al.sub.1-xSi.sub.xO layer thickness. Unlike a polycrystalline layer, a nanocrystalline layer does not generate a strong X-ray diffractions signal, and therefore cannot be measured unambiguously by grazing-incidence X-ray diffraction. The existence of a nanocrystalline layer can be detected, e.g., by high-resolution transmission electron microscopy (TEM) cross sectional imaging. To optimize the device, the minimum Si/Al ratio in the Al.sub.1-xSi.sub.xO layer can may be ¼ (e.g. x>0.2). If the Si/Al ratio is too high, for example greater than 4 (e.g. x>0.8), the device can demonstrate characteristics of decreased threshold voltage. In some cases where the threshold voltage is substantially decreased, the threshold voltage (V.sub.th) can be negative, causing the device to operate in depletion mode, e.g., in the ON state when 0 bias is applied to the gate, instead of in enhancement mode, e.g., in the OFF state when 0 bias is applied to the gate. Hence, the deposition conditions of the Al.sub.1-xSi.sub.xO gate insulator layer can be optimized such that a high deposition temperature and an optimized Si/Al ratio are maintained while still achieving an amorphous layer. In some implementations, the growth or deposition temperature of the amorphous Al.sub.1-xSi.sub.xO layer is greater than 500° C., for example greater than 800° C. or greater than 900° C., and/or the ratio of the Si fractional composition to the Al fractional composition (1−x)/x is less than 4, for example less than 1, less than ⅓. In one embodiment, the Si/Al ratio is about ⅔, which results in a Si content of about 40%. This ratio can be an optimized ratio to improve threshold voltage and to increase the gate to source breakdown voltage of the transistor. The threshold voltage hysteresis between the positive direction sweep and the negative direction sweep can also be reduced for III-N devices grown with Al.sub.1-xSi.sub.xO at an optimized ratio. In some cases, precursor gases can be used in the growth reactor before the growth of the insulator layer, but not during the growth of the insulator layer, to form a sheet acceptor layer. This sheet acceptor layer can increase the charge at the interface between the III-N channel layer and the insulator layer. An example of these gases can include Mg, Fe, Zn or others gases. In some cases, during the growth of the amorphous Al.sub.1-xSi.sub.xO layer, different source gases can be injected into the growth reactor, such as N.sub.2O, NO, hydrazine and derivatives. These source gases can result in a low concentration of nitrogen being incorporated into the amorphous Al.sub.1-xSi.sub.xO layer, where the nitrogen concentration is substantially lower than the concentrations of Al, Si, and O in the layer. Other alternative layers could be used to construct the gate insulator including Al.sub.2O.sub.3, or Al.sub.xSi.sub.yN. However, the performance of the Al.sub.1-xSi.sub.xO layer as a gate insulator can provide III-N device performance advantages that are more desirable to enhancement mode operation.

(45) Referring back to FIG. 3A, a gate electrode is formed on the gate insulator (step 304). The gate electrode can be the gate contact 123 of FIG. 1. As noted above, the gate electrode can be formed conformally on the gate insulator at least partially in the recess, by depositing metal stacks, e.g., titanium/aluminum (Ti/Al) or semiconductor materials in combination with metal, e.g., titanium nitride/aluminum (TiN/Al) using metal evaporation or sputtering, and optionally performing a post-gate deposition annealing process. The gate electrode formed with TiN/Al, in this embodiment, can interact with the amorphous Al.sub.1-xSi.sub.xO to form an interface which acts to increase the threshold voltage of the III-N device. Typically, when a semiconductor gate electrode with a large work function, such as TiN/Al, is connected to a gate insulator such as Al.sub.xSi.sub.yN, the threshold voltage shift is close to zero when compared to a gate electrode with a smaller work function such as titanium/aluminum (Ti/Al) due to Fermi level pinning at the dielectric surface. However, when the disclosed amorphous Al.sub.1-xSi.sub.xO is connected to a semiconductor gate electrode such as titanium nitride/aluminum (TiN/Al), the threshold voltage of the III-N device can be increased. This effect is demonstrated using metal-insulator-semiconductor capacitor structures with Al.sub.xSi.sub.yN and Al.sub.1-xSi.sub.xO on GaN with gate electrodes composed of various work function materials, as shown in FIG. 8. A post-gate deposition anneal process can be performed in a gas ambient environment including oxygen or forming gas (H.sub.2+N.sub.2). The annealing process can be performed at a temperature greater than 400° C. The hydrogen in the forming gas can penetrate through the gate electrode during the annealing process and attached to dangling bonds at the oxide/gate electrode interface. Removing these dangling bonds can improve the oxide interface surface quality. As such, the III-N device can demonstrate improved performance characteristics such as higher V.sub.th and hysteresis in the V.sub.th swing curve. The gate electrode can include vertical sidewalls in the recess adjacent to the barrier layer and slanted sidewalls in the recess adjacent to the insulator layer. In some implementations, the gate electrode includes extending portions that are outside the recess and extend towards but are separated from the source contact and the drain contact, respectively. These extending portions of the gate electrode can act as field plates to reduce the electric field across the depletion region of the III-N device.

(46) After deposition of the gate electrode, the gate electrode can further be used as an etch mask to etch the gate insulator, such that the gate insulator remains directly beneath the gate contact but is etched away elsewhere, as shown in FIG. 1. Alternatively, the gate insulator 120 can be partially etched as shown in FIG. 6.

(47) Next, the source and drain contacts which are electrically coupled to the channel layer are then formed such that the gate electrode is in between the source and drain contacts (step 306). The source and drain contacts can be the source contact 121 and the drain contact 122 of FIG. 1, respectively. As noted above, the source contact and the drain contact can be formed as metal stacks, e.g., Ti/Al/Ni/Au or Ti/Al, in contact with the channel layer in the III-N device, e.g., by using metal evaporation or sputtering, and optionally performing a post-deposition annealing process. In some cases, the source and drain contacts, respectively, form ohmic contacts electrically contacting or coupled to the conductive channel, e.g., the 2DEG channel, in the channel layer. In some cases, a recess can be formed by dry etching before the deposition of the source and drain contacts. The source and drain contacts are then formed in the recess to allow for lower contact resistance between the metal/III-N interface. The source and drain contacts may optionally be formed prior to forming the recess.

(48) Metal-oxide-semiconductor enhancement mode III-N power devices have been formed using Al.sub.2O.sub.3 as the gate insulator layer. However, III-N devices with Al.sub.1-xSi.sub.xO gate insulator layers demonstrate an increase in threshold voltage and a decrease in hysteresis of the gate characteristics, both of which are preferred for enhancement mode operation. The addition of Si to the gate insulator layer can be a difficult task and requires equipment that would not conventionally be needed to deposit high quality Al.sub.2O.sub.3 as the gate insulator layer. As the Si content increases beyond an optimized value (as shown in FIG. 10), values of the threshold voltage can become more negative than a value of the threshold voltage corresponding to the optimized Si content value. In addition, Al.sub.1-xSi.sub.xO demonstrates an unpinned dielectric interface when used in combination with gate electrode material with a high work function such as titanium nitride, as shown if FIG. 8.

(49) FIG. 3B shows an example process 300B. Process 300B can be performed after process 200A or 200B have been performed for forming III-N device. For instance, the process steps 202, 204, 206, 208, 210, 212 in conjunction with process 300B can be used to form the III-N device 400, 500, or 600 of FIG. 4, FIG. 5 or FIG. 6 respectively. The processing steps 300B of FIG. 3B can be used as an alternative to the process 300A of FIG. 3A to form at least part of the III-N device 400. Process 300B includes the same process steps 302, 304, and 306 of process 300A but includes an additional step 308 to be performed before process step 302.

(50) Referring to FIG. 3B, the process 300B includes regrowing (at step 308) a III-N layer on the top surface of the channel layer, inside the recess formed in process step 210. The regrown III-N layer can act as a III-N capping layer, and can have any one of the examples of compositions described below in connection with FIG. 4. In one embodiment, the III-N capping layer has a composition of AlGaN on the side of the III-N capping layer adjacent to the III-N channel layer and a composition of GaN on the side of the III-N capping layer opposite the III-N channel layer. The III-N capping layer can be a ternary or a quaternary compound such as InAlGaN. In another embodiment, the III-N capping layer can have a composition of AlN on the side of the III-N capping layer adjacent to the III-N channel layer, a middle composition of AlGaN and a composition of GaN on the side of the III-N capping layer opposite the III-N channel layer. The growth of the III-N capping layer can be performed in a MOCVD growth reactor. The III-N capping layer can have a thickness between 1 nm and 10 nm. The thickness of the III-N capping layer is smaller than the thickness of the III-N barrier layer. The III-N barrier layer can have a thickness of up to 30 nm and the regrowth of the III-N capping layer can have a thickness of 1-10 nm, as described above. The III-N capping layer can grow on the sidewalls of the III-N barrier layer, as shown in layer 117 of FIG. 4. In some implementations, precursor gases can be used in the growth reactor before the growth of the III-N capping layer, but not during the growth of the III-N capping layer, to form a sheet acceptor. An example of these gases can include Mg, Fe, Zn or others gases. For example, AlGaN can be grown during an initial phase of the III-N capping layer growth. In a middle phase, Mg gas can be introduced in the growth reactor for a period of time. In a final phase of the III-N capping layer, GaN can be grown that is substantially free of Mg doping. In another embodiment, the III-N capping layer can also include a final composition of a p-type GaN layer on the side of the III-N capping layer opposite the III-N channel layer. This p-type GaN layer can improve the threshold voltage (Vth) of the III-N device to insure proper enhancement mode operation of the device.

(51) Next, an amorphous Al.sub.1-xSi.sub.xO gate insulator is formed (at step 302) on the III-N capping layer. For example, the amorphous Al.sub.1-xSi.sub.xO gate insulator can be formed using step 302 of process 300A as described above in connection with FIG. 3A for process 300B in connection with FIG. 3B.

(52) In one embodiment, a post deposition anneal can be performed on the III-N device after the gate insulator is formed. The anneal process can be performed in situ, in a growth reactor in which the gate insulator was formed, without exposing the III-N device to air between the forming of the gate insulator and the annealing steps. The anneal process can be performed at a temperature of at least 800° C., e.g., 850° C., 900° C., 950° C. The anneal process can be performed for at least 20 minutes, e.g., 25, 30 or 40 minutes.

(53) In another embodiment, the growth of the III-N capping layer and the growth of the amorphous Al.sub.1-xSi.sub.xO gate insulator can be performed in situ in a growth reactor in which the III-N capping layer was grown. In this manner, the III-N device is kept in the growth reactor without being exposed to air between the steps of growing of the III-N capping layer and the forming of the gate insulator.

(54) In yet another embodiment, the III-N capping layer, the amorphous Al.sub.1-xSi.sub.xO gate insulator, and the anneal of the III-N device can be performed in a MOCVD growth reactor, in a sequential manner, without exposing the III-N device to air between the steps of growing the III-N capping layer and the forming of the gate insulator; and between the steps of forming the gate insulator and the annealing.

(55) After the formation of a III-N capping layer, the growth reactor typically needs to be conditioned to allow for safe growth of an oxide layer. Hydrogen gas present during the III-N capping layer growth must be purged from the MOCVD reactor before Oxygen source gases can be used. This can require removal of the III-N device from the growth reactor after the deposition of the III-N capping layer and before the deposition of the amorphous Al.sub.1-xSi.sub.xO gate insulator. Exposing the III-N device to the atmosphere can result in defect formation or formation of an unintended oxidation layer to on the III-N capping layer. These defects and/or oxidization layer can result in degraded device performance and particularly in degradation in device performance preferred for enhancement mode operation. Poor surface quality of the III-N device interface between the channel layer 114, the regrowth III-N capping layer 117, and the gate insulator 120 can result in a reduced threshold voltage shift and increased surface charge trapping. The increased surface charge trapping at the device interfaces described above can have the effect of increased on-resistance R.sub.on, particularly during switching operation of the III-N device.

(56) Referring back to FIG. 3B, a gate electrode is formed (at step 304) on the gate insulating layer. The gate electrode can be formed using step 304 of process 300A described above in connection with FIG. 3A. As noted above, the gate electrode can be formed conformally on the gate insulator at least partially in the recess, by depositing metal stacks, e.g., titanium/aluminum (Ti/Al) or semiconductor materials in combination with metal, e.g., titanium nitride/Aluminum (TiN/Al) using metal evaporation or sputtering, and optionally performing a post-gate deposition annealing process. In a particular embodiment, the gate electrode is formed with titanium nitride and aluminum (TiN/Al). The titanium nitride can be deposited by sputtering without exposure to air with the aluminum (Al). The aluminum top metal can act as a conductive layer to enhance the electron mobility of the gate electrode.

(57) In addition, referring back to steps 308, 302, and 304 of process 300B, these steps performed together can result in decreased surface trapping at the interface of the III-N channel layer and the III-N capping layer. The amorphous Al.sub.1-xSi.sub.xO layer in combination with the semiconductor gate material such as TiN/Al, can result in improved III-N device threshold voltage compared to using conventional gate insulators such as Al.sub.xSi.sub.yN.

(58) Referring back to FIG. 3B, the source and drain contacts are formed (at step 306) in a manner that is similar to step 306 of process 300A described above in connection with FIG. 3A. In some implementations, the source and drain contacts can be formed of the same materials and using the same processes as described in process 300A. The benefits of having the recessed ohmic contacts apply to the formation of the III-N device described in the process 300A.

(59) FIG. 4 is a cross sectional view of an example III-N device 400. Device 400 is similar to device 100 of FIG. 1, except that device 400 includes a III-N capping layer 117 formed in the recess 124, on the top surface of the channel layer 114. The gate insulator 120 is formed on the III-N capping layer 117, as shown in FIG. 4.

(60) Layers of device 400 each have the same properties as the respective like numbered layers of device 100 of FIG. 1, and can therefore be the same materials and formed using the same methods previously described with the reference to device 100 of FIG. 1. The processes used to create the III-N device 400 can be the process 200A (without optional step 210) in combination with process 300B, as described above. The III-N capping layer 117 can have different compositions of III-N materials compared to the channel layer 114 and the barrier layer 116. The III-N capping layer 117 can have a lower ratio of Al than that of the III-N barrier layer 116. The III-N capping layer 117 can be GaN or AlGaN. The III-N capping layer 117 can be a ternary or a quaternary compound such as InAlGaN. In some implementations, the III-N capping layer 117 can have a composition of AlGaN on a side of the III-N capping layer adjacent to the III-N channel layer and GaN on the side of the III-N capping layer opposite the III-N channel layer. The III-N capping layer 117 can also be doped to form a p-type GaN layer or a doped AlGaN layer. In yet another implementation, the capping layer 117 can include a composition of AlN/AlGaN/GaN, where the AlN layer is on a side of the III-N capping layer adjacent to the III-N channel layer. A preferred embodiment of the III-N capping layer is an initial composition of AlGaN adjacent the III-N channel layer and a final composition of p-type GaN adjacent the gate insulator layer 120.

(61) The III-N capping layer 117 is deposited after the formation of the recess 124 in the III-N device. Dry etching techniques used to form the recess 124 can cause ion bombardment damage, which can reduce the channel carrier mobility. The ion bombardment damage on the surface of the channel layer 114 can be repaired by adding the III-N capping layer 117 after the formation of the recess 124 in a first portion of the device. Additionally, the capping layer 117 can improve the channel mobility by inserting a III-N heterojunction between the gate dielectric and the channel material. In a particular embodiment, the formation of the recess 124 includes partially etching the III-N channel layer 114 in a first portion of the device. This portion of the etched channel can be replaced by the III-N capping layer. The III-N capping layer 117 can be important to optimize the depth of the recess 124 to ensure the device realizes enhancement mode operation. The III-N capping layer can grow on the sidewalls of the III-N barrier layer, as shown in layer 117 of FIG. 4. The gate insulator 120 is formed on the III-N capping layer 117 in the recess instead of directly on the III-N channel layer 114 as in the device 100 of FIG. 1. The gate insulator 120 can have the same shape and properties as the gate insulator of device 100 in FIG. 1.

(62) FIG. 5 is a cross-sectional view of another III-N device 500. Device 500 is similar to device 400 of FIG. 4, except that device 500 has been created using the optional process step 210 described in process 200A. Process step 210 includes partially removing the insulator layer 118 before forming the trench 124. Partially removing the insulator layer 118 can result in the formation of region 126 in FIG. 5. The insulator layer 118 may only remain in an area near the drain 122 in a region of the device between the gate and the drain. The width of the insulator layer 118 removed can be 2 times the width of the recess 124 or up to 50 times the width of the recess 124. The regrowth of the III-N capping layer 117 in the recess 124 can be problematic to perform due to the small open area of the recess compared to the overall distance between the source contact 121 and the drain contact 122. Since the III-N capping layer tends to not grow on the insulator layer 118, the growth rate of the III-capping layer 117 in the recess 124 can be very high and difficult to control due to the masking effect with a small percent open area. Removing the insulator layer 118 with a greater width than the recess 124 can reduce the growth rate of the III-N capping layer 117, by making a larger percent open area, and make the deposition thickness more accurate. As a result, the III-N capping layer can grow on the exposed top surface of the III-N barrier layer 116 created by the removal of the insulator layer 118 in the area 126. Poor control of the thickness of the III-N capping layer can affect the threshold voltage of the device. If the III-N capping layer is too thick, the threshold voltage of the device can increase, causing the device to operate in depletion mode instead of enhancement mode, as desired. The gate insulator layer 120 is then formed over the III-N capping layer 117. The gate insulator 120 can extend all the way from the source contact 121 to the drain contact 122. Next, the gate contact 123 is formed conformally on the gate insulator 120 at least partially in the recess 124. Finally, the gate contact 123 can be used as an etch mask to etch the gate insulator 120, such that the gate insulator 120 remains directly beneath the gate contact 123 but is etched away everywhere else. Alternatively, the gate insulator can be etched away only over the insulator layer 118 but remain over the III-N capping layer 117 (not shown), or the gate insulator can be partially etched away and still remain over the entire active area between the source contact 121 and the drain contact 122 (not shown).

(63) FIG. 6 is a cross-sectional view of another III-N device 600. Device 600 is similar to device 500 of FIG. 5, except that, while device 500 has been created by completely removing the insulator layer 118 using the optional process step 210 described in process 200A of FIG. 2A, device 600 can be created by following process 200B of FIG. 2B, which does not include forming the insulator layer on the barrier layer, as described in process step 208 of process 200A. Next, process 300B is followed and the III-N capping layer 117 is grown directly on the channel layer 116 from the source 121 to the drain 122. The insulator layer 120 is over the III-N capping layer 117. In this embodiment, the insulator layer 120 is typically only partially etched in a region outside the gate electrode 123 in order to passivate the III-N capping layer 117. In a preferred embodiment for device 600, the III-N barrier layer 116 can have an initial composition of Al.sub.xGa.sub.1-xN and a final composition of GaN and is substantially free of Al at the top surface of the III-N barrier layer.

(64) FIG. 7 is a cross-sectional view of another III-N device 700. Device 700 is similar to device 100 of FIG. 1, except that device 700 includes two gate electrodes 723 and 723′ between the power electrodes 721 and 722. Device 700 can be operated as a bidirectional switch (i.e., a four quadrant switch or FQS), where voltages on the first gate electrode 723 are applied relative to the first power electrode 721, voltages on the second gate electrode 723′ are applied relative to the second power electrode 722, and power electrodes 721 and 722 are each operated as a source and a drain of the device 700 (depending on the polarity of the voltage across the device and/or the direction of current flow).

(65) Layers 710, 712, 714, 716, and 718 of device 700 each have the same properties as respective layers 110, 112, 114, 116, and 118 of the device of FIG. 1, and can therefore be the same materials and formed using the same methods previously described with reference to device 100 of FIG. 1. Recesses 724 and 724′ can each have the same shape and properties as recess 124 in FIG. 1, and can be formed by the same methods as those described with reference to device 100 of FIG. 1. Gate electrodes 723 and 723′, as well as their respective gate insulator layers 720 and 720′, can each have the same shape and properties as gate insulator layers 120 in FIG. 1, and can be formed by the same methods and/or from the same materials as those described with reference to device 100 of FIG. 1.

(66) FIG. 8 shows flat-band voltages 800 of gate electrode materials with different work functions. As show in the FIG. 8, the flat-band voltage of a gate insulator layer formed of Al.sub.xSi.sub.yN is relatively unchanged for the range of metal work functions. However, the flat-band voltage of a gate insulator layer formed of Al.sub.1-xSi.sub.xO has a strong positive correlation as the metal work function increases. The gate electrode corresponding to the metal work function of 4.3 eV in this figure is Ti/Al. The gate electrode corresponding to the metal work function of 4.9 eV and 5.0 eV in this figure is TiN and Ni respectively. The Al.sub.1-xSi.sub.xO has an unpinned dielectric surface with the metal, whereas the Al.sub.xSi.sub.yN dielectric surface is pinned due to fermi level pinning. Measurements in FIG. 8 show that a III-N device with Al.sub.1-xSi.sub.xO in combination with a gate electrode material with a high work function such as TiN can achieve much better device performance, e.g., higher threshold voltage, than a III-N device using Al.sub.1-xSi.sub.xN as the gate insulator layer.

(67) FIG. 9A defines the criteria for the V.sub.TH measurement shown in FIG. 10. As shown in FIG. 9A, V.sub.TH is defined as V.sub.GS with I.sub.DS @10.sup.−5 A/mm (V.sub.TH=V.sub.GS@10.sup.−5 A/mm). FIG. 9B shows criteria for determining the low field voltage (V.sub.LF) limit for the metal-insulator-semiconductor capacitor structure measurement shown in FIG. 10. At a relatively low V.sub.G (−10V to 10V), the gate leakage is constant and low. As V.sub.G increases (>10V) the gate leakage increases until the device reaches catastrophic breakdown. The V.sub.G which corresponds to a gate leakage (I.sub.G) of 10.sup.−4 A/cm2 is used to define V.sub.LF. Device operation is preferable in a low field range. Operation outside the low field range can result in device instability and hole injection into the gate insulator dielectric. This area of operation can also demonstrate characteristics of greater hysteresis compared to device operation with the V.sub.LF range.

(68) FIG. 10 shows a first graph 1000A of the change in threshold voltage (VIE), and a second graph 1000B of the low field voltage (V.sub.LF), of a III-N device with an Al.sub.1-xSi.sub.xO gate insulator layer for varying dielectric composition of Si, where x corresponds to the % Si shown in the figure. The first graph 1000A shows that V.sub.TH increases as the Si content increases from 30-80% and decreases as the Si content approaches 100%. The V.sub.TH of a III-N device must be positive to demonstrate enhancement mode operation. A minimum preferable V.sub.TH value for stable operation is indicated in the first graph 1000A by the horizontal line with a value of ˜0.35V. The second graph 1000B shows the low field voltage (V.sub.LF) increases from 0%-50% Si and then decreases as the Si value approaches 80%. A dielectric layer with 100% Si (SiO.sub.2) typically shows a very high V.sub.LF but with undesirable V.sub.TH. A minimum preferable V.sub.LF value for stable operation is indicated in the second graph 1000B by a horizontal line with a value of ˜15V. To design a III-N device which is optimized for Si content, high V.sub.TH in combination with high V.sub.LF must be considered. As indicated in the combination of graphs 1000A and 1000B of FIG. 10, an ideal Si % range which meets the performance requirements of V.sub.TH and V.sub.LF is between about 40%-50% Si content of the Al.sub.1-xSi.sub.xO gate insulator layer.

(69) A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. Features shown in each of the implementations may be used independently or in combination with one another. Accordingly, other implementations are within the scope of the following claims.