AN ELECTRONIC DEVICE AND A METHOD FOR SUPPRESSING NOISE FOR AN ELECTRONIC DEVICE

Abstract

The present invention relates to an electronic device, comprising: —a GFET; —noise suppression means comprising: —a modulation unit applying to a gate (G) of the GFET a signal V.sub.g with frequency f.sub.m to modulate charge carrier density of a graphene channel around the charge neutrality point between charge carrier density values at frequency f.sub.m, —a control unit (CU), and —a demodulation circuit which is CMOS-implemented and that: —comprises first and second circuital branches alternately switchable to demodulate an electrical signal of frequency f.sub.m; or —is configured to generate and apply a signal V.sub.b with frequency f.sub.mb to a source (S) of the GFET continuously, simultaneously and with a delay t.sub.d to induce a phase with respect to V.sub.g to yield a maximal demodulated output signal (So). The present invention also concerns to a method for suppressing noise for the device of the invention.

Claims

1. An electronic device, comprising: a graphene field effect transistor (GFET); and a noise suppression mechanism comprising a modulation unit configured to generate and apply to a gate electrode structure of said GFET, a voltage oscillating time-dependent signal having at least one component with a frequency of f.sub.m and that oscillates between first and second voltage values selected so that charge carrier density of a graphene channel of the GFET is modulated around the charge neutrality point of the graphene between charge carrier density values at, at least, said frequency f.sub.m, wherein said noise suppression mechanism further comprises a control unit, and a demodulation circuit which is CMOS-implemented and that comprises first and second circuital branches which are alternately switchable, under the control of said control unit, to demodulate at least an electrical signal of frequency f.sub.m of a modulated electrical current circulating through the graphene channel of the GFET when is under said modulation around the charge neutrality point of the graphene.

2. The device according to claim 1, wherein said first and second circuital branches are alternately switchable, under the control of said control unit, for respectively sampling first and second portions of at least said electrical signal of frequency f.sub.m of a modulated electrical current circulating through the graphene channel when the GFET is biased and the graphene channel is under said modulation around the charge neutrality point of the graphene.

3. The device according to claim 2, wherein said demodulation circuit further comprises: a high-pass filter having a cut frequency f.sub.c1<f.sub.m and that electrically connects an output of the GFET through which said modulated electrical current goes out, or of a further component electrically connected to said output, with an input of said demodulation circuit; and a post-processing unit electrically connected to respective outputs of said first and second circuital branches to receive, under the control of said control unit, said sampled first and second portions, and configured to process the same to provide a demodulated output signal.

4. The device according to claim 3, wherein said post-processing unit is configured to process said sampled first and second portions to provide said demodulated output signal according to one or more of the following types of linear combinations: additions, subtractions, or weighted additions and subtractions.

5. The device according to claim 2, or wherein each of said first and second circuital branches comprises: a switch configured and arranged to electrically connect or disconnect said input of the demodulation circuit with the output of the respective circuital branch, when in a respective on or off state induced by said control unite; and a capacitor electrically connected between said output of the respective circuital branch and a ground point and that is configured and arranged to be charged with an electrical current circulating through said switch when in said on state; wherein said post-processing unit is configured to receive said sampled first and second portions by measuring, under the control of said control unite, the magnitude of the electrical charge stored on the respective charged capacitor; and wherein the device further comprises at least one reset circuit configured and arranged to drain, under the control of the control unit, the electrical charge stored on the capacitors.

6. The device according to claim 5, wherein said demodulation circuit further comprises said further component electrically connected between said output of the GFET and said high-pass filter, wherein said further component is a transimpedance or capacitive transimpedance amplifier.

7. The device according to claim 2, or wherein each of said first and second circuital branches comprises: a switch configured and arranged to electrically connect or disconnect said input of the demodulation circuit with the output of the respective circuital branch, when in a respective on or off state induced by said control unit; a capacitive transimpedance amplifier with an input electrically connected between said switch and the output of the respective circuital branch, wherein said capacitive transimpedance amplifier comprises, electrically connected in parallel with each other: an operational amplifier, a capacitor configured and arranged to be charged with an electrical current circulating through said switch when in said on state, and a reset circuit configured and arranged to drain, under the control of the control unit, the electrical charge stored on the capacitor; wherein said post-processing unit is configured to receive said sampled first and second portions by measuring, under the control of said control unit, the magnitude of the electrical signal provided by the operation amplifier when the respective capacitor is charged.

8. The device according to claim 5, wherein said control unit is configured to control said switches, said post-processing unit, and said at least one reset circuit, to operate according to a reading mode that comprises: inducing said on state of said switch of the first circuital branch along a time t.sub.int1 that coincides with at least part of the time during which the first voltage value of the voltage oscillating time-dependent signal is being applied to the gate electrode structure of the GFET; inducing said off state of said switch of the first circuital branch; inducing said on state of said switch of the second circuital branch along a time t.sub.int2 that coincides with at least part of the time during which the second voltage value of the voltage oscillating time-dependent signal is being applied to the gate electrode structure of the GFET; inducing said off state of said switch of the second circuital branch, once said t.sub.int2 has lapsed; controlling said at least one reset circuit or reset circuits, to drain the electrical charge stored on the capacitors, after said t.sub.int2 has lapsed; controlling the post-processing unit to obtain a signal out by performing, and then processing, the following measurements: during t.sub.int1 or t.sub.int2: the magnitude of the electrical charge stored on the charged capacitor of the first circuital branch; or the magnitude of the electrical signal provided by the operation amplifier of the first circuital branch when the respective capacitor is charged; during t.sub.int2: the magnitude of the electrical charge stored on the charged capacitor of the second circuital branch; or the magnitude of the electrical signal provided by the operation amplifier of the second circuital branch when the respective capacitor is charged.

9. The device according to claim 1, wherein said control unit is configured also to generate and apply to said gate electrode structure of the GFET said voltage oscillating time-dependent signal having at least one component with a frequency of f.sub.m and that oscillates between first and second voltage values.

10. The device according to claim 9, wherein the GFET further comprises a sensitizing structure arranged over said graphene channel, wherein said sensitizing structure is configured to induce charge carriers therein, wherein said sensitizing structure is an actively controlled sensitizing or functionalizing structure, and wherein the device further comprising a drift compensation mechanism to compensate an unwanted drift caused by the graphene of the GFET, said drift compensation mechanism comprising a control electrode electrically connected to said actively controlled sensitizing structure and said control unit configured to operate in a drift compensation mode.

11. The device according to claim 10, wherein in said drift compensation mode, said control unit is configured to perform the actions of said reading mode while applying to said control electrode a voltage V.sub.on that turns on the actively controlled sensitizing or functionalizing structure to generate charges that can be sensed by the graphene channel by changing its conductance induced by an external physical quantity, to obtain said signal out, and, once the charge stored on the capacitors is drained, perform the following actions: applying a voltage V.sub.off to said control electrode, during a time t.sub.int1+t.sub.int2, to tune the actively controlled sensitizing or functionalizing structure to a condition where a change in said external physical quantity does not lead to a change in charge carrier density in the graphene channel; inducing said on state of said switch of the first circuital branch along a time t.sub.int1 that coincides with at least part of the time during which the first voltage value of the voltage oscillating time-dependent signal is being applied to the gate electrode structure of the GFET; inducing said off state of said switch of the first circuital branch; inducing said on state of said switch of the second circuital branch along a time t.sub.int2 that coincides with at least part of the time during which the second voltage value of the voltage oscillating time-dependent signal is being applied to the gate electrode structure of the GFET; inducing said off state of said switch of the second circuital branch, once said t.sub.int2 has lapsed; controlling said at least one reset circuit or reset circuits, to drain the electrical charge stored on the capacitors, after said t.sub.int2 has lapsed; controlling the post-processing unit to obtain a drift correction out by performing, and then processing, the following measurements representative of a drift charge: during t.sub.int1 or t.sub.int2: the magnitude of the electrical charge stored on the capacitor of the first circuital branch; or the magnitude of the electrical signal provided by the operation amplifier of the first circuital branch when the respective capacitor has been charged; during t.sub.int2: the magnitude of the electrical charge stored on the capacitor of the second circuital branch; or the magnitude of the electrical signal provided by the operation amplifier of the second circuital branch when the respective capacitor has been charged; adjust the first and second voltage values of the voltage oscillating time-dependent signal based on said drift correction out, and use said adjusted first and second voltage values to perform subsequent reading modes, to compensate said unwanted drift therein.

12. An electronic device, comprising: a graphene field effect transistor (GFET); and a noise suppression mechanism comprising a modulation unit configured to generate and continuously apply to a gate electrode structure of said GFET a voltage oscillating time-dependent signal having at least one component with a frequency of f.sub.m and that oscillates between first and second voltage values selected so that charge carrier density of a graphene channel of the GFET is modulated around the charge neutrality point of the graphene between charge carrier density values at at least said frequency f.sub.m, wherein said noise suppression mechanism further comprises a control unit, and a demodulation circuit which is CMOS-implemented and is configured to, under the control of said control unit, generate a bias voltage oscillating time-dependent signal having at least one component with a frequency of f.sub.mb and that oscillates between first and second voltage values, and apply the same to a source electrode structure of the GFET continuously, simultaneously and with a delay t.sub.d to induce a phase with respect to the voltage oscillating time-dependent signal applied to the gate electrode structure, wherein said delay t.sub.d is selected to optimize the conditions to demodulate at least an electrical signal of frequency f.sub.m of a modulated electrical current circulating through the graphene channel of the GFET when is under said modulation around the charge neutrality point of the graphene and yield a maximal demodulated output signal.

13. The device according to claim 12, wherein said demodulation circuit further comprises a low-pass filter having a cut frequency f.sub.c2>f.sub.m, f.sub.mb and with an input that is electrically connected to a drain electrode structure of the GFET, to filter and provide at an output of the low-pass filter the electrical signal corresponding to the induced charge on the GFET channel, with or without a DC offset.

14. The device according to claim 13, wherein said low-pass filter is passive, and the device further comprises an impedance matching unit interconnected between said drain electrode structure and the input of said low-pass filter.

15. A method for suppressing noise for an electronic device according to claim 1, comprising performing the operations of said control unit of the electronic device.

16. A method for suppressing noise for an electronic device according to claim 12, comprising performing the operations of said control unit of the electronic device.

17. The device according to claim 7, wherein said control unit is configured to control said switches, said post-processing unit, and said at least one reset circuit, to operate according to a reading mode that comprises: inducing said on state of said switch of the first circuital branch along a time t.sub.int1 that coincides with at least part of the time during which the first voltage value of the voltage oscillating time-dependent signal is being applied to the gate electrode structure of the GFET; inducing said off state of said switch of the first circuital branch; inducing said on state of said switch of the second circuital branch along a time t.sub.int2 that coincides with at least part of the time during which the second voltage value of the voltage oscillating time-dependent signal is being applied to the gate electrode structure of the GFET; inducing said off state of said switch of the second circuital branch, once said t.sub.int2 has lapsed; controlling said at least one reset circuit or reset circuits, to drain the electrical charge stored on the capacitors, after said t.sub.int2 has lapsed; controlling the post-processing unit to obtain a signal out by performing, and then processing, the following measurements: during t.sub.int1 or t.sub.int2: the magnitude of the electrical charge stored on the charged capacitor of the first circuital branch; or the magnitude of the electrical signal provided by the operation amplifier of the first circuital branch when the respective capacitor is charged; during t.sub.int2: the magnitude of the electrical charge stored on the charged capacitor of the second circuital branch; or the magnitude of the electrical signal provided by the operation amplifier of the second circuital branch when the respective capacitor is charged.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0089] In the following some preferred embodiments of the invention will be described with reference to the enclosed figures. They are provided only for illustration purposes without however limiting the scope of the invention.

[0090] FIG. 1 shows the relative change of resistance dR/R in the graphene of the device of the present invention, for a given change in carrier density as a function of the total carrier density in the graphene. The arrow indicates the range over which the carrier density needs to be modulated to achieve optimal noise suppression. Below the main panel a time trace of the modulation signal of frequency that needs to be applied to the gate electrode structure of the GFET is represented.

[0091] FIG. 2 shows simulation results of the device of the first aspect of the present invention for Embodiment 2, for a GFET that is switched from one carrier density level to another. On the left: voltages S1o and S2o as a function of time. On the right: So=S1o−S2o as a function of time.

[0092] FIG. 3 shows simulation results of the device of the first aspect of the present invention for Embodiment 2, for a GFET that is switched from one carrier density level to another. In this simulation noise containing low frequency components of the GFET was added to the resistance. On the left: voltages S1o and S2o as a function of time. On the right: So=S1o−S2o as a function of time. This signal clearly shows the noise suppression and demodulation functionality of the embodiment.

[0093] FIG. 4 shows a block diagram of the device of the first aspect of the present invention, showing the connections of the control unit and signal processing unit to the GFET and demodulation circuit (these two latter components have been identified just as “Embodiments 1, 2, 3”), for embodiments 1, 2 and 3.

[0094] FIG. 5 is a schematic drawing of the device of the first aspect of the present invention, for Embodiment 1, including an optional dark current subtraction (DCS), which is not necessary to include when the high pass filter provide the DC dark current subtraction.

[0095] FIG. 6 shows the timing scheme for the demodulation circuit in Embodiments 1-3. Note that the pulse rise and fall times should be finite in reality.

[0096] FIG. 7 is a schematic drawing of the device of the first aspect of the present invention, for Embodiment 2, including an optional dark current subtraction (DCS), which is not necessary to include when the gain of the amplifier is low.

[0097] FIG. 8 is a schematic drawing of the device of the first aspect of the present invention, for Embodiment 3, including an optional dark current subtraction (DCS), which is not necessary to include when the high pass filter provide the DC dark current subtraction.

[0098] FIG. 9 is a block diagram of the device of the second aspect of the present invention, showing the connections of the control unit to the GFET for Embodiment 4, where the block identified as “Embodiment 4” includes that GFET and the demodulation circuit.

[0099] FIG. 10 is a schematic drawing of the second aspect of the present invention, for Embodiment 4, including a dark current subtraction unit (DCS) and an offset correction unit (OC). On the right an illustration of the different signal applied to the gate (G) and source (S) terminals of the GFET.

[0100] FIG. 11 shows a timing sequence for the voltage signals applied to the gate (V.sub.g) and source (V.sub.b) of the GFET of the device of Embodiment 4. Note that the pulse rise and fall times should be finite in reality. t.sub.d is a time delay induced between those signals (V.sub.g and V.sub.b).

[0101] FIG. 12 shows an implementation of the device of the second aspect of the invention, for Embodiment 4. V.sub.g is a voltage applied to the gate G of the GFET that induces a charge Δn in the GFET channel. On the left: simulation of the output signal as a function of V.sub.g offset (with respect to the V.sub.g at the charge neutrality point) and the phase between the GFET source and gate offset modulation. On the right: measurement of the output signal as a function of V.sub.g and the phase between the GFET source and gate modulation. The source drain bias was modulated with an amplitude of 0.5V, gate G was modulated with amplitude of 0.5V. Both at 113 Hz (homodyne detection f.sub.m=f.sub.mb). Note that the charge neutrality point of this device was located at ˜2.9 V.

[0102] FIG. 13 shows the signal out of a real device as a response to three different n.sub.ind levels on the GFET with respect to n.sub.ind=0. Note that the base level contains an offset. Left: signal of a device read using a scheme similar to the one described in Embodiment 4 (homodyne detection f.sub.m=f.sub.mb). Thanks to the noise suppression and mixing scheme, the signal to noise ratio is a factor 10 higher than in the Right panel: signal of a device read using a DC bias and fixed V.sub.g.

[0103] FIG. 14 depicts a timing sequence for the signals of the drift compensation mechanism in case the GFET device comprises active control over the sensitizing structure, as is symbolically illustrated on the right. Note that the pulse rise and fall times should be finite in reality. Also note that V.sub.g1 and V.sub.g2 are slightly different in the second sequence if drift is present in the GFET device.

[0104] FIG. 15 is a block diagram of the device of the first aspect of the present invention, showing the connections of the control unit and signal processing unit to the GFET and demodulation circuit (these two latter components have been identified just as “Embodiments 1, 2, 3”), for embodiments 1, 2 and 3, with the implementation of a drift correction by means of the drift compensation mechanism.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0105] In the present invention an electronic device comprising a GFET connected to four different demodulation circuits, for four respective embodiments, is disclosed. For all four embodiments the GFET has a gate electrode called G that can modulate the charge carrier density of the GFET. The voltage on the gate V.sub.g should be modulated around the charge neutrality point of the graphene (average carrier density=0) to achieve noise suppression, hence gate voltages V.sub.g1 and V.sub.g2 correspond to carrier densities with an opposite sign (once cancelled any possible DC offset, if so). The simplest way of implementing a modulation in CMOS is a square wave. FIG. 1 illustrates the modulation around the points where the relative change in resistance dR/R (directly proportional to Δn) using a square wave.

[0106] In FIG. 2 and FIG. 3 Spice simulations of a circuit according to Embodiment 2 are shown, to demonstrate that the demodulation and noise suppression work.

Embodiments 1, 2 and 3

[0107] In the following, the above identified as Embodiments 1, 2, 3, and 4 will be described with reference to the attached drawings.

[0108] Particularly, schematics representing Embodiments 1, 2 and 3 are respectively shown in FIGS. 5, 6, and 7, and by means of a block diagram in FIG. 4, and for all of them the electronic device of the first aspect of the present invention comprises: [0109] a graphene field effect transistor GFET; [0110] noise suppression means comprising: [0111] a modulation unit configured to generate and apply to a gate electrode structure G of said GFET a voltage oscillating time-dependent signal V.sub.g having at least one component with a frequency of f.sub.m and that oscillates between first V.sub.g1 and second V.sub.g2 voltage values selected so that charge carrier density of a graphene channel of the GFET is modulated around the charge neutrality point of the graphene between charge carrier density values at at least said frequency f.sub.m, [0112] a control unit CU, and [0113] a demodulation circuit which is CMOS-implemented and that comprises first and second circuital branches which are alternately switchable, under the control of the control unit CU, to demodulate at least an electrical signal of frequency f.sub.m of a modulated electrical current circulating through the graphene channel of the GFET when is under said modulation around the charge neutrality point of the graphene.

[0114] For the illustrated implementation of those Embodiments 1, 2, and 3, the source S of the GFET is connected to a bias voltage source, and the drain to a dark current subtraction unit DCS, which is preferably of one of the following types: graphene field effect transistor, MOSFET, one CMOS resistor with resistance value corresponding to the GFET resistance at V.sub.g1 and V.sub.g2 (when the resistances are substantially equal), at least two CMOS resistors with corresponding values corresponding to the GFET resistance at V.sub.g1 and V.sub.g2 (when the two resistances are not substantially equal).

[0115] As shown in FIGS. 4, 5, 7, and 8, the first and second circuital branches are alternately switchable, under the control of the control unit CU, for respectively sampling first S1o and second S2o portions of the electrical signal of frequency f.sub.m of a modulated electrical current circulating through the graphene channel when the GFET is biased and the graphene channel is under said modulation around the charge neutrality point of the graphene.

[0116] As the noise that needs to be suppressed is 1/f noise, the GFET output signal is connected to the demodulation circuit through a high pass filter HF having a cut frequency f.sub.d<f.sub.m and that electrically connects the drain D of the GFET through which the modulated electrical current goes out, or of a further component electrically connected to that drain D, with an input of the demodulation circuit.

[0117] This high pass filter HF can be implemented passive by using for example a capacitor or can be implemented by an active filter, preferably by using one of the following types: active resistor-capacitor, MOSFET-capacitor, transconductance-opamp-capacitor or switched capacitor.

[0118] The device also comprises a post-processing unit PU (see FIG. 4) electrically connected to respective outputs of the first and second circuital branches to receive, under the control of the control unit CU (that control is schematically represented by the arrow line Ct), the sampled first S1o and second S2o portions, and configured to process the same to provide a demodulated output signal So.

[0119] Those sampled first and second portions, or resulting voltages S1o and S2o, need to be further processed. Examples of this post-processing include linear combinations of S1o and S2o, for example additions, subtractions or weighted additions and subtractions.

[0120] To achieve noise suppression, one possibility is to process S1o and S2o differentially (S1o−S2o), for example by another analogue differential amplifier or a differential analogue to digital converter.

[0121] For Embodiments 1 and 2, as shown in FIGS. 5 and 7, respectively, each of the first and second circuital branches comprises: [0122] a switch SW1, SW2, particularly a FET, configured and arranged to electrically connect or disconnect the input of the demodulation circuit with the output of the respective circuital branch, when in a respective on or off state induced by the control unit CU, by means of the application of a gate voltage S1, S2; and [0123] a capacitor C1, C2 electrically connected between the output of the respective circuital branch and a ground point and that is configured and arranged to be charged with an electrical current circulating through the switch SW1, SW2 when in said on state.

[0124] The post-processing unit PU is configured to receive the sampled first S1o and second S2o portions by measuring/reading, under the control of the control unit CU, the magnitude of the electrical charge stored on the respective charged capacitor C1, C2, and the device further comprises reset circuits (one per branch) configured and arranged to drain, under the control of the control unit CU, the electrical charge stored on the capacitors C1, C2.

[0125] For Embodiment 2, as shown in FIG. 7, the device further comprises the above mentioned further component electrically connected between the drain D of the GFET and the high-pass filter HF, wherein that further component is a transimpedance or capacitive transimpedance amplifier A.

[0126] For Embodiment 3, as shown in FIG. 8, each of the first and second circuital branches comprises: [0127] a switch SW1, SW2, particularly a FET, configured and arranged to electrically connect or disconnect said input of the demodulation circuit with the output of the respective circuital branch, when in a respective on or off state induced by said control unit CU, by means of the application of a gate voltage S1, S2; [0128] a capacitive transimpedance amplifier with an input electrically connected between the switch SW1, SW2 and the output of the respective circuital branch, wherein that capacitive transimpedance amplifier comprises, electrically connected in parallel with each other: [0129] an operational amplifier A1, A2, [0130] a capacitor C1, C2 configured and arranged to be charged with an electrical current circulating through said switch SW1, SW2 when in said on state, and [0131] a reset circuit configured and arranged to drain, under the control of the control unit CU, the electrical charge stored on the capacitor C1, C2; [0132] wherein the post-processing unit PU is configured to receive the sampled first S1o and second S2o portions by measuring/reading, under the control of the control unit CU, the magnitude of the electrical signal provided by the operation amplifier A1, A2 when the respective capacitor C1, C2 is charged.

[0133] FIG. 6 shows the timing sequence for the operation of Embodiments 1, 2, and 3, according to a reading mode for which the control unit CU is configured to control the switches SW1, SW2, the post-processing unit PU, and the reset circuits, to operate as follows: [0134] applying a first voltage value V.sub.g1 of the voltage oscillating time-dependent signal V.sub.g to the gate G of the GFET; [0135] applying a voltage S1-on to the gate of the FET SW1 to induce its on state, along a time t.sub.int1 that coincides with the time during which V.sub.g1 is being applied to the gate G of the GFET. This leads a current to charge capacitor C1; [0136] after time t.sub.int1 the control unit CU sets V.sub.g to V.sub.g2, S1 to off, and applies a voltage S2-on to the gate of the FET SW2 to induce its on-state along a time t.sub.int2 that coincides with the time during which the second voltage value V.sub.g2 is being applied to the gate G of the GFET. Now capacitor C2 gets charged; [0137] after time t.sub.int2 the control unit CU sets S2 to off and drains the charges on capacitors C1 and C2 by applying a voltage to put the ‘reset’ capacitors in the on-state during time t.sub.rst; [0138] then the control unit CU controls the post-processing unit PU to obtain a signal out So (corresponding to the carrier charge that the GFET is designed to sense when used for sensing applications) by performing, and then processing, the following measurements/readings: [0139] during t.sub.int1 (at any point during time t.sub.int1, but preferably as close as possible to the end of t.sub.int1) or during t.sub.int2, to obtain S1o: [0140] the magnitude of the electrical charge stored on the charged capacitor C1 of the first circuital branch, for Embodiments 1 and 2; or [0141] the magnitude of the electrical signal provided by the operation amplifier A1 of the first circuital branch when the respective capacitor C1 is charged, for Embodiment 3; [0142] during t.sub.int2 (preferably close to the end thereof), to obtain S2o: [0143] the magnitude of the electrical charge stored on the charged capacitor C2 of the second circuital branch, for Embodiments 1 and 2; or [0144] the magnitude of the electrical signal provided by the operation amplifier A2 of the second circuital branch when the respective capacitor C2 is charged, for Embodiment 3.

Drift Compensation:

[0145] The GFET can contain an actively controlled sensitizing structure. An implementation of this for a photodetector is described by Nikitskiy et al. (Nikitskiy, I. et al. Integrating an electrically active colloidal quantum dot photodiode with a graphene phototransistor. Nat. Commun. 7, 11954 (2016). Using a control electrode Control 1 for the actively controlled sensitizing structure it is possible to add a drift compensation to the read-out schemes proposed in Embodiments 1, 2 and 3.

[0146] Drift is an unwanted shift in the doping of the graphene. This manifests itself as a resistance change when the gate of the GFET is set to a specific gate voltage. This drift can be compensated by tuning the gate voltage. In this drift compensation, an extension of the read-out schemes of embodiments 1-3 is performed to measure the drift, and then use the measured drift in a feedback control loop to adjust the values of V.sub.g1 and V.sub.g2.

[0147] A schematic representation of the GFET with the active sensitizing structure S and control electrode C1, together with a timing sequence of the control signals applied by the control unit CU are shown in FIG. 14, while a block diagram of the resulting embodiments incorporating the feedback control loop is shown in FIG. 15.

[0148] As shown in FIGS. 14 and 15, the GFET comprises an actively controlled sensitizing structure SS, and the device further comprises a drift compensation mechanism to compensate an unwanted drift caused by the graphene of the GFET, the drift compensation mechanism comprising a control electrode C1 electrically connected to the actively controlled sensitizing structure S and the control unit CU configured to operate in a drift compensation mode.

[0149] As shown in FIG. 15, in the drift compensation mode, the control unit CU is configured to perform the actions of the reading mode explained above for any of Embodiments 1, 2 or 3, but with the addition of the application first of a voltage V.sub.on to the control electrode C1 that corresponds to turning on the sensitizing structure to generate charges that can be sensed by the graphene, and the maintaining of that V.sub.on through said reading mode, until the signal out So is obtained and the capacitors C1, C2 are discharged.

[0150] Then, as shown in FIG. 15, the control unit is configured and arranged to perform the following actions: [0151] applying V.sub.g1 to the gate G of the GFET; [0152] applying a voltage V.sub.off to the control electrode C1, during a time t.sub.int1+t.sub.int2, to tune the actively controlled sensitizing S to a condition where it cannot induce charge carrier into the graphene channel; [0153] voltage S1-on to the gate of the FET SW1 to induce its on state, along a time tints that coincides with the time during which Vg1 is being applied to the gate G of the GFET. This leads a current to charge capacitor C1; [0154] after time t.sub.int1 the control unit CU sets V.sub.g to V.sub.g2, S1 to off, and applies a voltage S2-on to the gate of the FET SW2 to induce its on-state along a time t.sub.int2 that coincides with the time during which the second voltage value V.sub.g2 is being applied to the gate G of the GFET. Now capacitor C2 gets charged; [0155] after time t.sub.int2 the control unit CU sets S2 to off and drains the charges on capacitors C1 and C2 by applying a voltage to put the ‘reset’ capacitors in the on-state during time t.sub.rst; [0156] then the control unit CU controls the post-processing unit PU (that control is schematically represented by the arrow line Ct), to obtain a drift correction out Dfo by performing, and then processing, the following measurements/readings representative of a drift charge: [0157] during t.sub.int1 (at any point during time t.sub.int1, but preferably as close as possible to the end of t.sub.int1) or during t.sub.int2: [0158] the magnitude of the electrical charge stored on the charged capacitor C1 of the first circuital branch, for Embodiments 1 and 2 incorporating the drift compensation mechanism; or [0159] the magnitude of the electrical signal provided by the operation amplifier A1 of the first circuital branch when the respective capacitor C1 is charged, for Embodiment 3 incorporating the drift compensation mechanism; [0160] during t.sub.int2 (preferably close to the end thereof): [0161] the magnitude of the electrical charge stored on the charged capacitor C2 of the second circuital branch, for Embodiments 1 and 2 incorporating the drift compensation mechanism; or [0162] the magnitude of the electrical signal provided by the operation amplifier A2 of the second circuital branch when the respective capacitor C2 is charged, for Embodiment 3 incorporating the drift compensation mechanism. [0163] adjust the first V.sub.g1 and second V.sub.g2 voltage values of the voltage oscillating time-dependent signal V.sub.g based on said drift correction out Dfo, and use said adjusted first V.sub.g1 and second V.sub.g2 voltage values to perform subsequent reading modes, to compensate the unwanted drift therein.

Embodiment 4

[0164] In FIG. 9 a block diagram of the control unit CU and components of Embodiment 4, including the connections between the two, is shown. Embodiment 4 does not need a signal processing unit as the processing is done by the mixing capabilities of the graphene. In FIG. 10 the implementation of this demodulation circuit is shown, while in FIG. 11 the timing sequence for this embodiment 4 is depicted.

[0165] For this Embodiment 4, as shown in FIGS. 9 and 10, the electronic device comprises: [0166] a graphene field effect transistor GFET; [0167] noise suppression means comprising: [0168] a modulation unit configured to generate and continuously apply to a gate electrode structure G of said GFET a voltage oscillating time-dependent signal V.sub.g having at least one component with a frequency of f.sub.m and that oscillates between first V.sub.g1 and second V.sub.g2 voltage values selected so that charge carrier density of a graphene channel of the GFET is modulated around the charge neutrality point of the graphene between charge carrier density values at at least said frequency f.sub.m, [0169] a control unit CU, and [0170] a demodulation circuit which is CMOS-implemented and is configured to, under the control of the control unit CU, generate a bias voltage oscillating time-dependent signal V.sub.b having at least one component with a frequency of f.sub.mb and that oscillates between first V.sub.b, and second V.sub.b2 voltage values, and apply the same to a source electrode structure S of the GFET continuously, simultaneously and with a delay td to induce a phase φ=2π.Math.f.sub.mb.Math.t.sub.d with respect to the voltage oscillating time-dependent signal V.sub.g applied to the gate electrode structure G, wherein said delay t.sub.d is selected to optimize the conditions to demodulate at least an electrical signal of frequency f.sub.m of a modulated electrical current circulating through the graphene channel of the GFET when is under said modulation around the charge neutrality point of the graphene and yield a maximal demodulated output signal So.

[0171] As shown in FIG. 11, for this Embodiment 4, the control unit CU continuously applies a voltage V.sub.g to the gate G of the GFET, alternating between V.sub.g1 and V.sub.g2 to modulate the charge carrier density in the graphene around the charge neutrality point. The control unit also applies continuously a bias voltage V.sub.b to the source S of the GFET alternating between V.sub.b1 and V.sub.b2. This voltage signal V.sub.b is applied with a time delay t.sub.d to optimize the conditions to maximize So.

[0172] The most likely implementation is that V.sub.b1 is a positive voltage and voltage V.sub.b2 is a negative voltage with respect to the source S of the GFET. It is however possible to operate with any DC offset between the two voltages and even put one of them to 0. As shown in FIG. 10, between the low pass filter LF an impedance matching unit Zm can be added if the low pass filter LF is passive. The low pass filter LF allows only the signal corresponding to the charge the charge induced in the graphene channel (plus a possible DC offset) pass. After the low-pass filter LF an offset correction unit OC can be added. The signal So (see FIG. 10) can be read out at any time in the described sequence.

[0173] Here, an explanation of the mixing in terms of an ideal sine wave is given. Note that the mixing can be achieved with any periodic function that can be asymmetric (i.e. positive and negative parts are not equal).

[0174] An AC bias V.sub.bias (i.e. V.sub.b) with amplitude V1 and frequency f.sub.mb is applied to the source S of the GFET:

V.sub.bias=V.sub.1 cos(2πf.sub.mb)

[0175] Using the gate G of the GFET (called also herein “gate 1”), the charge carrier density of the graphene is modulated at a frequency f.sub.m (which can be the same or different as f.sub.mb):

n=C.sub.gate1.Math.(V.sub.2 cos(2πf.sub.m))

[0176] Where C.sub.gate1 is the capacitance of the gate G of the GFET, and V.sub.2 the amplitude of the modulation.

[0177] The conductivity of the graphene is:

σ=√{square root over (n*.sup.2+n.sup.2)}.Math.e.Math.μ

[0178] Where n* is the residual charge carrier density, n the average charge carrier density, e the electron charge and p the mobility.

[0179] The average charge carrier density in the channel is a sum of the charge carrier density induced by the gate as expressed above and n.sub.ind which is the carrier density induced in the graphene channel.

[0180] Now the current that comes out of the mixer is as follows:

[00001]$I=V_{\mathrm{bias}}.Math.\sigma .Math.\frac{W}{L}=V_1\cos \left(2\pi f\right).Math.\sqrt{n^{*2}+{\left(n_{\mathrm{ind}}+C_b{V}_2\cos \left(2\pi f+{\varphi }_1\right)\right)}^2}.Math.e.Math.\mu .Math.\frac{W}{L}$

[0181] Where W is the width of the device and L the length of the graphene channel.

[0182] It is important to notice that, mathematically, there will only be traditional mixing when: n*<<n.sub.ind+C.sub.bV.sub.2. To operate in this condition is not practical as it will require high voltages to be applied to the gate. In practice the device will be operated for n*.Math.n.sub.ind+C.sub.bV.sub.2.

[0183] From this formula it can be seen that when there is noise in the mobility it will be suppressed by using this modulation/demodulation technique. To demonstrate this, data is shown in FIG. 13, where a factor 10 lower noise compared to a DC (bias and gate voltage) read-out was achieved.

[0184] Moreover, a simulation of Embodiment 4 based on the above formula has been performed by the present inventors, and in FIG. 12, left the results plotting So of Embodiment 4 are shown. In FIG. 12, right a measurement of the implementation of Embodiment 4 in a real device is shown, to provide proof that the scheme works.

[0185] A person skilled in the art could introduce changes and modifications in the embodiments described without departing from the scope of the invention as it is defined in the attached claims.