FLEXIBLE INTERPOSER

Abstract

The present invention provides for an interposer subassembly that is suitable for an electronic system having at least one integrated circuit (1C) component. The interposer subassembly comprises a flexible base layer, having a first surface and an opposing second surface, at least one active electronic circuit component, operatively integrated within said flexible base layer, and at least one first patterned contact layer, provided on any one of said first surface and said second surface of said flexible base layer and which is configured to operably interface with said at least one active electronic circuit component and the at least one 1C component.

Claims

1. An interposer subassembly for an electronic system having at least one integrated circuit (IC) component, comprising: a flexible base layer, having a first surface and an opposing second surface; at least one active electronic circuit component comprising a thin film of semiconductor, operatively integrated and embedded directly within said flexible base layer; at least one first patterned contact layer, provided on any one of said first surface and said second surface of said flexible base layer, and configured to operably interface with said at least one active electronic circuit component and the at least one IC component.

2. An interposer subassembly according to claim 1, further comprising at least one second patterned contact layer, provided on said flexible base layer at a surface opposite to said first patterned contact layer, and configured to operably connect to any one or any combination of said at least one active electronic circuit component, said first patterned contact layer, and the at least one IC.

3. An interposer subassembly according to claim 2, wherein said at least one first patterned contact layer comprises a plurality of first contact elements having a first line pitch, and, said at least one second patterned contact layer comprises a plurality of second contact elements having a second line pitch.

4. An interposer subassembly according to claim 3, wherein said first line pitch is different to said second line pitch.

5. An interposer subassembly according to claim 2, further comprising at least one passive electronic circuit component, operatively integrated within said flexible base layer and operably connected to said at least one active electronic circuit component and/or said at least one first patterned contact layer and/or said at least one second patterned contact layer.

6. An interposer subassembly according to claim 5, further comprising at least one conductive via, extending through at least a portion of said flexible base layer between said first surface and said opposing second surface, configured to operably connect any one or any combination of said at least one active electronic circuit component, said at least one passive electronic circuit component, said at least one first patterned contact layer and said at least one second patterned contact layer.

7. An interposer subassembly according to claim 1, wherein said flexible base layer comprises at least one dielectric layer material integrated within at least a portion of said flexible base layer and/or on at least a portion of said first surface of said flexible base layer and/or on at least a portion of said opposing second surface of said flexible base layer.

8. An interposer subassembly according to claim 1, further comprising at least one thermal management layer, operatively coupled to said flexible base layer, and configured to transfer heat energy away from any one or any combination of said at least one active electronic circuit component, said at least one first patterned contact layer, said at least one second patterned contact layer, said at least one passive electronic circuit component, and said at least one conductive via.

9. An interposer subassembly according to claim 8, wherein at least a portion of said at least one thermal management layer is electrically insulating.

10. An interposer subassembly according to claim 8, wherein said at least one thermal management layer has a predetermined coefficient of thermal expansion (CTE).

11. An interposer subassembly according to claim 8, wherein said at least one thermal management layer is a heat sink and/or a heat spreader embedded within said flexible base layer and thermally conductively coupleable to the at least one IC component.

12. An interposer subassembly according to claim 1, wherein said semiconductor material has a predetermined dopant concentration.

13. An interposer subassembly according to claim 12, wherein said predetermined dopant concentration is a predetermined concentration profile gradation of dopants.

14. An interposer subassembly according to claim 1, wherein said at least one active electronic circuit component is a transistor.

15. An interposer subassembly according to claim 5, wherein said at least one passive electronic circuit component comprises a metal integrated into said flexible base layer.

16. (canceled)

17. An interposer subassembly according to claim 1, wherein said at least one first patterned contact layer is made of an electrically conductive material.

18. An interposer subassembly according to claim 17, wherein said a electrically conductive material comprises at least one metal.

19-20. (canceled)

21. An interposer subassembly according to claim 1, configured so as to provide a predetermined gradation of the coefficient of thermal expansion (CTE).

22. An electronic system comprising: interposer subassembly according to claim 1; at least one first electronic component mounted to and electrically connected to said interposer subassembly.

23. An electronic system according to claim 22, wherein said at least one first electronic component is at least partially encased within an encapsulant material.

24-26. (canceled)

27. An electronic system according to claim 22, wherein said encapsulant material comprises a polymer.

28. An electronic system according to claim 22, wherein said at least one first electronic component is electrically connected to said interposer subassembly by at least one wire bond.

29. An electronic systems according to claim 22, wherein said at least one first electronic component is electrically connected to said interposer subassembly in a flip-chip configuration.

30. An interposer subassembly according to claim 5, wherein said at least one passive electronic circuit component is any one of a resistor, capacitor, inductor and diode.

31. An interposer subassembly according to claim 1, wherein said flexible base layer is formed from any one or any combination of substrate, glass, polymer, cellulose and metal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Example embodiments of the description will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0035] FIG. 1 (Prior Art) is a simplified schematic illustration of a ball-grid-array (BGA) with an interposer provided between the integrated circuit (IC) die and the BGA, for example, in the Pentium II CPU;

[0036] FIG. 2 (Prior Art) is a simplified schematic illustration of a high-performance system (2.5D integration), where an interposer connects multiple IC's to each other, as well as, to a package substrate;

[0037] FIG. 3 (Prior Art) shows a schematic of a IPDiA (now Murata Integrated Passive Solutions) with PICS IPD (Passive Integrated Connective Substrate, Integrated Passive Devices) and external active dies in a flip-chip or chip-on-silicon technology;

[0038] FIG. 4 (PriorArt) shows an illustration of a simplified cross-sectional schematic of an organic interposer structure, utilising high-modulus organic materials (e.g. polymers);

[0039] FIG. 5 shows a simplified cross-sectional illustration of an example embodiment of the present invention, including a flexible interposer comprising, inter alia, embedded passive and active electronic components;

[0040] FIG. 6 (a) shows a simplified cross-sectional illustration of another example embodiment of the present invention, where a flexible interposer stack further comprises thermal management features, and FIG. 6 (b) shows a simplified cross-sectional illustration of another example embodiment of the present invention, where the heat sink connection is made through the interposer substrate directly to the PCB

[0041] (Printed Circuit Board);

[0042] FIG. 7 shows a simplified cross-sectional schematic illustration of a double-sided interposer structure “sandwiching” a layer of active devices between two interconnect layers;

[0043] FIGS. 8(a)-(c) are simplified illustrations of another example embodiment of the present invention, in form of a “strap-attach” fan-out flexible interposer, (a) top-view, (b) side-view of two-sided flip-chip Si IC and (c) one-sided flip-chip Si IC;

[0044] FIG. 9 is a simplified perspective illustration (flexible base layer shown as dotted line) of another example embodiment of the present invention in form of a “skirt” interposer suitable to replace wire bonding;

[0045] FIG. 10 is a simplified illustration of another example embodiment of the present invention, (a) in form of a folded, single-sided flexible interposer, and (b) in form of a double-sided flexible interposer, i.e. with through-substrate vias to shorten the routing path between two or more IC's;

[0046] FIG. 11 is a simplified illustration of another example embodiment of the present invention, in form of a flexible interconnect for 3D stacked IC's, so as to provide a replacement for through-silicon vias (TSV);

[0047] FIG. 12 is a simplified illustration of another example embodiment of the present invention, in form of an interposer including glue logic/interface matching for 3D vertically stacked Si IC's;

[0048] FIG. 13 is a simplified illustration of another example embodiment of the present invention, where the flexible interposer is in form of a ribbon cable with integrated active and passive electronic components;

[0049] FIGS. 14(a)-(c) are simplified illustrations of another example embodiment of the present invention where the Si IC is embedded in the flexible interposer (e.g. polymer), in, in particular, (a) a thinned Si IC (e.g. 2 μm) is embedded in the flexible interposer (ca. 10 μm to 20 μm), (b) the Si IC is recessed or embedded in the flexible interposer substrate and (c) shows a double-sided flexible interposer with Si IC on the upper side embedded in rigid or flexible encapsulation or board/package;

[0050] FIGS. 15(a)-(c) are simplified illustrations of another example embodiment of the present invention, in form of a double-sided flexible interposer with Si IC's on both sides, and embedded in a rigid or flexible encapsulation or board/package, in particular, showing the manufacturing steps (a) where the Si IC is attached to the upper side of the flexible interposer and embedded in passivation whilst on a glass carrier, (b) where the glass carrier is removed and a second Si IC is mounted to the bottom side of the flexible interposer, and (c) where the bottom mounted Si IC is embedded in passivation, with one or more vias suitable to connect at least one of the Si IC's to the wider system, one of more of the Si IC's may be an embedded sensor, for example, for use in wearables, where an external sensor (e.g. for skin contact) is built onto or into the flexible interposer;

[0051] FIGS. 16(a) and 16(b) are simplified illustrations of another example embodiment of the present invention, with embedded Si IC's on a flexible interposer in a rigid or flexible package, where passivation (PASS) or package material aids heat dissipation (as well as providing predetermined mechanical properties), (a) on glass and (b) with bumps/balls;

[0052] FIG. 17 is a simplified illustration of another example embodiment of the present invention, where a fully integrated electronic assembly comprises a flexible interposer and other system components, as well as, a battery that may also be flexible;

[0053] FIG. 18 is a simplified perspective illustration of a flexible interposer interfaced to a flexible IC, or to another flexible interposer;

[0054] FIGS. 19(a)-(j) are illustrations of manufacturing steps (a) to (j) for a ‘mount silicon first’ approach, and

[0055] FIGS. 20(a)-(k) are illustrations of manufacturing steps (a) to (k) for embedding SI IC's and other components in accordance with the ‘mount silicon first’ process shown in FIG. 19.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

[0056] The described example embodiments relate to interposer technology. The interposer generally serves as an intermediate subassembly that can be positioned in between, and electrically interconnecting, one component or substrate and another component or substrate with the interposer positioned in between, as well as, interconnecting.

[0057] Throughout the specification, the term “connected” is understood to mean a direct connection such as electrical, mechanical or magnetic connection between the things that are connected. The term “coupled” is understood to mean a direct or indirect connection (i.e. through one or more passive or active intermediary devices). The term “scaling” may be understood to generally refer to converting one layout pitch to another layout pitch. Further, unless otherwise specified, the use of ordinal adjectives, such as, “first”, “second”, “third” etc. merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. Orientation terminology, such as, “horizontal” is understood with respect to a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” may refer to a direction perpendicular to the horizontal as defined previously. Prepositions, such as, “on”, “side”, “higher”, “upper”, “lower”, “over”, “bottom” and “under” may be understood with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation the electrical interconnects or the electronic package.

[0058] Referring now to FIG. 5, a simplified cross-section schematic illustration of an example embodiment of the flexible interposer 100 of the present invention is shown. The flexible interposer 100 comprises, inter alia, a flexible substrate or member 102 having active electronic components 104, as well as, passive electronic components 106 incorporated therein. Electrically conducting interconnects, such as, for example, conductor layers or signal lines 108 and vias 110, are incorporated into and on the flexible substrate or member 102, so as to connect and/or couple contact(s) 112 provided on the top or bottom surface of the flexible substrate or member 102. Bumps or balls 114 or other joining means known in the art may then be used to provide an interface with an external component, such as, a Printed Circuit Board (PCB) or another microchip, die or Integrated Circuit (IC), but may also be used to interconnect stacked multiple interposers 100.

[0059] Where a flexible interposer 100 is interfaced to a flexible Integrated Circuit (IC), or to another flexible interposer 100, a variety of techniques may be used to attach them. ‘Flip chip’ type attachment using balls or bumps 114 may be used, as mentioned above, or conductive adhesives and/or non-conducting adhesives may be used, as is known in the art. Alternatively the flexible interposers 100 (or flexible interposer and flexible IC) may both be arranged with their electrical contacts facing in the same direction (as illustrated in FIG. 18). One or more electrical contacts 115a on a flexible interposer 100a may be electrically connected to one or more electrical contacts 115b on the attached interposer 100b or flexible IC using a printed wire bond 117, for example using conductive ink. These electrical connection(s) may be sufficient to secure the two flexible structures together or additional means may be required, for example using non-conductive adhesive between the two flexible structures 100a, b.

[0060] The active 104 and passive 106 electronic components embedded in the interposer(s) 100 may include transistors, capacitors, inductors and/or resistors, whilst the interconnects (conducting layers, vias) 108, 110 and contacts 112 are configured to provide contact redistribution. Advantageously, the interposer of the present invention is capable of providing redistribution at a finer line pitch (e.g. of the order of 1 μm) than currently known organic (i.e. flexible) interposers.

[0061] In addition to providing a thin, flexible form factor and a system volume reduction, the flexible interposer 100 of the present invention incorporates active 104 and passive 106 components into the fabric (i.e. the substrate or member 102) of the interposer 100 allowing for further system volume and assembly cost reductions. For example, discrete passive/active components may be replaced with integrated equivalents, therefore, eliminating one or more assembly steps, as well as, reducing the cost of materials and allowing for optimal component positioning (e.g. immediately adjacent to an IC terminal). Further, by performing some of the functions that are conventionally performed in Si (silicon) IC's, the interposer 100 allows for a simplified and more compact Si IC design. Even more, an entire Si IC may be removed from the system by performing its function(s) in the interposer 100.

[0062] (i) Thermal Management Feature(s)

[0063] Referring now to FIGS. 6 (a) and (b), the interposer assembly of the present invention may comprise thermal management features, such as, for example, thermally conducting/dissipation layer(s) or inclusions 116 that may be embedded in the flexible interposer stack. Such features may supplement or replace thermal management features in the adjoining components, e.g. in a chip package if present (e.g. heat spreader 114) or in a PCB (e.g. heat sink). In case the thermal management feature(s) are also electrically insulating (e.g. using carbon black or alumina, i.e. Al.sub.2O.sub.3), such feature(s) may also replace an inter-metal dielectric or passivation layer of the interposer. Such layers, whether electrically insulating or otherwise, may then connect to “islands” or heat sink features in a PCB (122) or package and provide a thermal contact with any embedded Si IC.

[0064] The flexible interposer 100 integrity may also be optimised by incorporating coefficient of thermal expansion (CTE) gradations through the layers of the interposer assembly stack. For example, a layer adjacent to the Si IC may be formed from a material having a CTE that is similar to that of Si, whilst a layer adjacent to the PCB or package may be formed from a material that has a similar CTE to that of the PCB or package compound.

[0065] As shown in FIG. 6(b), an embedded ground plane may be utilised as a heat dissipation layer or heat sink 116. Heat sink connections may be made for an attached Si IC 120 through the interposer substrate 102 directly to the PCB 122. Wire bonds 118 or other signal connections may be made from the Si IC 120 to the PCB 122 through the interposer 100. Further, a predetermined interposer architecture may assist heat dissipation vertically or separate out components laterally.

[0066] (ii) Manufacture

[0067] In general, embodiments of the interposer 100 of the present invention may be manufactured by using known thin-film and lithographic techniques. For example, materials may be deposited in layers by a technique, such as vapour deposition (physical, e.g. sputter or chemical, e.g. PECVD), vacuum deposition (e.g. thermal or e-beam evaporation); coating (spin, dip, blade, bar, spray, slot-die), printing (jet, gravure, offset, screen, flexo), pulsed-laser deposition (PLD), atomic layer deposition (ALD) and/or other currently known techniques. Patterning of deposited materials may be performed by CBD (coat, bake, develop) and photo-lithography (i.e. exposure), electron beam lithography, x-ray lithography, ion-beam lithography, printing and/or other currently known techniques. The patterning may be combined, where applicable, with wet and/or dry (plasma) etching, ablation, milling, and/or lift-off patterning.

[0068] Different layer types of the interposer assembly may be as follows:

[0069] Interposer Substrates

[0070] Any suitable materials may be used as a substrate 102, which may be composed from one or more layers of such materials. The substrate 102 may be flexible, comprising any one or more materials from the following list: [0071] glass (rigid or flexible); polymer (e.g. polyethylene naphthalate, polyethylene terephthalate; polymethyl methacrylate; polycarbonate, polyvinylalcohol; polyvinyl acetate; polyvinyl pyrrolidone; polyvinylphenol; polyvinyl chloride; polystyrene; polyethylene naphthalate; polyethylene terephthalate; polyimide, polyamide (e.g. Nylon); poly(hydroxyether); polyurethane; polycarbonate; polysulfone; parylene; polyarylate; polyether ether ketone (PEEK); acrylonitrile butadiene styrene;1-Methoxy-2-propyl acetate (SU-8); polyhydroxybenzyl silsesquioxane (HSQ); Benzocyclobutene (BCB)); Al2O3, SiOxNy; SiO2; Si3N4; UV-curable resin; Nanoimprint resist; photoresist; polymeric foil; paper; insulator-coated metal (e.g. coated stainless-steel); cellulose.

[0072] Relatively thick substrate layers may be used for embedding IC's 120 and/or electronic components 104, 106, as well as, for decoupling the interposer's metal layers. This might necessitate filling any vias 110 by plating and defining the patterns by photo-patterning.

[0073] Some embodiments of the interposer 100 may not comprise a substrate 102, as such. The conductors 108, 110 and active 104 and passive 106 components may be separated by one or more dielectric materials (e.g. as listed under “Dielectrics”) and there may be no further structural materials in such examples. In other embodiments both substrate and dielectric materials may be present in the substrate 102.

[0074] Dielectrics

[0075] Elements of the interposer 100, and of the active 104 and/or passive 106 components integrated within the interposer 100, may comprise a dielectric material. Examples of suitable materials include: [0076] metal oxides such as Al2O3, ZrO2, HfO2, Y2O3, Si3N5, TiO2, Ta2O5; metal phosphates such as Al2POx; metal sulphates/sulphites such as HfSOx; metal nitrides such as AlN; metal oxynitride such as AlOxNy; inorganic insulators such as SiO2, Si3N4, SiNx; spin on glass (such as polyhydroxybenzyl silsesquioxane, HSQ), polymeric dielectric materials (such as Cytop, a commercially available amorphous fluoropolymer), 1-Methoxy-2-propyl acetate (SU-8), benzocyclobutene (BCB), polyimide, polymethyl methacrylate, polybutyl methacrylate, polyethyl methacrylate, polyvinyl acetate, polyvinyl pyrrolidone, polyvinylphenol, polyvinylchloride, polystyrene, polyethylene, polyvinyl alcohol, polycarbonate, parylene, silicone; UV-curable resins; Nanoimprint resists; or photoresists. The dielectric material may have a relatively low dielectric constant (low-K, e.g. Cytop, HSQ, parylene) or a relatively high dielectric constant (high-K, e.g. Ta2O5, HfO2).

[0077] Metal Layers

[0078] Metals may be used for the interposer conductors (i.e. interconnects 108, vias 110, contacts 112) and/or for the conductive elements of integrated active 104 or passive 106 components. The conductive elements may include, for example, capacitor plates, inductor windings or transistor electrodes. There are numerous suitable materials, including: [0079] metals, such as, Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys, such as, MoNi, Mo Cr, AlSi; transparent conductive oxides, such as, ITO, IZO, AZO; metal nitrides, such as, TiN; carbon materials, such as, carbon black, carbon nanotubes, graphene; conducting polymers, such as, polyaniline, PEDOT:PSS; or semiconductor material.

[0080] Metal features may comprise one or more layers of the same or different metals, as is well known in the art. Thicker metal layers may be formed to minimise electrical resistance, using a high aspect ratio (i.e. layer thickness/layer width) in order to retain high line density (ca. 1 μm track plus the gap pitch). For example, some Si IC's may draw ca. 2A (Ampere) current at 1.3V (Volt), so, the metal tracks in the interposer 100 may be of the order about 2 μm thick. Options to fulfil these requirements include (i) dry etching, to preserve definition at thickness, (ii) plating, (iii) the use of low resistance metals, such as gold, silver, copper and/or aluminium, or (iv) planarisation techniques.

[0081] Shielding metal layers may be built into the flexible interposer 100, e.g. to reduce any unwanted coupling between any components. Additionally or alternatively, shielding may protect ICs against external phenomena such as X-rays or other electromagnetic or particle radiation (e.g. beta-particles, gamma-rays), or may incorporate magnetic shielding properties. Such functionalities provide the flexible interposer 100 with packaging capabilities.

[0082] In some embodiments, through-film vias 110 and contacts 112 at both surfaces of the interposer 100 are necessary. Examples for producing such vias and contacts are as follows: [0083] Metal pad areas may be patterned directly on the (e.g. glass) carrier, or on an intervening release layer, before spin-coating a polymer film. Vias 110 may then be etched through the film (e.g. with an oxygen plasma dry etch, after photo-resist patterning), and connections may be made to the upper layers. The connections may be made with an upper metal layer that routes over positively sloped sidewalls around the etched vias to form connections, or by other methods suitable to fill the vias 110, such as, electro/electro-less plating techniques. In this method, the vias in the substrate 102 connecting to the bottom pad may consist of a limited area, with the pad extending beyond them. [0084] A polymer film is deposited on a (e.g. glass) carrier, then, vias are etched, in this particular case, with positive sidewalls. A metal is then deposited, allowing for no breakages at the via edges, thus, routing the metal both down, to contact the glass, and up, to the top of the polymer film (forming substrate 102). In this method, the bottom pad area is defined by the size of the via, leading to large etched regions of the polymer film. [0085] Alternatively, through-film vias may be produced mechanically instead of using deposition processes.

[0086] FIG. 7 shows an illustration of a double-sided interposer structure that may be adopted in order to provide a high routing density and allow access to contacts on both surfaces of the interposer by, for example, sandwiching a layer of active devices between two interconnect layers.

[0087] Semiconductors

[0088] Any known thin film semiconductor material may be used in the active devices 104 integrated into the interposer 100. Such materials may include: [0089] compound semiconductors, such as GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb; Metal oxides, their alloys and doped variants, such as ZnO, ZnSnO, NiO, NiSnO, SnO, SnO2, Sn(y)O, SnLiO, SnAlOx, Cu2O, CuZnO, CuLiO, CuAlO2, In2O3, LiZnO, InSnO (ITO), InZnO (IZO), HfInZnO (HIZO), InGaZnO (IGZO), La2O2Te, spinel oxides; Metal oxynitrides, e.g. ZnxOyNz; Metal halides, such as CuI, CuSnl; Inorganic semiconductors, such as amorphous, microcrystalline or nanocrystalline Si; Organic semiconductors, such as CuPc, pentacene, PTCDA, methylene blue, Orange G, rubrene; polymer semiconductors, such as PEDOT:PSS, POT, P3OT, P3HT, polyaniline, polycarbazole; 2D materials, such as graphene; Chalcogenides, such as, MoS2, GeSbTe; and perovskites, such as, SrTiO3, CH3NH3PbCl3, H2NCHNH2PbCl3, CsSnI3. These semiconductor materials may also be doped or contain a doping gradient and may be n-type or p-type.

[0090] When manufacturing interposer 100, in order to remove any maximum interposer size limitations set by the field of view of the lithography equipment, features in adjacent exposures may be connected in different layers, or by using known techniques such as reticle stitching. Also, Si IC's 120 and other components may be assembled by ‘pick and place’ (or similar processes) onto the flexible interposer 100 part-way through the interposer manufacturing process flow.

[0091] The manufacturing process may use the “Mount silicon first” approach, where system components (IC's, discrete components) are temporarily adhered to a carrier, before the components are coated and patterned with dielectric. A metal layer connects the components into a subsequent active/passive flexible interposer layer. After that, a redistribution layer (RDL) is provided, the systems are diced, detached from the carrier and attached to a PCB or other destination. FIGS. 19 (a) to (j) illustrate the process including the steps (a) glass (or SI) carrier, (b) adhesive coating, (c) place SI IC's and any components, contacts-side upwards, (d) coat, pattern (windows), cure thick PI (or other organic dielectric), (e) metal deposition and patterning, (f) TFT stack processing (semiconductors, dielectric, metal lines, etc. forming active and passive components and tracking), (g) final passivation and RDL (metal contacts and vias) layers, (h) dice, (i) pick/place, (j) attach (solder/ACP/etc.) to system level PCB, where the interposer comprising layers from step (e) (i.e. ‘metal deposition and patterning’ to step (g) (i.e. final passivation and RDL′) inclusive, i.e. the interposer is in effect being manufactured on top of the silicon IC's (SI IC's).

[0092] The electronic connections between the interposer and Si IC's 120 (and other system components) may be made using any appropriate conventional techniques, for example (i) thermosonic/ultrasonic bonding or soldering to connect a Si IC 120 to the flexible interposer 100 without any anisotropic conductive paste (ACP) or bumps, (ii) an adhesive layer, e.g. ACP, or (iii) “Printed wire bond”, so as to connect Si IC's 120 that are embedded, contact side upwards, in the flexible interposer 100, as illustrated in FIG. 18 for connecting flexible interposers 100a, 100b, to each other or to respective flexible IC's.

[0093] The manufacturing process may include testing, such as, an in-line flexible interposer 100 functional test that is performed prior to completion of the flexible interposer stack, ensuring that Si IC's 120 are only attached to “working” interposers 100. Further, in-line measurement and trimming of passive components may be performed, e.g. by laser, to ensure accurate values.

[0094] Yield optimisation and/or trimming may be provided, e.g. via a laser PROM (programmable read-only memory).

[0095] (iii) Geometric Arrangement Examples

[0096] Examples of various geometric arrangements are now described with reference to FIGS. 8 to 17. However, it is understood by the person skilled in the art that the present invention is not limited to those specific examples and any other suitable arrangement may be used when incorporating the flexible interposer 100 of the present invention.

[0097] FIG. 8 (a) illustrates a top-view of a “strap attach” fan-out flexible interposer 100, incorporating PCB contacts 112a on the underside of the interposer 100, where interposer 100 connections may be either (b) two-sided (e.g. IC contacts 112b on the upper side for a flip-chip silicon IC 120, and PCB contacts 112a on the lower side) or (c) one-sided (e.g. on the lower side both for PCB contacts 112a and for IC contacts 112b, for a Si IC 120 mounted with its pads facing upwards on a PCB (not shown).

[0098] FIG. 9 illustrates an example of a “skirt” interposer 100 that may be used to replace wire bonding, such as that used inside conventional Si IC packages, i.e. connecting the IC pads 124 to a lead frame. After the Si IC 120 has been attached to the package chassis or other support structure, interposer 100 is placed onto the top side of Si IC 120. The interposer tracks 111 are then bonded, e.g. ultrasonically bonded, to the IC pads 124 at one end, and to the lead-frame ‘leg’ pads 126 at the other. In some manufacturing processes, all IC pad-to-interposer connections are made substantially simultaneously, then all lead-frame leg pad-to-interposer connections are made substantially simultaneously in a subsequent step.

[0099] FIG. 10 (a) illustrates an example of a folded, single-sided flexible interposer 100, providing a smaller footprint stacked system and (b) a folded, double-sided flexible interposer 100, i.e. with through-substrate vias, to shorten the routing path between two or more IC's 120. Both examples provide a potentially simpler assembly process than placing components/IC's on opposing sides of the interposer 100, and both could, for example, connect IC's and other components in a 2.5D SiP.

[0100] FIG. 11 illustrates an example of a flexible interposer 100 interconnecting 3D stacked IC's, so as to provide a lower cost alternative to through-silicon vias (TSV).

[0101] FIG. 12 illustrates an example of a flexible interposer 100 for 3D vertically stacked silicon IC's, e.g. including glue logic/interface matching. Glue logic may be incorporated into an interposer when connecting off-the-shelf ICs with different I/O protocols or characteristics.

[0102] FIG. 13 illustrates an example of a flexible interposer assembly 100 (i.e. flexible IC) as a PCB-to-PCB ribbon cable with integrated active components and/or passive components.

[0103] FIG. 14 (a) illustrates an example for connecting a thinned Si IC 120 on a flexible interposer, e.g. a 2 μm thick Si IC on a 10 μm thick flexible interposer assembly (i.e. flexible IC), providing a fully flexible “large area” IC, where the Si IC 120 may be embedded in the flexible interposer assembly (i.e. flexible IC, e.g. 10 μm-20 μm). FIG. 14(b) illustrates an example for a recessed or embedded Si IC 120 in the flexible interposer substrate 102. This arrangement provides improved mechanical performance, and advantages over known approaches. FIG. 14 (c) shows a more detailed illustration of the example for a double-sided flexible interposer with Si IC on both sides, embedded in rigid or flexible passivation, encapsulation or board/package.

[0104] FIG. 15 is a simplified illustration of another example embodiment of the present invention, in the form of a double-sided flexible interposer with Si IC's on both sides, and embedded in a rigid or flexible passivation, encapsulation or board/package. One or more of the Si IC's may be an embedded sensor. An example of an interposer assembly including embedded sensors may be used, for example, in wearable electronic devices, where an external sensor is built onto or into the flexible interposer, e.g. for skin contact. FIGS. 15(a) to 15(c) reflect the steps in manufacture. In particular, in FIG. 15(a) a Si IC 120 is attached to the upper side of a flexible interposer and embedded in passivation whilst the flexible interposer (also called FlexIC) is on a glass carrier. In FIG. 15(b) the flexible interposer 100 has been detached from the glass carrier and in (c) a second Si IC 120 has been mounted to the underside of the flexible interposer and is embedded in passivation. One or more vias 128 connect one or both Si IC's 120 to the wider system.

[0105] FIG. 16 illustrates an example for embedding silicon IC's and/or sensors, where Si IC's 120 are embedded in a flexible interposer assembly (on the flexible interposer) in a rigid or flexible package. A passivation (PASS) layer or package material may be configured to aid heat dissipation. Here, short separation from the PCB (short interposer tracks) can minimise thermal issues. As illustrated in FIG. 16(a) the interposer 100 (i.e. FlexIC) is manufactured on a glass carrier, the silicon IC's 120 are attached to the interposer 100, and passivation is applied. The interposer 100, Si IC's 120 and passivation are then removed from the carrier and prepared for subsequent attachment to a package or application circuit, e.g. by attaching solder balls to the interposer (FIG. 16(b)).

[0106] A related example for embedding silicon ICs and other components is illustrated in FIGS. 20 (a) to (k) and is an application of the interposers described herein to fan-out wafer level packaging (FOWLP). In this approach, SI IC's and any other components are temporarily bonded to a carrier (e.g. glass, silicon—see step (a)), with their electrical contacts facing towards the carrier (see steps (b) and (c)). A rigid or flexible package is formed around and on top of the IC's and components, in an over-moulding step (see step (d)). This produces a reconstituted wafer of SI IC's and any other components, which is then removed from the carrier and inverted. The reconstituted wafer is then typically self-supporting through the subsequent steps, however, it may be temporarily bonded to a carrier (with the electrical contacts of the SI IC's and components facing away from the carrier), if necessary. Similar steps to those used in the ‘mount silicon first’ approach (see FIGS. 19 (a) to (j)) are employed to manufacture an interposer on top of the reconstituted wafer, making contact with the exposed SI IC's and other components within. This method may be used to produce a system-in-package (SiP) with high density contact redistribution and with active and passive components integrated into the interposer. In comparison to the ‘mount silicon first’ approach, this method provides several advantages, such as, for example, that the contacts of the SI IC's and components are presented at a planarised surface, and that the SI IC's and components are fully encapsulated as a part of the process. The steps illustrated in FIG. 20 include (a) glass (or silicon) carrier, (b) adhesive coating, (c) place SI IC's and any components, contacts-side downwards, (d) encapsulate or overmould to form a ‘reconstituted wafer’, (e) remove reconstituted wafer from carrier, invert, optionally place on a carrier, (f) dielectric deposition and patterning, (g) metal deposition and patterning, (h) TFT stack processing (semiconductors, dielectrics, metal lines, etc. forming active and passive components and tracking), (i) final passivation and RDL (metal contacts and vias) layers, (j) dice, (k) attach (solder/ACP/etc.) to system level PCB.

[0107] (iv) Example Interposer Functions

[0108] Examples of interposer functions may include: [0109] An Application Specific Integrated Circuit (ASIC) interposer may eliminate glue-logic (incorporating active components and/or passive components), fan-in/fan-out (multiplexing and serial/parallelization), level shifters, etc. from one or more silicon ASICs in a system. [0110] Electrostatic Discharge (ESD) protection and I/O buffers may be provided in the interposer of the present invention, consequently, reducing Si area required. Such ESD protection may be provided by a diode structure (Schottky diode) as described in WO2019/116020A1 (incorporated herein by reference). [0111] Power circuitry for low power states, i.e. low off-current, on a die by die basis with TFTs, e.g. IGZO TFTs, in the interposer. [0112] Memory circuits in the flexible interposer, e.g. using a laser fuse-based PROM or non-volatile memory elements. [0113] TFT circuits, e.g. for RFID, energy harvesting, integrated into the flexible interposer. [0114] Programmable connections between system components, built into (and optionally accessible from) the interposer.

[0115] (v) Example Systems

[0116] Examples of systems comprising the flexible interposer of the present invention may include a flexible 2.5D System in Package (SiP) interposer with integrated active and/or passive components, configured to reduce overall SiP bill of materials (BoM). An example system may be a Flex 2.5D SiP interposer connecting a processor with ADC and sensor(s), or a Flex 2.5D SiP with multiplexers/demultiplexers built into the interposer's TFT circuits (active layer).

[0117] Other systems may comprise an antenna, e.g. for a 5G chipset that is included in the package on a flexible interposer, providing reduced cost and area.

[0118] The interposer of the present invention may also provide for an improved/simplified print-head system design. Currently a complex system of MEMs and ASICs on flexible PCBs of different resolutions are employed for this application.

[0119] FIG. 17 illustrates an example of a fully integrated electronic assembly comprising a flexible interposer 100, Si IC(s) 120, a battery (which may be flexible) and other system components.

[0120] Example embodiments of wearable electronics systems may include (i) systems with one or more embedded external sensor(s) (e.g. for skin contact) connected onto or into the flexible interposer 100, (ii) smart ‘suits’, e.g. for doctors/surgeons, coupled with Virtual (VR) or Augmented Reality (AR), (iii) watches, fitness monitors etc. enabling flexibility and thinner form factors, (iv) systems for health monitoring, e.g. continuous glucose monitors or pumps, heart rate monitors, blood pressure monitors, wound management or body area networks.

[0121] Other example embodiments of the present invention may include: [0122] medical implants, e.g. subcutaneous (e.g. to detect bio-electrical signals such as ECG or biochemical concentrations such as glucose) or cochlear implants. [0123] Medicine packaging, e.g. with displays/speech, for improved compliance. [0124] Using the interposer assembly for connecting a large number of sensors, distributed over a large area, to a master processor, e.g. in autonomous vehicles, or for connecting multiple separate high-performance computing cores with high density, high bandwidth wiring whilst performing some of the functions outlined above. [0125] Embedded active electronics within a battery cell/pack, e.g. for charge/discharge management and protection, indicators, etc. [0126] Display driver attach and fan-out with active and/or passive components that are built-in allowing “flexible” and easier placement, e.g. may be used in automotive interior displays that are built into curved dashboards, pillars, overhead lighting, etc. Embodiments may also be used more generally as an active, transparent display backplane, including micro LED displays. [0127] Vibration monitors, where the flexible interposer assembly could improve the system sensitivity, as it is less rigid. [0128] MEMS interposer, where movement and/or flexibility is required.

[0129] As can be understood from the information disclosed, the present invention provides a series of advantages, such as, (i) reduced manufacturing costs, for example by employing low temperature thin-film, polymer-based technology; such cost reductions may enable current IC-containing products, even low-cost micro-controllers, to be offered at a significantly lower price point, by using bare, instead of packaged, die, (ii) flexibility, (iii) improved thermal insulation properties, (iv) a large area, as the interposer assembly could be used in applications where the final product is relatively large, e.g. the full (e.g. 8″ diameter) wafer or panel size may be used as the interposer, (v) substantial optical transparency, (vi) rapid turn-around design, for example by employing low temperature manufacturing processes, and (vii) very thin form factors compared to existing flexible interposers, e.g. FR4 (at hundreds of μm) limits the thinness of current systems, wherein the flexible interposer assembly may allow an order of magnitude thinner than the current limits.

[0130] It is understood by the person skilled in the art that other packaging (or ‘advanced integration’) technologies employing a fan-out element may also be improved by using an interposer assembly of the present invention, i.e. with integrated active and passive components. One example may be a wafer-level fan-out packaging (WLFO or FOWLP) in which silicon wafers are diced and ‘reconstituted’ before being attached to a redistribution layer (RDL). There are variants of this approach to packaging, e.g. chip-first/RDL-last fan-out and RDL-first/chip-last fan-out, however the interposers described in this disclosure may in any case enhance the functionality of the RDL whilst potentially simplifying the design of the silicon chip, by performing some of that chip's functionality in the interposer.

[0131] It will be appreciated by persons skilled in the art that the above embodiment(s) have been described by way of example only and not in any limitative sense, and that various alterations and modifications are possible without departing from the scope of the invention as defined by the appended claims.