Radio Frequency Receiver and Method for Down-Converting Signals to Baseband Signal Components

Abstract

A radio frequency receiver comprising mixer circuitry to down-convert a received signal, which is transported on a signal line to baseband signal components, is provided. The mixer circuitry comprises a plurality of switched capacitors, each connected to the signal line through a signal side node and to a corresponding switch through a switch side node. In this context, a voltage is sensed at each switch side node of the plurality of switched capacitors and is read out through a respective grounded capacitor.

Claims

1. A radio frequency receiver comprising: a mixer circuitry configured to down-convert a received signal that is transported on a signal line to baseband signal components, wherein the mixer circuitry comprises a plurality of switched capacitors, each connected to the signal line through a signal side node and to a corresponding switch through a switch side node, wherein a voltage is sensed at each switch side node of the plurality of switched capacitors and is read out through a respective grounded capacitor.

2. The radio frequency receiver according to claim 1, wherein the voltages at the switch side nodes of the plurality of switched capacitors correspond to baseband signal components.

3. The radio frequency receiver according to claim 2, wherein the mixer circuitry comprises: an even number of mixing paths, each comprising at least one of the plurality of switched capacitors.

4. The radio frequency receiver according to claim 3, wherein the mixer circuitry further comprises: a plurality of read-out switches coupled between each of the switch side nodes and the respective grounded capacitor.

5. The radio frequency receiver according to claim 4, further comprising: clock generating circuitry configured to generate at least four-phase non-overlapping clocks to drive the plurality of switched capacitors and the plurality of read-out switches.

6. The radio frequency receiver according to claim 5, wherein the switched capacitors are driven in rotation such that at a given clock phase, at least two switched capacitors are out of phase to each other and are connected in series.

7. The radio frequency receiver according to claim 6, further comprising: input circuitry configured to transform the received signal into a differential signal having a positive and a negative partial signal.

8. The radio frequency receiver according to claim 7, wherein the input circuitry further comprises an impedance matching network that corresponds to a low-loss LC network.

9. The radio frequency receiver according to claim 8, wherein the mixer circuitry further comprises: a first terminal and a second terminal configured to receive the positive and the negative partial signal of the differential signal, respectively.

10. The radio frequency receiver according to claim 1, wherein the mixer circuitry further comprises: bias switches configured to set a common-mode bias voltage of the mixer circuitry and a plurality of read-out switches through an external supply.

11. The radio frequency receiver according to claim 1, further comprising: output circuitry coupled to the mixer circuitry configured to output the baseband signal components.

12. The radio frequency receiver according to claim 1, further comprising: an antenna for receiving radio frequency signals.

13. A method for down-converting a received signal that is transported on a signal line to baseband signal components in a radio frequency receiver comprising mixer circuitry, wherein the method comprises: connecting each of a plurality of switched capacitors to the signal line through a signal side node; and connecting each of the plurality of switched capacitors to a corresponding switch through a switch side node; sensing a voltage at each switch side node of the plurality of switched capacitors; and reading out the sensed voltage through a respective grounded capacitor.

14. The method according to claim 13, wherein the method further comprises: arranging an even number of mixing paths, each comprising at least one of the plurality of switched capacitors.

15. The method according to claim 13, wherein the method further comprises: driving the switched capacitors in rotation such that at a given clock phase at least two switched capacitors are out of phase to each other and are connected in series.

16. The radio frequency receiver according to claim 1, wherein the mixer circuitry comprises: an even number of mixing paths, each comprising at least one of the plurality of switched capacitors.

17. The radio frequency receiver according to claim 1, wherein the mixer circuitry further comprises: a plurality of read-out switches coupled between each of the switch side nodes and the respective grounded capacitor.

18. The radio frequency receiver according to claim 1, further comprising: clock generating circuitry configured to generate at least four-phase non-overlapping clocks to drive the plurality of switched capacitors and a plurality of read-out switches.

19. The radio frequency receiver according to claim 1, further comprising: input circuitry configured to transform the received signal into a differential signal having a positive and a negative partial signal.

20. The radio frequency receiver according to claim 19, wherein the mixer circuitry further comprises: a first terminal and a second terminal configured to receive the positive and the negative partial signal of the differential signal, respectively.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0021] The above, as well as additional features, will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.

[0022] FIG. 1a shows a top-plate mixing technique for switched R-C mixing path.

[0023] FIG. 1b shows a bottom-plate mixing technique for switched R-C mixing path.

[0024] FIG. 2 shows a wireless receiver using bottom-plate configuration according to the prior art.

[0025] FIG. 3 shows a block diagram of the radio frequency receiver, according to an example of the first aspect.

[0026] FIG. 4 shows a first embodiment of the mixer circuitry, according to an example of the first aspect.

[0027] FIG. 5a shows the read-out technique for a single-ended configuration at a clock phase of 0 degrees, according to example embodiments.

[0028] FIG. 5b shows the read-out technique for a single-ended configuration at a clock phase of 90 degrees, according to example embodiments.

[0029] FIG. 6a shows the read-out technique for a fully differential configuration at a phase of 0 degrees, according to example embodiments.

[0030] FIG. 6b shows the read-out technique for a fully differential configuration at a phase of 180 degrees, according to example embodiments.

[0031] FIG. 7 shows a second embodiment of the mixer circuitry, according to an example of the first aspect.

[0032] FIG. 8 shows a flow chart of an embodiment, according to an example of the second aspect.

[0033] All the figures are schematic, not necessarily to scale, and generally only show parts that are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.

DETAILED DESCRIPTION

[0034] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout.

[0035] FIG. 1a, FIG. 1b and FIG. 2 have already been described above.

[0036] FIG. 3 illustrates a block diagram of the radio frequency receiver 10 according to the first aspect. The radio frequency receiver comprises mixer circuitry 11, clock generating circuitry 12, input circuitry 13, output circuitry 14, and an antenna 15. The input circuitry 13 receives a radio frequency signal through the antenna 15 and transforms the received radio frequency signal into a differential signal having a positive partial signal RF+ and a negative partial signal RF−, which are not shown in FIG. 3. In this context, the antenna 15 can be generalized as a radio frequency signal source with a series source resistance. The transformation of the received signal into the differential signal can be achieved via, for example, a balanced to unbalanced radio frequency transformer (Balun) with a preferable turns ratio.

[0037] The input circuitry 13 might further comprise a low-loss LC network to perform impedance matching at the input side that is coupled to the mixer circuitry 11. The functionalities and constructions of a Balun and an LC impedance matching network are known in the art. Therefore, these circuits are not described herein in greater detail. Instead of receiving radio frequency signals through the antenna 15, the input circuitry 13 may comprise radio frequency connectors to receive signals via, for example, coaxial cables.

[0038] The clock generating circuitry 12 comprises, for instance, frequency divider circuitry, for example, a modulo counter to provide non-overlapping clocks. The number of clock phases and the duty cycle depend on the number of mixing paths utilized in the mixer circuitry 11. In the following embodiments, four-phase non-overlapping clocks are illustrated with a 25% duty cycle that are generated by a divide-by-2 circuit. However, the claims are not limited to only this arrangement and any divide-by circuit of N order with a different duty cycle or other circuitry to generate multi-phase clocks is considered to fall within the scope of the claims.

[0039] The mixer circuitry 11 performs modulation of the differential radio frequency signal, and with respect to the clock phases that drive the mixing paths, the differential in-phase baseband signal components I+, I− and the differential quadrature baseband signal components Q+, Q− are fed to the output circuitry 14 that is coupled to the mixer circuitry 11. The output circuitry 14 performs differential amplification such that the output is proportional to the difference between the two inputs. The output circuitry 14 outputs the in-phase baseband signal component I and the quadrature baseband signal component Q.

[0040] FIG. 4 illustrates a first example embodiment of the mixer circuitry according to the first aspect. The differential signal from the input circuitry 13 is transported on the signal lines 41, 43 of the mixer circuitry 11. Herein, the mixer circuitry 11 comprises four mixing paths. However, it is clear that any lower or higher number of mixing paths can be used. Although, having mixer circuitry 11 that comprises an even number of mixing paths does provide at least two mixing paths which are out of phase during a given clock phase.

[0041] In this embodiment, the mixer circuitry 11 comprises a plurality of switched capacitors C.sub.R1, C.sub.R2, C.sub.R3, C.sub.R4, C.sub.R5, C.sub.R6, C.sub.R7, C.sub.R8 that comprise a respective signal side node 45.sub.1, 45.sub.2, 45.sub.3, 45.sub.4, 45.sub.5, 45.sub.6, 45.sub.7, 45.sub.8 and a respective switch side node 47.sub.1, 47.sub.2, 47.sub.3, 47.sub.4, 47.sub.5, 47.sub.6, 47.sub.7, 47.sub.8. Each of the signal side nodes 45.sub.1-45.sub.8 is connected to corresponding signal lines 41, 43 that comprise the positive partial signal and the negative partial signal RF+, RF−. Particularly, the signal side nodes 45.sub.1-45.sub.4 are connected to the signal line 41 that transports the positive partial signal RF+ and the signal side nodes 45.sub.5-45.sub.8 are connected to the signal line 43 that transports the negative partial signal RF−.

[0042] In this embodiment, each pair of the switched side nodes 47.sub.1-47.sub.8 is differentially connected to each other through a respective switch M.sub.1, M.sub.2, M.sub.3, M.sub.4. Particularly, node 47.sub.1 is differentially connected to node 47.sub.5 through the switch M.sub.1, node 47.sub.2 is differentially connected to node 47.sub.6 through the switch M.sub.2, node 47.sub.3 is differentially connected to node 47.sub.7 through the switch M.sub.3, and node 47.sub.4 is differentially connected to node 47.sub.8 through the switch M.sub.4. Hence, the total number of switched capacitors C.sub.R1-C.sub.R8 depends on the number of mixing paths as well as on the differential configuration of the mixer circuitry 11.

[0043] The mixer circuitry 11 further comprises grounded capacitors C.sub.B1, C.sub.B2, C.sub.B3, C.sub.B4, which correspond to each of the differential in-phase and quadrature baseband signal components. The grounded capacitors C.sub.B1-C.sub.B4 are alternatively connected to each switch side node 47.sub.1-47.sub.8 through read-out switches 49.sub.1, 49.sub.2, 49.sub.3, 49.sub.4, 49.sub.5, 49.sub.6, 49.sub.7, 49.sub.8. To facilitate a clear understanding of the operation, the grounded capacitors C.sub.B1-C.sub.B4 along with the read-out switches 49.sub.1-49.sub.8 are drawn separately, where similar node references are maintained to translate an electrical connection. The read-out switches 49.sub.1-49.sub.8 are switched with respect to the clock phases, and the corresponding differential baseband component is stored in the respective grounded capacitor C.sub.B1-C.sub.B4. For example, the grounded capacitor C.sub.B1 is used to read out the baseband signal component at the switch side node 47.sub.7 of the switched capacitor C.sub.R7 through the read-out switch 49.sub.7 during the clock phase Φ.sub.1. The same grounded capacitor C.sub.B1 is re-used to read out the baseband signal component at the switch side node 4′71 of the switched capacitor C.sub.R1 through the read-out switch 49.sub.1 during the clock phase Φ.sub.3.

[0044] The mixer circuitry 11 further comprises bias switches 481, 482, 483, 484, 485, 486, 487, 488 to periodically set a common-mode bias voltage Vc of the mixer circuitry 11 and the plurality of read-out switches 49.sub.1-49.sub.8 through an external supply that is not shown in FIG. 4.

[0045] Referring to FIG. 5a and FIG. 5b, the baseband signal component read-out technique in a single-ended configuration is illustrated in greater detail. A four-path single-ended mixer with a bottom plate configuration is shown where the input radio frequency signal RF is down-converted to baseband signal components by clocks Φ.sub.0, Φ.sub.90, Φ.sub.180, and Φ.sub.270 operating at phases 0, 90, 180, and 270 degrees on the switches M.sub.1, M.sub.2, M.sub.3, and M.sub.4 respectively. It is assumed that the down-converted baseband voltages across the switched capacitors C.sub.R1-C.sub.R4 are V.sub.R0, V.sub.R90, V.sub.R180, and V.sub.R270, respectively.

[0046] In FIG. 5a, read-out of the baseband voltage is performed at the clock phase Φ.sub.0. The baseband voltages V.sub.R0 and V.sub.R180 are in anti-phase since the clock phases Φ.sub.0 and Φ.sub.180 that are driving their corresponding switches M.sub.1 and M.sub.3 are 180 degrees phase-shifted. Therefore, the in-band instantaneous voltages can be expressed as:

V.sub.R0=−V.sub.R180

[0047] When switch M.sub.1 is conducting, the bottom-plate of the capacitor C.sub.R1 is connected to ground, and the other capacitors C.sub.R2, C.sub.R3, C.sub.R4 remain floating. When sensing from node A, the capacitors C.sub.R3 and C.sub.R1 are connected in series to ground. Therefore, the resultant voltage at node A is:

V.sub.A=−V.sub.R180+V.sub.R0=2×V.sub.R0

[0048] As a result, a voltage gain of two is achieved for baseband signals by simply sensing the voltage from the node A.

[0049] In FIG. 5b, read-out of the baseband voltage is performed at the clock phase Φ.sub.90. The baseband voltages V.sub.R90 and V.sub.R270 are in anti-phase since the clock phases Φ.sub.90 and Φ.sub.270 that are driving their corresponding switches M.sub.2 and M.sub.4 are 180 degrees phase-shifted. Therefore, the in-band instantaneous voltages can be expressed as:

V.sub.R90=−V.sub.R270

[0050] When switch M.sub.2 is conducting, the bottom-plate of the capacitor C.sub.R2 is connected to ground, and the other capacitors C.sub.R1, C.sub.R3, C.sub.R4 remain floating. When sensing from node B, the capacitors C.sub.R2 and C.sub.R4 are connected in series to ground. Therefore, the resultant voltage at node B is:

V.sub.B=−V.sub.R270+V.sub.R90=2×V.sub.R90

[0051] As a result, a voltage gain of two is achieved for baseband signals by simply sensing the voltage from the node B.

[0052] Referring to FIG. 6a and FIG. 6b, the baseband signal component read-out technique in a fully differential configuration is illustrated in greater detail. A four-path fully differential mixer with bottom plate configuration is shown where the balanced radio frequency input signals RF+, RF− are down-converted to baseband signal components by clocks Φ.sub.0, Φ.sub.90, Φ.sub.180, and Φ.sub.270 operating at phases 0, 90, 180, and 270 degrees on the switches M.sub.1, M.sub.2, M.sub.3, and M.sub.4 respectively. The balanced differential inputs RF+, RF− result in a zero voltage point that occurs in the middle of the inversion region in the channel when a switch M.sub.1-M.sub.4 is closed. It is assumed that the down-converted baseband voltage across the switched capacitors C.sub.R1-C.sub.R4 is V.sub.R0, V.sub.R90, V.sub.R180, and V.sub.R270, respectively. Likewise, the down-converted baseband voltages across the switched capacitors C.sub.R5-C.sub.R8 are assumed to be −V.sub.R0, −V.sub.R90, −V.sub.R180, and −V.sub.R270, respectively.

[0053] In FIG. 6a, read-out of the baseband voltage is performed at the clock phase Φ.sub.0. The baseband voltages V.sub.R0 and V.sub.R180 are in anti-phase since the clock phases Φ.sub.0 and Φ.sub.180 that are driving their corresponding switches M.sub.1 and M.sub.3 are 180 degrees phase-shifted. When M.sub.1 is conducting, the positive portion of the baseband signal components can be sensed at the bottom-plate of the switched capacitor C.sub.R3, and the negative portion of the baseband signal component can be sensed at the bottom-plate of the switched capacitor C.sub.R7. Since the zero voltage point behaves similar to ground in the single-ended configuration, the resulting positive baseband signal component V.sub.B+ as well as the resulting negative baseband signal component V.sub.B− correspond to a double voltage gain of the respective positive and negative baseband signal components, as shown in FIG. 5a. The additional read-out capacitors C.sub.B1 and C.sub.B2 are used to read out the respective baseband signal components V.sub.B+, V.sub.B−.

[0054] In FIG. 6b, the additional read-out capacitors C.sub.B1, C.sub.B2 are re-used at the clock phase Φ.sub.180. When M.sub.3 is conducting, the positive portion of the baseband signal components can be sensed at the bottom-plate of the switched capacitor C.sub.R5, and the negative portion of the baseband signal component can be sensed at the bottom-plate of the switched capacitor C.sub.R1. Since the input signal is fully differential and 180-degree phase shifted clocks are driving the switches M.sub.1 and M.sub.3, the read-out capacitors C.sub.B1, C.sub.B2 are effectively re-used to read-out the respective baseband signal components V.sub.B+, V.sub.B−. Furthermore, an additional order of infinite impulse response filtering is achieved in this technique since the read-out capacitors C.sub.B1, C.sub.B2 share the charges with two switched capacitors C.sub.R1, C.sub.R3 resp. C.sub.R5, C.sub.R7 at different time instants.

[0055] FIG. 7 illustrates a second example embodiment of the mixer circuitry 21 according to the first aspect. The second example embodiment of the mixer circuitry 21 differs from the first example embodiment of the mixer circuitry 11 according to FIG. 4 in that the grounded capacitors C.sub.B1, C.sub.B2, C.sub.B3, C.sub.B4, C.sub.B5, C.sub.B6, C.sub.B7, C.sub.B8 are not re-used and each of the grounded capacitors C.sub.B1-C.sub.B8 is dedicated to a corresponding switch side node 47.sub.1-47.sub.8 through the plurality of read-out switches 49.sub.1-49.sub.8. Such a configuration of reading out the baseband signal components through dedicated grounded capacitors C.sub.B1-C.sub.B8 facilitates direct digital conversion of the baseband signal components.

[0056] FIG. 8 illustrates a flow chart of an example embodiment of the method according to the second aspect. In a first step S1, each of a plurality of switched capacitors is connected to the signal line through a signal side node. In a second step S2, each of the plurality of switched capacitors is connected to a corresponding switch through a switch side node. In a third step S3, a voltage at each switch side node of the plurality of switched capacitors is sensed and is read out through a respective grounded capacitor.

[0057] While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.