The present invention relates to a power management system (PMS) for multiple energy storage systems (ESS) that is for integrated management of the system having multiple ESS for controlling a frequency and having a hierarchical control structure. The PMS for ESS comprises: a plurality of ESS; a local management system (LMS) for managing one or more ESS of the plurality of ESS for each local unit; an ESS Controller (ESSC) for general management of the LMS, judging a state of the LMS and determining an output value of one or more ESS in the LMS, and transmitting the determined output value to the respective ESS; and a PMS for general management of the entire system comprising the plurality of ESS, the LMS and the ESSC, judging the state of the entire system and participating in a power grid frequency control market through a grid operator contract, controlling the output of the LMS, and adjusting a control parameter for output control.

Tunable filters, cancellers, and duplexers based on passive mixers. A tunable delay cell includes passive mixers electrically coupled together for receiving an input signal and outputting a delayed signal, each passive mixer comprising a plurality of mixer switches. The tunable delay includes a control circuit for providing, to each passive mixer, a respective plurality of local oscillator (LO) signals, one to each mixer switch of each passive mixer. The control circuit is configured to vary the LO signals to cause a target frequency band of the input signal to be delayed by a target delay time in propagating through the passive mixers.

The present disclosure provides a hetero-integrated terahertz low-noise miniaturized image frequency rejection transceiver front-end, including an intermediate frequency circuit and a terahertz circuit arranged up and down, where the terahertz circuit includes a local oscillator frequency tripler, a 135° 3 dB filter coupler, a radio frequency waveguide power divider, and two quartz hetero-integrated subharmonic mixers; resonant cavities of an input unit, a first output unit, an isolation unit, and a second output unit of the 135° 3 dB filter coupler are sequentially coupled through resonant grooves to form a ring structure, a cavity length of the resonant cavity of the input unit is twice that of the resonant cavities of the other three units, and an electrical length of a waveguide of the first output unit is 45° different from that of a waveguide of the second output unit.

The present disclosure provides a GaAs monolithic integrated terahertz low-noise communication system transceiver front-end, including an intermediate frequency circuit and a terahertz circuit. The terahertz circuit includes a local oscillator frequency tripler, a local oscillator unidirectional 3 dB filter coupler, a radio frequency 180° filter coupler, and two terahertz GaAs monolithic integrated subharmonic mixers. The local oscillator unidirectional 3 dB filter coupler and the radio frequency 180° filter coupler each include one ring-cylindrical resonant cavity and four rectangular waveguides. The ring-cylindrical resonant cavity is divided into four rectangular waveguides which are correspondingly connected to the four sector-annular resonant cavities, respectively. The present disclosure suppresses the local oscillator noise by adopting a local oscillator unidirectional 3 dB filter coupler and a radio frequency 180° filter coupler with both coupling and filtering functions, thereby achieving a low local oscillator noise transceiver front-end.

An electronic device may include a harmonic rejection mixer with a delay line, mixer array, and load. The delay line may generate LO phases. Each mixer in the array may have a first input that receives an LO phase and a second input coupled to an input switch and the first input of the next mixer circuit through an inter-mixer switch. The load may include a set of switches. In a transmit mode, the input switches and set of switches may be closed while the inter-mixer switches are open. In a self-calibration mode, the input switches and set of switches may be open while the inter-mixer switches are closed. A controller may sweep through phase codes for the programmable delay line while storing a digital output from the load. The controller may calibrate the phase code based on the digital output.

The present disclosure provides a mixing circuit with high harmonic suppression ratio, including: a multi-phase generation module, which receives a first input signal and generates eight first square wave signals with a phase difference of 45°; a quadrature phase generation module, which receives a second input signal and generates four second square wave signals with a phase difference of 90°; a harmonic suppression module, connected with an output end of the quadrature phase generation module to filter out higher order harmonic components in the second square wave signals; and a mixing module, connected with output ends of the multi-phase generation module and the harmonic suppression module to mix output signals of the multi-phase generation module and the harmonic suppression module. The mixing circuit with high harmonic suppression ratio adds a harmonic suppression module on the basis of multi-phase mixing, thereby improving the harmonic suppression ratio of the output signal.

The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.

A digital down converter (DDC) that improves efficiency by taking advantage of the periodicity of the coarse mixing process and the memory inherent in the convolution operation performed by decimation filters. In embodiments, the DDC filters and decimates a received signal to generate subfilter outputs and coarse mixes the subfilter outputs for each frequency band of interest. Accordingly, the DDC eliminates the need for separate decimation filters for each of the in-phase (I-phase) and quadrature (Q-phase) signals of each frequency band. In some embodiments, for each frequency band, the DDC combines the subfilter outputs into partial sums for each of the I- and Q-phases. In some of those embodiments, the coarse mixing operation is performed by multiplying the partial sums by real multiplicands and performing a simple post-rotation operation. In those embodiments, the DDC significantly reduces the number of multiplication operations required to perform the coarse mixing process.

A radio frequency (RF) transmission circuit includes an input stage, a current-mode mixer coupled to an output of the input stage, an attenuator coupled to an output of the current-mode mixer, and a matching network coupled to an output of the attenuator. The input stage, current-mode mixer, attenuator, and the matching network are configured in a series stack.

A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.