Circuit carrier, package, and method for manufacturing a package

Abstract

A circuit carrier includes a first side, two layers arranged to define an intermediate space there between, with at least one of the two layers being electrically conductive and attached to the first side. The at least one of the two layers has a region deformed such as to exhibit an indentation and has a trace structure in the indentation. A first insulating material fills the intermediate space, and a second insulating material fills the indentation, A second side in opposition to the first side is shaped to have in the deformed region a cut-out for receiving a bare die such as to come into an electrical contact with the at least one of the two layers.

Claims

1. A method for manufacturing a circuit carrier, said method comprising: arranging an electrically conductive first layer on a first side of a board at a distance to a second layer to define an intermediate space there between; filling the intermediate space with a first insulating material; curing the board such as to deform a region of the board in such a way that the electrically conductive first layer has an indentation in the deformed region; forming a cutout on a second side of the board in opposition to the first side such that the indentation and the cut-out lie opposite one another; structuring the electrically conductive first layer to produce a trace structure; populating a bare die in the cut-out such as to come into electrical contact with the electrically conductive first layer; and filling the indentation with a second insulating material.

2. The method of claim 1, wherein the trace structure is produced in the indentation.

3. The method of claim 1, wherein the bare die is brought into the electrical contact with the trace structure of the electrically conductive first layer.

4. The method of claim 1, wherein the board is cured and the region deformed by lamination.

5. The method of claim 1, wherein the cutout is formed by deep milling or punching out.

6. The method of claim 1, wherein the cut-out is formed by deep milling or punching out up to the electrically conductive first layer.

7. A method for manufacturing a package, said method comprising: arranging an electrically conductive first layer on a first side of a board at a distance to a second layer to define an intermediate space there between; filling the intermediate space with a first insulating material; curing the board such as to deform a region of the board in such a way that the electrically conductive first layer has an indentation in the deformed region; forming a cut-out on a second side of the board in opposition to the first side such that the indentation and the cut-out lie opposite one another; populating a bare die in the cut-out such as to come into electrical contact with the electrically conductive first layer; structuring the electrically conductive first layer to produce a trace structure; and filling the indentation with a second insulating material.

8. The method of claim 7, wherein after the cut-out is formed in the board and the bare die is then populated in the cut-out to produce a populated board, the populated board is cured and deformed during the curing to produce the deformed region with the indentation at a point which lies opposite the cut-out.

9. The method of claim 7, wherein the trace structure is arranged at least in the indentation.

10. The method of claim 7, wherein the trace structure of the electrically conductive first layer is arranged in electrical contact with the bare die.

11. The method of claim 8, wherein the cut-out in the board is formed by punching out.

12. The method of claim 8, wherein the curing and deforming realized by lamination.

13. The method of claim 8, wherein, during the deforming, the bare die is insulated with the first insulating material.

14. The method of claim 7, wherein first the board is cured and deformed during the curing to produce the deformed region with the indentation, then the cut-out is formed at the second side of the board at a point which lies opposite the indentation, and then the bare die is populated in the cut-out, so that the bare die is in electrical contact with the electrically conductive first layer.

15. The method of claim 14, wherein the curing and deforming realized by lamination.

16. The method of claim 14, wherein the cut-out in the board is formed by deep-milling.

Description

BRIEF DESCRIPTION OF THE DRAWING

(1) Other features and advantages of the present invention will be more readily apparent upon reading the following description of currently preferred exemplified embodiments of the invention with reference to the accompanying drawing, in which:

(2) FIG. 1 shows a top perspective view of one embodiment of a circuit carrier according to the present invention;

(3) FIG. 2 shows a sectional representation of a top perspective view of the circuit carrier of FIG. 1;

(4) FIG. 3 shows a bottom perspective view of the circuit carrier of FIG. 1;

(5) FIG. 4 shows a sectional representation of the circuit carrier of FIG. 3;

(6) FIG. 5 shows a cross-sectional view of the circuit carrier of FIG. 3;

(7) FIG. 6 shows a cross-sectional view of another embodiment of a circuit carrier according to the present invention;

(8) FIG. 7 shows a perspective view of a board with a first insulating material in a raw state;

(9) FIG. 8 shows a perspective view of a deformed board with the cured first insulating material;

(10) FIG. 9 shows a sectional representation of the board of FIG. 8;

(11) FIG. 10 shows a cross-sectional view of the board of FIG. 8;

(12) FIG. 11 shows a perspective view of the board of FIG. 8 with a trace structure;

(13) FIG. 12 shows a sectional representation of the board of FIG. 11;

(14) FIG. 13 shows a perspective view of the board of FIG. 11 with an indentation filled in with a second insulating material;

(15) FIG. 14 shows a sectional representation of the board of FIG. 13;

(16) FIG. 15 shows a sectional representation of the board of FIG. 13;

(17) FIG. 16 shows a perspective view of the board from FIG. 13 with a cut-out on a rear side of the circuit carrier;

(18) FIG. 17 shows a sectional representation of the circuit carrier of FIG. 16;

(19) FIG. 18 shows a cross-sectional view of the circuit carrier of FIG. 16;

(20) FIG. 19 shows a sectional representation of a package according to the present invention with a circuit carrier according to the present invention and with an insulating bare die;

(21) FIG. 20 shows a cross-sectional view of the package of FIG. 19;

(22) FIG. 21 shows a cross-sectional view of a package according to the present invention with the circuit carrier of FIG. 6 and with a bare die;

(23) FIG. 22 shows a cross-sectional view of a package according to the present invention with an additional circuit carrier;

(24) FIG. 23 shows a cross-sectional view of a modified package according to the present invention;

(25) FIG. 24 shows a bottom perspective view of a circuit carrier according to the present invention to be populated;

(26) FIG. 25 shows a sectional representation of the circuit carrier of AG. 24;

(27) FIG. 26 shows a cross-sectional view of the circuit carrier of FIG. 24 with a bare die ready for population;

(28) FIG. 27 shows a package according to the present invention with the circuit carrier of FIG. 24 populated with a non-insulated bare die;

(29) FIG. 28 shows a sectional representation of the package of FIG. 27;

(30) FIG. 29 shows a cross-sectional view of the package of FIG. 27;

(31) FIG. 30 shows a perspective view of the package of FIG. 27 with an insulated bare die;

(32) FIG. 31 shows a sectional representation of the package of PG. 30;

(33) FIG. 32 shows a cross-sectional view of the package of FIG. 30;

(34) FIG. 33 shows a perspective view of a circuit carrier module with a plurality of circuit carriers according to the present invention, and

(35) FIG. 34 shows a cross-sectional view of a package populated on a printed circuit board.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(36) Throughout all the figures, same or corresponding elements may generally be indicated by same reference numerals. These depicted embodiments are to be understood as illustrative of the invention and not as limiting in any way. It should also be understood that the figures are not necessarily to scale and that the embodiments may be illustrated by graphic symbols, phantom lines, diagrammatic representations and fragmentary views. In certain instances, details which are not necessary for an understanding of the present invention or which render other details difficult to perceive may have been omitted.

(37) Turning now to the drawing, and in particular to FIGS. 1 to 6, with FIGS. 1 to 5 showing various views of a first embodiment of a circuit carrier according to the present invention, generally designated by reference numeral 1, and with FIG. 6 showing a cross-sectional view of a second embodiment of a circuit carrier according to the present invention, generally designated by reference numeral 100. The description below relates to both embodiments of the circuit carrier. Specific reference is made to the differences between the embodiments. The circuit carrier 1, 100 has two layers 2, 3, wherein at least one of the two layers 2 of the circuit carrier 1, 100 is made of an at least electrically conductive material. This material is preferably copper. It is likewise conceivable to use other electrically conductive materials, e.g. metals, such as aluminum, or alloys. The at least electrically conductive layer 2 is attached to a first side 7 of the circuit carrier 1, 100.

(38) An intermediate space 4 is defined between the layers 2, 3. In this context, the second layer 3 may also be made of a dielectric, e.g. be embodied from the first insulating material. Advantageously, however, at least electrically conductive layers 2 and 3, for example copper layers, are used.

(39) The intermediate space 4 is filled with a first insulating material 5 (see FIGS. 5 and 6), which forms what is known as the core. The first insulating material 5 is generally a dielectric material (a dielectric), which both lends the circuit carrier 1, 100 robustness and rigidity and, in its preliminary stage or in the raw state (not yet crosslinked or cured) can be deformed, at least in a thermoplastic manner. The first insulating material 5 may for example involve a thermoplastic, such as polyamide for example, or a thermosetting plastic, such as epoxy resin for example. In this context, a particularly advantageous material is a prepreg material, for example a glass-fiber reinforced prepreg material, in particular a glass-fiber reinforced laminate. At this point, it should be noted that many other materials may be used as the core for the circuit carrier 1, 100, provided they have a thermoplastic preliminary stage and can be cured after the shaping by means of heating, irradiation or by chemical reaction (for example by supplying heat) of at least two reactants.

(40) Additionally, the circuit carrier 1, 100 has at least one region 6, 600 deformed in this way such that the electrically conductive layer 2 of the circuit carrier 1, 100 has an indentation 8 in the deformed region 6, 600. When viewed from above (e.g. FIG. 1 or FIG. 2), the indentation 8 may extend over the entire upper side 7 of the deformed region 6, 600. The shape of the indentation 8 may approximately correspond to the shape of a notch, which for example is rectangular and in particular is square. For example, as shown, it may have the shape of a trough with a trapezoid-shaped cross-section (FIG. 2). At this point, it should be noted that the deformed region does not only comprise the first (upper) side 7, but also the core 5 and preferably a second side 11 (the rear side) of the circuit carrier 1. The deformed region 6, 600 may have a spatial extent D and a depth h (see FIG. 10). The extent D may amount to approximately 0.5 to 5 cm, in particular 1.5 cm. For example, in a deformed region which is square-shaped when viewed from above (not shown), the extent D may be the same in both horizontal directions and may amount to 1.5 cm×1.5 cm for example. In preferred embodiments, the depth h may amount to approximately 200 to 300 micrometers. The flanks of the deformed regions 6, 600 i.e. the transitions between a non-deformed region of the electrically conductive layer 2 and the base of the indentation 8—descend towards the indentation base and may have an incline of approximately 20 to 30 degrees. It is indeed possible to implement a different incline angle α of the flank in relation to the non-deformed region of the electrically conductive layer 2, In the case of an angle which is too steep, e.g. 90 degrees, however, there would be the risk of a tear in the layer or film.

(41) In this context, the second side 11 opposite the first side 7 (the rear side) of the circuit carrier 1 according to the first embodiment has an elevation 14 corresponding to, preferably congruent to the indentation 8. The second side 110 of the circuit carrier 100 is embodied in a flat manner according to the second embodiment.

(42) The first side 7 of the circuit carrier 1, 100 is structured at least in the indentation 8 and has a trace structure 9. The trace structure 9 is advantageously formed in the base of the indentation 8. The trace structure 9 may, for example, be generated by means of etching technology/subtractive methods or also by means of a laser, for example by means of a laser direct structuring. In FIGS. 3 to 5, it is particularly easy to identify that a through groove, i.e. in this context a groove passing through the second layer 2, can be introduced into the second layer 2 here. Depending on the application, the trace structure 9 may have various shapes. In the example shown, the through groove has the shape of a wave, for example a sinusoidal wave. The trace structure 9 advantageously corresponds to a mating contour (contour of the contact area) on a semiconductor die, with which the circuit carrier 1, 100 is to be populated and has the corresponding contacting points. The geometry of the trace structure generally depends upon the geometric contact areas of the terminals of the semiconductor die to be populated.

(43) The indentation 8 is filled in with a second insulating material 10, Preferably, only the indentation 8 is filled in, so that there is no second insulating material 10 beyond the edges of the indentation 8 (see e.g. FIGS. 1 to 6). The application of the second insulating material 10 may already be possible at a room temperature (approx. 25° C.). It is also conceivable for the second insulating material 10 to be heated up and applied by way of dispensing, jetting or doctor blading. This depends upon the specific material selection.

(44) The second insulating material 10 advantageously likewise involves a dielectric. Chemically curing materials, for example curable polymers with a liquid preliminary stage, in particular one or two-part epoxy resins, are particularly preferred here. It is also conceivable for physically bonding or thermoplastic substances to be used as the second insulating material 10. A prepreg material (prefabricated semi-finished part) may likewise function as second insulating material 10.

(45) In the deformed region 6, 600, the second side 11, 110 (the rear side) of the circuit carrier 1, 100 has a cut-out 12 shaped in such a way that it is possible to populate a bare die 13 in the cut-out 12 and, in the process, bring said bare the 13 into electrical contact with the at least electrically conductive layer 2 attached to the first side 7 of the circuit carrier 1, 100 (see e.g. FIG. 5). In this context, the bare die 13 may be received in the cut-out 12 in such a way that an air gap remains between the bare die 13 and walls of the cut-out.

(46) It is understood that the circuit carrier 1, 100 may have a plurality of deformed regions 6, 600 and cut-outs 12 embodied as mentioned above and thus may be populated with a plurality of bare dies (see FIG. 33). In this context, one electronic component may be populated in each cut-out. It is possible to populate different kinds of electronic components in different cut-outs, such as lateral, e.g. Gall, or transverse, e.g. IGBT, components for example. In this case (FIG. 33), it may be expedient if the circuit carriers 1, 100 are connected to a half bridge in pairs.

(47) The second layer 3 may be embodied from an at least thermally conductive material. It is conceivable for the second layer to be embodied from the same material as the core of the circuit carrier 1, 100, i.e. from the first insulating material 5. Preferably, materials which are able to conduct both heat and current, so that it is both possible for the circuit carrier 1, 100 to be brought into (electrical) contact on both sides and also for the heat to be efficiently dissipated by way of the second layer 3. Metals, and in particular copper, lend themselves as such materials.

(48) It is furthermore apparent from FIGS. 1 to 5 that the cut-out 12 may be formed in the elevation 14. In general, the cut-out is formed at the point of the rear side 11, 110 of the circuit carrier 1, 100 which lies opposite the indentation 8.

(49) In FIGS. 3 to 6, it is particularly easy to identify that the cut-out 12 may be formed in such a deep manner that its base 15 is at least partially formed by the layer 2 which is made of the at least electrically conductive material and attached to the first side 7 of the circuit carrier 1, 100. This enables a particularly favorable bonding of the bare die 13 to the circuit carrier 1, 100.

(50) FIGS. 7 to 18 show intermediate products, which are produced after respective steps of a method, which for example may be used to manufacture the circuit carrier of FIGS. 1 to 5 described above.

(51) The method comprises the following steps. In one step, a board is provided which e.g. is not yet laminated, wherein the board comprises two layers 2, 3 and at least one of the two layers 2, 3 of the board is made of the aforementioned at least electrically conductive material, such as copper for example. This electrically conductive layer 2 is arranged on a first side 7 of the board. Defined between the layers 2, 3 is the intermediate space 4, which is completely filled with the first insulating material 5. Boards of this kind are often referred to as base material. In this context, the first insulating material 5 is in its preliminary stage—material in the raw state. For example, the first insulating material 5 may have been applied to the first layer 2 in the form of a paste, A board of this kind is shown in FIG. 7, wherein it should be noted that the second layer 3 in principle may consist of the first insulating material 5. The (second) layer 3 may also be embodied from an electrically conductive material, e.g. from copper.

(52) In another step (step A), the board is cured and in the process at least one region 6 of the board is deformed in such a way that the at least electrically conductive layer 2 has an indentation 8 in the deformed region 6 (FIGS. 8 to 10). This may take place by way of lamination. In this context, the at least one region 6 of the circuit carrier 1 may be deformed in such a way that the second side 11 of the circuit carrier 1 (the rear side) has an elevation 14 in the deformed region 6. For example, the desired regions of the board may already be deformed during the lamination of the base material made of two layers 2, 3 (e.g. made of copper) and the first insulating material 5 (e.g. prepreg material).

(53) In another step (step B) the cut-out 12 is formed on the second side 11 of the board opposite the first side 7 (on the rear side).

(54) The temporal order of steps A and B can be chosen freely and, as already explained in the introduction to the description, substantially depends upon which material is used as the first insulating material. For example, the order B-A may be more suitable for glass-reinforced prepregs than the order A-B. In turn, the order A-B may be more suitable if the first insulating material 5 has the form of a viscous paste in the raw state.

(55) Regardless of the order of steps A and B, the indentation 8 and the cut-out 12 are generated in the deformed region 6, 600 in such a way that they lie opposite one another and at least one electronic component, e.g. a bare die 13, can be populated in the cut-out 12 and brought into electrical contact with the at least electrically conductive layer 2 attached to the first side 7 of the circuit carrier 1—i.e. with the base of the indentation 8.

(56) If the second side 11 has the aforementioned elevation 14, then the cut-out 12 is formed in the elevation 14, In this context, it may be expedient if the cut-out 12 is deep up to the layer 2 which is made of the at least electrically conductive material and attached to the first side 7 of the circuit carrier 1, so that for example bond pads (electrical terminals) 17 of the bare die 13 can be directly set onto the electrically conductive material of the at least one layer 2.

(57) The generation of the cut-out 12 may for example take place by way of deep milling, in particular in the sequence A-B, or by punching out, in particular in the sequence B-A.

(58) In order to obtain a trace structure 9, in one step of the method at least part of the at least electrically conductive layer 2 is structured. This working step may take place immediately after step A, whereby an intermediate product shown in FIGS. 11 and 12 may be obtained. In this case, the electrically conductive layer 2 is structured in the already present deformed region 6, specifically advantageously in a base of the indentation 8. Etching technology may be used in this context, for example.

(59) It is also conceivable, however, for the structuring of the electrically conductive layer to still take place before step A and/or B. In such a case, the indentation 8 or the cut-out 12 is formed in the region of the board where the trace structure 9 is already present (the cut-out 12 is formed on a side of the board opposite the trace structure 9).

(60) In another step, the indentation 8 may be filled in with the second insulating material 10, advantageously up to its edges. As a result, voltage flashovers between individual traces of the trace structure 9 may be avoided and leakage currents may be reduced.

(61) FIGS. 19 to 21 show packages which for example may be obtained with the aid of the circuit carriers 1, 100 described above. One such package 1000, 1001 for example comprises the circuit carrier 1 or 100 and at least one bare die 13, which is populated on the circuit carrier 1, 100.

(62) The bare die 13 is thus arranged in the cut-out 12 and is electrically connected to the at least electrically conductive layer 2. To this end, the bare die 13 for example may have a plurality of the aforementioned electrical terminals 17, which are in contact with traces of the trace structure 9.

(63) If necessary, the bare die 13 may be insulated by an optionally present air gap between the bare die 13 and both the walls and the part of the base of the cut-out 12, with which the bare die 13 is not in contact, being at least partially filled with a third insulating material 16. As a result, for example, the different terminals 17 (the bond pads) of the bare die 13 may be electrically insulated from one another. The third insulating material 16—a dielectric—is advantageously chosen from the same group of substances from which the first and the second insulating material are chosen. It is conceivable for all three insulation materials to be different or the same. It is also conceivable for only the second insulating material 10 to be the same as the third insulating material 16.

(64) As already explained, the bare die may be embodied as a lateral component, for example as a GaN component or a vertical component, for example as an IGBT component.

(65) Moreover, an additional circuit carrier 18 may be provided in the package 1000, 1001 (see FIGS. 22 and 23). This may be a ceramic circuit carrier, e.g. DCB (direct copper bonded) circuit carrier for example. The additional circuit carrier 18 may be attached to the side of the bare die 13 which lies opposite the first side 7 of the circuit carrier 1, 100 and—according to the examples shown in FIGS. 19 to 21—lies opposite the bond pads 17. The primary function of the additional circuit carrier 18 may be the thermal heat dissipation of the package 1000, 1001 for example. Moreover, the additional circuit carrier 18 may be used for the thermal insulation of the bare die 13. This makes it possible to obtain a package 1000 which can be brought into contact on one side, as can be seen in FIG. 22.

(66) If the second layer 3 is electrically conductive, then the additional circuit carrier 18 may be electrically connected to the second layer 3 (for example by means of a pad 19 or bump or the like). In this case, the additional circuit carrier 18 dissipates the heat from the package 1000 and simultaneously ensures that the package 1000 can be brought into (electrical) contact on both sides (see FIG. 23).

(67) Additionally, the layers 2 and 3 may be electrically connected (by way of a via through the insulating material 5). This is then particularly advantageous if a potential of a top-side pad is to be applied to the rear-side pad of the semiconductor die. Primarily in lateral components (GaN), it may be expedient if the source potential is applied to said pad, in order to reduce capacitive charge reversal losses in the die during switching. This, however, depends upon the semiconductor architecture/design and does not describe a generally applicable rule.

(68) The package 1000, 1001 may be embodied as a surface-mounted component or as an SMD (surface-mounted device). FIG. 34 shows by way of example a printed circuit board populated with the package 1000. In this case, the package 1000 may be populated on a printed circuit board in a particularly simple manner, for example by means of further terminals 20 arranged on the at least one layer 2.

(69) In FIGS. 24 to 32, intermediate products of individual method steps of an exemplary method for manufacturing the package 1000 (e.g. according to FIG. 20) are shown. A circuit carrier 1, 100 and a bare die 13 can be assumed (see FIGS. 24 to 26). In this context, the circuit carrier 1, 100 may be obtained by the aforementioned circuit carrier manufacturing method for example. Subsequently, the bare die 13 may be populated in the cut-out 12 in such a way that the one bare die 13 is in electrical contact with the at least electrically conductive layer 2. Following this, the cut-out 12 may be at least partially filled with the third insulating material 16, so that the aforementioned air gap (FIGS. 27 to 29) between the bare die 13 and the areas delimiting the cut-out 12 is filled and terminals 17 of the bare die 13 can be insulated from one another (FIGS. 30 to 32).

(70) Not shown in the Figures is the already explained preferred form of the package manufacturing method, in which the board in the raw state and an electronic component, e.g. a bare die, can be assumed. As already described, in this embodiment, first the cut-out can be formed, advantageously punched out, in the board provided. Following this, the bare die can be populated (and contacted) in the cut-out carved out of the semi-finished part made of the first insulating material, in order to obtain a populated board. Subsequently, the populated board can be cured and deformed in the process, advantageously by lamination, in order to obtain the at least one deformed region, in which the at least electrically conductive layer has the indentation at the point which lies opposite the indentation. In this context, during the curing and deforming, for example during the lamination using pressure and temperature, the heated first insulating material can flow into the intermediate spaces between the bare die and the at least electrically conductive layer and at least partially enclose and insulate the bare die. It is thus possible to dispense with the further insulation with a further insulating material (e.g. with a third insulating material). In this manner, the package 1001 from FIG. 21 can be generated for example.

(71) FIG. 33 shows a circuit carrier 1, 100 with a plurality of deformed regions 6, 600. Circuit carriers 1, 100 of this kind enable module/cluster-like structures. The circuit carriers 1, 100 are connected to a half bridge in pairs.

(72) It can be seen that alterations and/or additions of parts to the previously described circuit carrier, the package or manufacturing methods thereof may take place without deviating from the field and scope of the present invention. Likewise, it can be seen that although the invention has been described in relation to specific examples, a person skilled in the art would certainly be in a position to obtain many other corresponding forms of a circuit carrier, a package or manufacturing methods thereof, which have the properties presented in the claims and thus all fall within the protective scope specified thereby.

(73) In summary, the invention relates to circuit carriers 1, 100 for receiving a bare die, wherein the circuit carrier 1, 100 comprises two layers 2, 3, wherein at least one of the two layers 2 of the circuit carrier 1, 100 is at least electrically conductive and is attached to a first side 7 of the circuit carrier 1, 100, wherein the layers 2, 3 define an intermediate space 4, which is completely filled with a first insulating material 5, wherein the circuit carrier 1, 100 has at least one region 6, 600 deformed in such a way that the at least electrically conductive layer 2 of the circuit carrier 1, 100 has an indentation 8 in the deformed region 6, 600, wherein the at least electrically conductive layer 2 of the circuit carrier 1, 100 has a trace structure 9 at least in the indentation 8, wherein the indentation 8 is filled in with a second insulating material 10, wherein a second side 11, 110 of the circuit carrier 1, 100 opposite the first side 7 has a cut-out 12 in the deformed region 6, 600 which is shaped in such a way that a bare die 13 can be populated in the cut-out 12 and, in doing so, can be brought into electrical contact with the at least electrically conductive layer 2 which is attached to the first side 7 of the circuit carrier 1, 100.

(74) The reference characters in the claims merely serve to better understand the present invention and do not in any case signify a restriction of the present invention.

(75) While the invention has been illustrated and described in connection with currently preferred embodiments shown and described in detail, it is not intended to be limited to the details shown since various modifications and structural changes may be made without departing in any way from the spirit and scope of the present invention. The embodiments were chosen and described in order to explain the principles of the invention and practical application to thereby enable a person skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.