Signal Delay Device and Simulator Device for Simulating Spatial Distances in Distance Measuring Devices Based on Electromagnetic Waves

Abstract

A signal delay device includes a demultiplexer, D∈ delay means, D additional delay means, a multiplexer, and a control unit. For each delay means, a delay input and a demultiplexer output are connected, and a delay output and a multiplexer input are connected. For each additional delay means, an additional delay input is connected to a delay signal path, and an additional delay output and a multiplexer input are connected. The demultiplexer divides an input data word stream into parallel data word streams. Each delay means will delay the data words in the parallel data word streams. Each additional delay means will delay the data words in the delayed parallel data word stream by an additional delay time. The control unit controls the multiplexer such that an output data word stream corresponding to the input data word stream with a time delay is output.

Claims

1. A signal delay device for simulating spatial distances in distance measuring devices using electromagnetic waves, comprising: a demultiplexer; D∈ delay means; D additional delay means; a multiplexer; and a control unit; wherein the demultiplexer has a demultiplexer input and D demultiplexer outputs; wherein each of the D delay means has a delay input and a delay output; wherein each of the D additional delay means has an additional delay input and an additional delay output; wherein the multiplexer has 2.Math.D multiplexer inputs and a multiplexer output; wherein for each of the D delay means, on the one hand, the delay input and one of the D demultiplexer outputs are connected to one another via an input signal path and, on the other hand, the delay output and one of the 2.Math.D multiplexer inputs are connected to one another via a delay signal path; wherein, for each of the D additional delay means, on the one hand, the additional delay input is connected to one of the delay signal paths and, on the other hand, the additional delay output and one of the 2.Math.D multiplexer inputs are connected to one another via an additional delay signal path; wherein the demultiplexer is designed to divide an input data word stream having data words with an external transmission rate of S at the demultiplexer input into interleaved, parallel data word streams at an internal transmission rate of P=S/D in each case and to output these parallel data word streams at the D demultiplexer outputs; wherein each of the D delay means can be preset with a forwarding delay factor m∈.sub.0, and each of the D delay means is designed to delay each data word in the respective parallel data word stream at the delay input by a forwarding delay time Δt.sub.m=m/P and to output the delayed data word at the delay output; wherein each of the D additional delay means is designed to delay each data word in the respective delayed parallel data word stream at the additional delay input by an additional delay time of Δt.sub.z=1/P and to output the additionally delayed data word at the additional delay output; and wherein an output delay factor n∈.sub.0 can be preset to the control unit, the control unit is designed to determine the forwarding delay factor m from a predefined output delay factor n and to preset this to the D delay means and to control the multiplexer in such a manner that an output data word stream corresponding to the input data word stream with a time delay of Δt=n/S is output at the multiplexer output.

2. The signal delay device according to claim 1, wherein at least one of the delay means and/or one of the additional delay means is/are implemented in an FPGA.

3. The signal delay device according to claim 1, wherein the control unit is adapted to determine the forwarding delay factor according to m=└n/D┘.

4. The signal delay device according to claim 1, wherein at least one of the D additional delay means has a work cycle of f.sub.P=S/D.

5. The signal delay device according to claim 1, wherein at least one of the additional delay means is a delay line.

6. The signal delay device according to claim 1, wherein at least one of the additional delay means is a flip-flop.

7. The signal delay device for simulating spatial distances in distance measuring devices using electromagnetic waves, comprising: a demultiplexer; D∈ delay means; a multiplexer; and a control unit; wherein the demultiplexer has a demultiplexer input and D demultiplexer outputs; wherein each of the D delay means has a delay input and a delay output; wherein the multiplexer has D multiplexer inputs and a multiplexer output; wherein for each of the D delay means, on the one hand, the delay input and one of the D demultiplexer outputs are connected to one another via an input signal path and, on the other hand, the delay output and one of the D multiplexer inputs are connected to one another via a delay signal path; wherein the demultiplexer is designed to divide an input data word stream having data words with an external transmission rate of S at the demultiplexer input into interleaved, parallel data word streams at an internal transmission rate of P=S/D in each case and to output these parallel data word streams at the D demultiplexer outputs; wherein each of the D delay means can be preset with a separate forwarding delay factor m.sub.d∈.sub.0 with d∈≤D, and each of the D delay means is designed to delay each data word in the respective parallel data word stream at the delay input by a separate forwarding delay time Δt.sub.m,d=m.sub.d/P and to output the delayed data word at the delay output; and wherein an output delay factor n∈.sub.0 can be preset to the control unit, the control unit is designed to determine the forwarding delay factors m.sub.d from a predefined output delay factor n and to preset them to the D presettable delay means and to control the multiplexer in such a manner that an output data word stream corresponding to the input data word stream with a time delay of Δt=n/S is output at the multiplexer output.

8. The signal delay device according to claim 7, wherein at least one of the delay means is implemented in an FPGA.

9. The signal delay device according to claim 7, wherein the control unit is adapted to determine the separate forwarding delay factors according to m.sub.d└=(n+d−1)/D┘ for d∈≤D.

10. The signal delay device according to claim 1, wherein the external transmission rate is S≥2 GS/s.

11. The signal delay device according to claim 1, wherein D=2.

12. The signal delay device according to claim 1, wherein the demultiplexer and/or the multiplexer has/have a work cycle f.sub.S corresponding to the external transmission rate S.

13. The signal delay device according to claim 1, wherein at least one of the D delay means has a work cycle of f.sub.P=S/D.

14. The signal delay device according to claim 1, wherein at least one of the delay means is a delay line.

15. The signal delay device according to claim 1, wherein the signal delay device is designed to simulate distances in distance measuring devices using radar or lidar.

16. A simulator device for simulating spatial distances for distance measuring devices using electromagnetic waves, comprising: a receiver; an analog-to-digital converter; a signal delay device; a digital-to-analog converter; and a transmitter; wherein the receiver is designed to receive measurement signals radiated by a distance measuring device in the form of first electromagnetic waves, to mix them downward and to feed them to the analog-to-digital converter; wherein the analog-to-digital converter is designed to convert the downwardly mixed measurement signals into a data word stream and to feed them to the signal delay device; wherein the signal delay device is designed to delay the data word stream and to feed the delayed data word stream to the digital-to-analog converter; wherein the digital-to-analog converter is designed to convert the delayed data word stream into echo signals and to feed them to the transmitter; and wherein the transmitter is designed to mix the echo signals upwards and radiate them in the form of second electromagnetic waves to the distance measuring device; wherein the signal delay device includes: a demultiplexer; D∈ delay means; D additional delay means; a multiplexer; and a control unit; wherein the demultiplexer has a demultiplexer input and D demultiplexer outputs; wherein each of the D delay means has a delay input and a delay output; wherein each of the D additional delay means has an additional delay input and an additional delay output; wherein the multiplexer has 2.Math.D multiplexer inputs and a multiplexer output; wherein for each of the D delay means, on the one hand, the delay input and one of the D demultiplexer outputs are connected to one another via an input signal path and, on the other hand, the delay output and one of the 2.Math.D multiplexer inputs are connected to one another via a delay signal path; wherein, for each of the D additional delay means, on the one hand, the additional delay input is connected to one of the delay signal paths and, on the other hand, the additional delay output and one of the 2.Math.D multiplexer inputs are connected to one another via an additional delay signal path; wherein the demultiplexer is designed to divide an input data word stream having data words with an external transmission rate of S at the demultiplexer input into interleaved, parallel data word streams at an internal transmission rate of P=S/D in each case and to output these parallel data word streams at the D demultiplexer outputs; wherein each of the D delay means can be preset with a forwarding delay factor m∈0, and each of the D delay means is designed to delay each data word in the respective parallel data word stream at the delay input by a forwarding delay time Δt.sub.m=m/P and to output the delayed data word at the delay output; wherein each of the D additional delay means is designed to delay each data word in the respective delayed parallel data word stream at the additional delay input by an additional delay time of Δt.sub.z=1/P and to output the additionally delayed data word at the additional delay output; and wherein an output delay factor n∈0 can be preset to the control unit, the control unit is designed to determine the forwarding delay factor m from a predefined output delay factor n and to preset this to the D delay means and to control the multiplexer in such a manner that an output data word stream corresponding to the input data word stream with a time delay of Δt=n/S is output at the multiplexer output.

17. The simulator device according to claim 16, wherein the simulator device includes a single antenna for both transmission and reception.

18. The simulator device according to claim 16, wherein the simulator device is designed to simulate distances for distance measuring devices using radar or lidar.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In detail, there is a plurality of possibilities for designing and further developing the signal delay devices and the simulator device. Reference is made to the following description of a preferred embodiment of a simulator device with a signal delay device in conjunction with the drawings.

[0047] FIG. 1 schematically illustrates an embodiment of a simulator device.

[0048] FIG. 2 schematically illustrates a first embodiment of a signal delay device.

[0049] FIG. 3a-3j schematically illustrate data word streams in the first embodiment for n=4.

[0050] FIG. 4a-4j schematically illustrate data word streams in the first embodiment for n=5.

[0051] FIG. 5 schematically illustrates a second embodiment of a signal delay device.

[0052] FIG. 6a-6f schematically illustrate data word streams in the second embodiment for n=4.

[0053] FIG. 7a-7f schematically illustrate data word streams in the second embodiment for n=5.

DETAILED DESCRIPTION

[0054] FIG. 1 shows an embodiment of a simulator device 1 in a block diagram. The simulator device 1 has a receiver 2, an analog-to-digital converter 3, a signal delay device 4, a digital-to-analog converter 5, a transmitter 6 and an antenna 7. The simulator device 1 is part of simulator, not shown, for testing a distance measuring device 8.

[0055] The distance measuring device 8 is a radar distance measuring device which operates with signals in a frequency range around a frequency of 77 GHz. During operation, outside a simulator, the distance measuring device 8 determines a distance between the distance measuring device 8 and an object from an overall transit time of a signal. The overall transit time of the signal is determined, in particular, by the transit time of a measurement signal from the distance measuring device 8 to the object and the transit time of an echo signal reflected from the object back to the distance measuring device 8.

[0056] In the simulator device 1, the receiver 2 is designed to receive a measurement signal radiated by the distance measuring device 8 in the form of first electromagnetic waves 9 via the antenna 7, to mix it downwards and to feed it to the analog-to-digital converter 3. The analog-to-digital converter 3 is designed to convert the downwardly mixed measurement signal into a data word stream and to feed it to the signal delay device 4. The signal delay device 4 is designed to delay the data word stream by Δt and to feed the delayed data word stream to the digital-to-analog converter 5. By designing the signal delay device 4 to delay the data word stream, it is designed to simulate spatial distances. The same, thus, applies to the simulator device 1. The digital-to-analog converter 5 is designed to convert the delayed data word stream into an echo signal and supply it to the transmitter 6. The transmitter 6 is designed to mix the echo signal upwards and radiate it back to the distance measuring device 8 in the form of second electromagnetic waves 10.

[0057] The simulator device 1 thus generates an echo signal from the received measurement signal with a delay Δt and radiates it back to the distance measuring device 8. The echo signal is received by the distance measuring device 8 and when the measurement signal and echo signal are evaluated by the distance measuring device 8, the delay Δt added by the signal delay device 4 increases the overall transit time. The delay Δt generated by the signal delay device 4 appears as a transit time to the distance measuring device 8, which is why a distance Δd between the distance measuring device 8 and a simulated object can be set by setting the delay Δt. Due to the integration of the distance information into the electromagnetic waves 10, the simulator is an OTA device.

[0058] The signal delay device 4 can be implemented in various ways. FIG. 2 shows a first embodiment of the signal delay device 4 and FIG. 5 shows a second embodiment.

[0059] The first embodiment of the signal delay device 4 shown in FIG. 2 shows a demultiplexer 11, four delay means 12a-12d, four additional delay means 13a13d, a multiplexer 14 and a control unit 15. Accordingly, in this embodiment D=4. The four delay means 12a-12d, the four additional delay means 13a13d and the control unit 15 are implemented in one FPGA.

[0060] The demultiplexer 11 has one demultiplexer input 16 and four demultiplexer outputs 17a-17d. Each of the four delay means 12a-12d has one delay input 18a-18d and one delay output 19a-19d. Each of the four additional delay means 13a-13d has one additional delay input 20a-20d and one additional delay output 21a-21d. The multiplexer 14 has eight multiplexer inputs 22a-22h and one multiplexer output 23. Thus, the number of multiplexer inputs 22a22h is twice as large as the number of demultiplexer outputs 17a-17d.

[0061] In each of the four delay means 12a-12d, the delay input 18a-18d and one of the four demultiplexer outputs 17a-17d are connected to one another via an input signal path 24a-24d, and the delay output 19a-19d and one of the eight multiplexer inputs 22a-22h are connected to one another via a delay signal path 25a-25d. In each of the four additional delay means 13a-13d, the additional delay input 20a-20d is connected to one of the delay signal paths 25a25d, and the additional delay output 21a-21d and one of the eight multiplexer inputs 22a-22h are connected to one another via an additional delay signal path 26a-26d. The individual input signal paths 24a-24d are separate from one another, i.e. not connected to one another. The same applies to the individual delay signal paths 25a-25d and also to the additional delay signal paths 26a26d.

[0062] The demultiplexer 11 is designed to separate an input data word stream containing data words (a.sub.0, a.sub.1, a.sub.2, a.sub.3, a.sub.4, a.sub.5, a.sub.6, a.sub.7, a.sub.8, a.sub.9, a.sub.10, a.sub.11, . . . ) with an external transmission rate of S=2.5 GS/s at the demultiplexer input 16 into four parallel, interleaved data word streams (a.sub.0, a.sub.4, a.sub.8, . . . ) and (a.sub.1, a.sub.5, a.sub.9, . . . ) and (a.sub.2, a.sub.6, a.sub.10, . . . ) and (a.sub.3, a.sub.7, a.sub.11, . . . ) with an internal transmission rate, in each case, of P=S/D=(2.5 GS/s)/4=625 MS/s and to output these at the four demultiplexer outputs 17a-17d. In the data word streams, each data word has 10 bits.

[0063] Each of the four delay means 12a-12d can be preset with a forwarding delay factor m∈.sub.0 and each of the four delay means 12a-12d is designed to delay each data word in the respective parallel data word stream at the delay input 18a-18d by a forwarding delay time Δt.sub.m=m/P=m/(625 MS/s)=m.Math.1.6 ns and to output the delayed data word at the delay output 19a-19d. The forwarding delay time is identical for all four delay means 12a-12d.

[0064] Each of the four additional delay means 13a-13d is designed to delay each data word in the respective delayed parallel data word stream at the additional delay input 20a-20d by an additional delay time of Δt.sub.z=1/P=1/(625 MS/s)=1.6 ns and to output the additional delayed data word at the additional delay output 21a-21d.

[0065] An output delay factor n∈.sub.0 can be preset for the control unit 15. It is designed to determine the forwarding delay factor m from a preset output delay factor n and to preset it for the four delay means 12a-12d. Furthermore, it is designed to control the multiplexer 14 in such a way that an output data word stream corresponding to the input data word stream with a time delay of Δt=n/S=n/(2.5 GS/s)=n.Math.0.4 ns is output at the multiplexer output 23. For this, the control unit 15 is designed to determine the forwarding delay factor according to m=└n/4┘. Thus, form as a function of n:

TABLE-US-00001 n 0 1 2 3 4 5 6 7 8 m 0 0 0 0 1 1 1 1 2

[0066] FIGS. 3a-3j and 4a-4j show data word streams at certain locations in the signal delay device 4 according to the first embodiment and illustrate the setting of the multiplexer 14 by the control unit 15 so that a data word stream delayed by Δt compared to the data word stream at the demultiplexer input 16 is preset at the multiplexer output 23.

[0067] FIG. 3a-3j show the data word streams over time for n=4. Accordingly, m=1, Δt.sub.m=m/P=1/(625 MS/s)=1.6 ns and Δt=n/S=4.Math.0.4 ns=1.6 ns. The time axes of FIG. 3a-3j are synchronous to each other.

[0068] FIG. 3a shows the data word stream at the demultiplexer input 16, FIG. 3b at the multiplexer input 22a, FIG. 3c at the multiplexer input 22b, FIG. 3d at the multiplexer input 22c, FIG. 3e at the multiplexer input 22d, FIG. 3f at the multiplexer input 22e, FIG. 3g at the multiplexer input 22f, FIG. 3h at the multiplexer input 22g, FIG. 3i at the multiplexer input 22h and FIG. 3j at the multiplexer output 23.

[0069] While the data word streams at the demultiplexer input 16 and at the multiplexer output 23 have the external transmission rate S=2.5 GS/s, the data word streams between the demultiplexer outputs 17a-17d and the multiplexer inputs 22a-22h have the internal transmission rate P=625 MS/s.

[0070] The vertical arrows running from the data word streams in FIG. 3b-3i to the data word stream in FIG. 3j symbolize the setting of the multiplexer 14 by control unit 15.

[0071] FIG. 4a-4j show the data word streams for n=5. Accordingly, Δt=n/S=5.Math.0.4 ns=2.0 ns and is still m=1. The data word streams in FIG. 4a-4i are identical to those in FIG. 3a-3i. Only the data word stream shown in FIG. 4j is delayed by a further 0.4 ns compared to the data word stream shown in 3j. This also shows the necessity of the additional delay means 13a-13d. The data words a.sub.3 and a.sub.7 are provided by these at the correct time, since the delay means 12a12d already provide the next data words a.sub.7 and a.sub.11.

[0072] The second embodiment of the signal delay device 4 shown in FIG. 5 comprises a demultiplexer 11, four delay means 12a-12d, a multiplexer 14 and a control unit 15. Accordingly, D=4 in this embodiment. The four delay means 12a-12d and the control unit 15 are implemented in one FPGA.

[0073] The demultiplexer 11 has one demultiplexer input 16 and four demultiplexer outputs 17a-17d. Each of the four delay means 12a-12d has one delay input 18a-18d and one delay output 19a-19d. The multiplexer 14 has four multiplexer inputs 22a-22d and one multiplexer output 23. Therefore, the number of multiplexer inputs 22a-22d is as large as the number of demultiplexer outputs 17a-17d.

[0074] For each of the four delay means 12a-12d, the delay input 18a-18d and one of the four demultiplexer outputs 17a-17d are connected to one another via an input signal path 24a-24d and the delay output 19a-19d and one of the four multiplexer inputs 22a-22d are connected to one another via a delay signal path 25a-25d. The individual input signal paths 24a-24d are separate from one another, i.e. not connected to one another. The same applies to the individual delay signal paths 25a-25d.

[0075] The demultiplexer 11 is designed to divide an input data word stream containing data words (a.sub.0, a.sub.1, a.sub.2, a.sub.3, a.sub.4, a.sub.5, a.sub.6, a.sub.7, a.sub.8, a.sub.9, a.sub.10, a.sub.11, . . . ) with an external transmission rate of S=2.5 GS/s at the demultiplexer input 16 into four parallel, interleaved data word streams (a.sub.0, a.sub.4, a.sub.8, . . . ) and (a.sub.1, a.sub.5, a.sub.9, . . . ) and (a.sub.2, a.sub.6, a.sub.10, . . . ) and (a.sub.3, a.sub.7, a.sub.11, . . . ) with an internal transmission rate, in each case, of P=S/D=(2.5 GS/s)/4=625 MS/s and to output these at the four demultiplexer outputs 17a-17d. In the data word streams, each data word has 10 bits.

[0076] Each of the four delay means 12a-12d can be preset with a separate forwarding delay factor m.sub.d∈.sub.0 with d∈≤4 and each of the four delay means 12a-12d is designed to delay each data word in the respective parallel data word stream at the delay input 18a-18d by a forwarding delay time Δt.sub.m,d=m.sub.d/P=m.sub.d/(625 MS/s) and to output the delayed data word at the delay output 19a-19d. The forwarding delay time can thus be different between the four delay means 12a12d.

[0077] An output delay factor n∈.sub.0 can be preset for the control unit 15. This is designed to determine the separate forwarding delay factors m.sub.d from a preset output delay factor n and to preset them to the four settable delay means 12a12d. In addition, it is designed to control the multiplexer 14 in such a way that an output data word stream corresponding to the input data word stream with a time delay of Δt=n/S=n/(2.5 GS/s)=n.Math.0.4 ns is output at the multiplexer output 23. For this, the control unit is designed to determine the forwarding delay factors according to m.sub.d=[(n+d−1)/4] mit d∈≤4. Thus, for m.sub.d as a function of n:

TABLE-US-00002 n m.sub.1 m.sub.2 m.sub.3 m.sub.4 0 0 0 0 0 1 0 0 0 1 2 0 0 1 1 3 0 1 1 1 4 1 1 1 1 5 1 1 1 2 6 1 1 2 2 7 1 2 2 2 8 2 2 2 2

[0078] FIGS. 6a-6f and 7a-7f show data word streams at certain locations in the signal delay device 4 according to the second embodiment and illustrate the setting of the multiplexer 14 by the control unit 15 so that a data word stream delayed by Δt compared to the data word stream at the demultiplexer input 16 is preset at the multiplexer output 23.

[0079] FIG. 6a-6f show the data word streams over time for n=4. Accordingly, m.sub.1=m.sub.2=m.sub.3=m.sub.4=1, Δt.sub.m,1=Δt.sub.m,2=Δt.sub.m,3=Δt.sub.m,4=1.6 ns and Δt=n/S=4.Math.0.4 ns=1.6 ns. The time axes of FIG. 6a-6f are synchronous to one another.

[0080] FIG. 6a shows the data word stream at the demultiplexer input 16, FIG. 6b at the multiplexer input 22a, FIG. 6c at the multiplexer input 22b, FIG. 6d at the multiplexer input 22c, FIG. 6e at the multiplexer input 22d and FIG. 6f at the multiplexer output 23.

[0081] While the data word streams at the demultiplexer input 16 and at the multiplexer output 23 have the external transmission rate S=2.5 GS/s, the data word streams between the demultiplexer outputs 17a-17d and the multiplexer inputs 22a-22h have the internal transmission rate P=625 MS/s.

[0082] The vertical arrows running from the data word streams in FIG. 6b-6e to the data word stream in FIG. 6f symbolize the setting of the multiplexer 14 by the control unit 15.

[0083] FIG. 7a-7f show the data word streams for n=5. Thus, m.sub.1=m.sub.2=m.sub.3=1, m.sub.4=2, Δt.sub.m,1=Δt.sub.m,2=Δt.sub.m,3=1.6 ns, Δt.sub.m,4=3.2 ns and Δt=n/S=5.Math.0.4 ns=2.0 ns. The data word streams in FIG. 7a-7d are identical to those in FIG. 6a-6d. The data word stream shown in FIG. 6e is delayed by a further 1.6 ns so that data words a.sub.3 and a.sub.7 are available at the correct time. The data word stream shown in FIG. 7f is delayed by a further 0.4 ns compared to the data word stream shown in FIG. 6f.