GATE DRIVER ON ARRAY (GOA) SUBSTRATE, METHOD FOR FABRICATING SAME, AND DISPLAY DEVICE COMPRISING SAME

Abstract

A gate driver on array (GOA) array substrate, a method for fabricating the same, and a display device including the same, which include a GOA driving circuit. The GOA driving circuit includes a plurality of GOA units. Each of the GOA units includes a thin film transistor array layer, a first metal layer, an insulating layer, and a second metal layer. The first metal layer has a patterned signal line at a position crossing the second metal layer. The signal line includes a trunk portion and side walls formed of two opposite sides of the trunk portion. The side walls are shaped as arc-shaped grooves.

Claims

1. A gate driver on array (GOA) array substrate, comprising: a base substrate; and a GOA driving circuit disposed on the base substrate and comprising a plurality of GOA units connected to each other, wherein each of the GOA units comprises: a thin film transistor array layer; a first metal layer disposed on the thin film transistor array layer; an insulating layer disposed on the first metal layer; and a second metal layer disposed on the insulating layer; wherein the first metal layer has a patterned signal line at a position crossing the second metal layer, the signal line comprises a trunk portion and side walls formed of two opposite sides of the trunk portion, and the side walls are shaped as arc-shaped grooves.

2. The GOA array substrate according to claim 1, wherein the arc-shaped grooves are formed on the signal line by a half-tone mask and a photolithography pattern process.

3. The GOA array substrate according to claim 2, wherein the half-tone mask comprises a non-total light transmission area having various mask penetrating rates.

4. The GOA array substrate according to claim 1, wherein a thickness of the insulating layer on the arc-shaped grooves is same as a thickness of the insulating layer on the trunk portion.

5. The GOA array substrate according to claim 4, wherein the insulating layer is made of silicon nitride or silicon oxide.

6. The GOA array substrate according to claim 1, wherein a material of the first metal layer is same as a material of a gate metal layer of the thin film transistor array layer; and a material of the second metal layer is same as a material of a source/drain metal layer of the thin film transistor array layer.

7. The GOA array substrate according to claim 1, wherein the thin film transistor array layer comprises a plurality of scan lines parallel to each other, and the GOA drive circuit is configured to drive the scan lines.

8. A method for fabricating a gate driver on array (GOA) array substrate, comprising: S10: forming a first metal layer on a GOA driving circuit area of a base substrate, wherein the first metal layer has a patterned signal line at a cross-line position of the GOA driving circuit area, and the signal line comprises a trunk portion and side walls formed of two opposite sides of the trunk portion; S20: etching the side walls by a half-tone mask and a photolithography pattern process to form arc-shaped grooves; S30: forming an insulating layer on the first metal layer, wherein the insulating layer fills the arc-shaped grooves; S40: forming a second metal layer on the insulating layer.

9. The method for fabricating the GOA array substrate according to claim 8, wherein, in S20, the half-tone mask comprises a non-total light transmission area having various mask penetrating rates.

10. The method for fabricating the GOA array substrate according to claim 8, wherein, in S30, a thickness of the insulating layer on the arc-shaped grooves is same as a thickness of the insulating layer on the trunk portion.

11. The method for fabricating the GOA array substrate according to claim 8, wherein, in S30, the insulating layer is made of silicon nitride or silicon oxide.

12. The method for fabricating the GOA array substrate according to claim 8, wherein, in S10, a material of the first metal layer is same as a material of a gate metal layer of the thin film transistor array layer.

13. The method for fabricating the GOA array substrate according to claim 8, wherein, in S40, a material of the second metal layer is same as a material of a source/drain metal layer of the thin film transistor array layer.

14. A display device, comprising a gate driver on array (GOA) array substrate, wherein the GOA array substrate comprises: a base substrate; and a GOA driving circuit disposed on the base substrate and comprising a plurality of GOA units connected to each other, wherein each of the GOA units comprises: a thin film transistor array layer; a first metal layer disposed on the thin film transistor array layer; an insulating layer disposed on the first metal layer; and a second metal layer disposed on the insulating layer; wherein the first metal layer has a patterned signal line at a position crossing the second metal layer, the signal line comprises a trunk portion and side walls formed of two opposite sides of the trunk portion, and the side walls are shaped as arc-shaped grooves.

15. The display device according to claim 14, wherein the arc-shaped grooves are formed on the signal line by a half-tone mask and a photolithography pattern process.

16. The display device according to claim 15, wherein the half-tone mask comprises a non-total light transmission area having various mask penetrating rates.

17. The display device according to claim 14, wherein a thickness of the insulating layer on the arc-shaped grooves is same as a thickness of the insulating layer on the trunk portion.

18. The display device according to claim 17, wherein the insulating layer is made of silicon nitride or silicon oxide.

19. The display device according to claim 14, wherein a material of the first metal layer is same as a material of a gate metal layer of the thin film transistor array layer; and a material of the second metal layer is same as a material of a source/drain metal layer of the thin film transistor array layer.

20. The display device according to claim 14, wherein the thin film transistor array layer comprises a plurality of scan lines parallel to each other, and the GOA drive circuit is configured to drive the scan lines.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0031] FIG. 1 is a schematic cross-sectional structural diagram of a gate driver on array (GOA) unit of a GOA array substrate at a cross-line position according to an embodiment of the present disclosure.

[0032] FIG. 2 is a flowchart of a method for fabricating a GOA array substrate according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

[0033] The embodiments provided by the present disclosure can solve the technical problem that, in a current GOA array substrate or in a method for fabricating the same, a first metal layer (M1) and a second metal layer (M2) of a GOA unit are prone to short circuit, triggering overcurrent protection, and then causing a black screen of a display device.

[0034] Please refer to FIG. 1, which is a schematic cross-sectional structural diagram of a gate driver on array (GOA) unit of a GOA array substrate at a cross-line position according to an embodiment of the present disclosure. From FIG. 1, components of the embodiment of the present disclosure and a relative positional relationship among the components can be seen intuitively.

[0035] Specifically, the GOA array substrate comprises a base substrate 10 and a GOA driving circuit. The GOA driving circuit is disposed on the base substrate 10 and comprises a plurality of GOA units 20 connected to each other. Each of the GOA units 20 comprises a thin film transistor array layer 21, a first metal layer (M1) 22 disposed on the thin film transistor array layer 21, an insulating layer 23 disposed on the first metal layer (M1) 22; and a second metal layer (M2) 24 disposed on the insulating layer 23.

[0036] The first metal layer (M1) 22 has a patterned signal line at a position crossing the second metal layer (M2) 24. The signal line comprises a trunk portion 221 and side walls 222 formed of two opposite sides of the trunk portion 221. The side walls 222 are shaped as arc-shaped grooves.

[0037] Specifically, the base substrate 10 may be a glass substrate. A material of the glass substrate is uniform and has high transparency, low reflectance, and good thermal stability so that its properties can be kept stable after multiple high-temperature processes. This preferred embodiment does not limit the base substrate 10. When fabricating the GOA array substrate, those skilled in the art can select the base substrate 10 according to specific needs.

[0038] Specifically, the thin film transistor array layer 21 comprises a plurality of scan lines (not shown) parallel to each other. The GOA drive circuit is configured to drive the scan lines and drive on or off pixels in a display area of the GOA array substrate.

[0039] Specifically, the first metal layer (M1) 22 may be a metal compound conductive layer formed of a plurality of metal layers. The first metal layer (M1) 22 is generally formed by a vapor deposition technique, and then etched to form various signal lines. Further, a material of the first metal layer (M1) 22 is same as a material of a gate metal layer of the thin film transistor array layer.

[0040] Furthermore, the arc-shaped grooves are formed on the signal line by a half-tone mask and a photolithography pattern process. The half-tone mask comprises a non-total light transmission area having various mask penetrating rates. A photolithography process of exposing, developing and etching a photoresist material using the half-tone mask makes the first metal layer (M1) 22 to form a patterned signal line at a cross-line position of a GOA bus line area.

[0041] Specifically, the insulating layer 23 covers the first metal layer (M1) 22. The insulating layer 23 may comprise one or two layers and may be formed of silicon oxide, silicon nitride, or silicon oxynitride. Preferably, the insulating layer 23 is formed of silicon nitride. A thickness of the insulating layer 23 on the arc-shaped grooves is same as a thickness of the insulating layer 23 on the trunk portion 221.

[0042] Specifically, the second metal layer (M2) 24 may be a metal compound conductive layer formed of a plurality of metal layers. The second metal layer (M2) 24 is generally formed by a vapor deposition technique, and then etched to form various signal lines. Further, a material of the second metal layer (M2) 24 is same as a material of a source/drain metal layer of the thin film transistor array layer.

[0043] In a GOA array substrate provided by the present disclosure, a signal line of a first metal layer (M1) at a cross-line position in a GOA unit is provided with grooves having a certain arc, which increases a deposition thickness of an insulating layer at the position, thereby effectively preventing a short circuit between the signal line of the first metal layer (M1) and the signal line of the second metal layer (M2), and improving stability of a GOA drive circuit.

[0044] Please refer to FIG. 1 and FIG. 2. FIG. 2 is a flowchart of a method for fabricating a GOA array substrate according to an embodiment of the present disclosure. The method comprises the following steps.

[0045] S10: forming a first metal layer 22 on a GOA driving circuit area of a base substrate 10, wherein the first metal layer 22 has a patterned signal line at a cross-line position of the GOA driving circuit area, and the signal line comprises a trunk portion 221 and side walls 222 formed of two opposite sides of the trunk portion;

[0046] Specifically, S10 further comprises the following steps.

[0047] First, a base substrate 10 is provided. The base substrate 10 is provided with a thin film transistor array layer 21. The thin film transistor array layer 21 comprises a plurality of scan lines (not shown) parallel to each other. Then, a first metal layer (M1) 22 is deposited on a GOA driving circuit area of the base substrate 10. The first metal layer (M1) 22 is disposed on the thin film transistor array layer 21. The first metal layer (M1) 22 may be a metal compound conductive layer formed of a plurality of metal layers. The first metal layer (M1) 22 is etched to form various signal lines. Further, a material of the first metal layer (M1) 22 is same as a material of a gate metal layer of the thin film transistor array layer.

[0048] S20: etching the side walls 222 by a half-tone mask and a photolithography pattern process to form arc-shaped grooves.

[0049] Specifically, S20 further comprises the following steps.

[0050] First, the side walls 222 are etched by a half-tone mask and a photolithography pattern process to form arc-shaped grooves. The arc-shaped grooves are formed on the signal line by a half-tone mask and a photolithography pattern process. The half-tone mask comprises a non-total light transmission area having various mask penetrating rates. Furthermore, a photolithography process of exposing, developing and etching a photoresist material using the half-tone mask makes the first metal layer (M1) 22 to form a patterned signal line at a cross-line position of a GOA bus line area.

[0051] S30: forming an insulating layer 23 on the first metal layer 22, wherein the insulating layer 23 fills the arc-shaped grooves.

[0052] Specifically, S30 further comprises the following steps.

[0053] An insulating layer 23 is formed on the first metal layer 22 by plasma enhanced chemical vapor deposition (PECVD). The insulating layer 23 fills the arc-shaped grooves. The insulating layer 23 may comprise one or two layers, and may be formed of silicon oxide, silicon nitride, or silicon oxynitride. Preferably, the insulating layer 23 is formed of silicon nitride. A thickness of the insulating layer 23 on the arc-shaped grooves is same as a thickness of the insulating layer 23 on the trunk portion 221.

[0054] S40: forming a second metal layer 24 on the insulating layer 23.

[0055] Specifically, S40 further comprises the following steps.

[0056] A second metal layer (M2) 24 is deposited on the insulating layer 23 by physical vapor deposition (PVD). The second metal layer (M2) 24 may be a metal compound conductive layer formed of a plurality of metal layers. The second metal layer (M2) 24 is etched to form various signal lines. Further, a material of the second metal layer (M2) 24 is same as a material of a source/drain metal layer of the thin film transistor array layer. The thin film transistor array layer 21, the first metal layer (M1) 22, the insulating layer 23, and the second metal layer (M2) 24 form GOA units 20 in the GOA driving circuit. The GOA units 20 are configured to drive the scan lines of the thin film transistor array layer 21 and drive on or off pixels in a display area of the GOA array substrate.

[0057] The present disclosure further provides a display device comprising the aforementioned gate driver on array (GOA) array substrate. The specific implementation of the GOA array substrate can refer to the previous embodiments, and will not be described herein.

[0058] In the above, a GOA array substrate, a method for fabricating the same, and a display device comprising the same provided by the present disclosure, a signal line of a patterned first metal layer is designed to have grooves with a certain arc at a position crossing a signal line of a second metal layer, which increase a deposition thickness of an insulating layer at the position, thereby preventing a short circuit between the signal line of the first metal layer and the signal line of the second metal layer and improving stability of a GOA drive circuit in the GOA array substrate.

[0059] It should be understood that those skilled in the art may make equivalent replacements or changes based on the technical solutions and inventive concepts of the present application, and all such changes or replacements shall fall within the scope of the claims of the present application.