A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.

A semiconductor device with a high on-state current is provided. An oxide semiconductor film; a source electrode and a drain electrode over the oxide semiconductor film; an interlayer insulating film positioned to cover the oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the oxide semiconductor film; a barrier insulating film over the oxide semiconductor film; and a gate electrode over the gate insulating film are included. The barrier insulating film is positioned between the source electrode and the gate insulating film and between the drain electrode and the gate electrode. An opening is formed in the interlayer insulating film so as to overlap with a region between the source electrode and the drain electrode. The barrier insulating film, the gate insulating film, and the gate electrode are positioned in the opening of the interlayer insulating film. Above the barrier insulating film, the gate insulating film is in contact with the interlayer insulating film.

Disclosed is a semiconductor device comprising an oxide semiconductor layer on a substrate and including a first part and a pair of second parts that are spaced apart from each other across the first part, a gate electrode on the first part of the oxide semiconductor layer, and a pair of electrodes on corresponding second parts of the oxide semiconductor layer. A first thickness of the first part of the oxide semiconductor layer is less than a second thickness of each second part of the oxide semiconductor layer. A number of oxygen vacancies in the first part of the oxide semiconductor layer is less than a number of oxygen vacancies in each second part of the oxide semiconductor layer.

A display panel and a display apparatus are disclosed. The display apparatus includes the display panel and a sensing device. The display panel includes a substrate, a first signal line, and a first dummy conductive pattern. The substrate includes a functional display region, a buffer region, and a general display region. The buffer region is located between the functional display region and the general display region. The first signal line and the first dummy conductive pattern are disposed on the substrate and correspond to the buffer region. The first dummy conductive pattern is overlapped with a part of the first signal line. The sensing device is overlapped with the functional display region.

A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

A display panel is provided. The display panel includes a plurality of signal lines and a testing circuit. The testing circuit includes a plurality of transistors electrically connected to the plurality of signal lines. The plurality of transistors are disposed in at least two groups, and a number of transistors of each group of the at least two groups is less than a total number of the plurality of signal lines. Therefore, the testing circuit of the display panel of the disclosure can reduce the circuit placement space in the horizontal direction.

A liquid crystal display device comprises a display panel, at least one signal generator, and a plurality of wires. The display panel has a plurality of input ends to receive data signal. The at least one signal generator has a plurality of output ends to supply the data signal to the input ends of the display panel, respectively. The wires connects the output ends of the at least one signal generator to the input ends of the display panel, respectively, the wires having lengths measured between the output ends of the at least one signal generator and the input ends of the display panel, respectively, the length of the wires being different from each other according to location of the output ends of the at least one signal generator.

Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

A display device includes a substrate having a first surface and a second surface opposite to the first surface. The display device includes a first conductive layer disposed on the first surface and a second conductive layer disposed on the second surface. The first conductive layer and the second conductive layer are disposed on the opposite sides of the substrate. The display device includes a connective portion at least partially disposed in the substrate and penetrating from the first surface to the second surface. The first conductive layer is electrically connected to the second conductive layer through the connective portion. The display device includes a light-emitting element disposed on the first surface and an insulation layer disposed on the first conductive layer. Along a direction perpendicular to the first surface, the first electrode and the second electrode of the light-emitting element are not overlapped with the connective portion.