Component Carrier With Embedded IC Substrate Inlay, and Manufacturing Method

Abstract

A component carrier, including a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure, a cavity in the stack, an inlay substrate at least partially embedded in the cavity. The inlay substrate includes a component and an IC substrate stacked one above the other, a first redistribution structure that electrically connects the component to a first component carrier main surface, and a second redistribution structure that electrically connects the IC substrate to a second component carrier main surface opposed to the first component carrier main surface.

Claims

1. A component carrier, comprising: a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure; a cavity in the stack; an inlay substrate at least partially embedded in the cavity, wherein the inlay substrate comprises a component and an IC substrate stacked one above the other; a first redistribution structure that electrically connects the component to a first component carrier main surface; and a second redistribution structure that electrically connects the IC substrate to a second component carrier main surface being opposed to the first component carrier main surface.

2. The component carrier according to claim 1, further comprising: an interposer structure arranged between the component and the IC substrate.

3. The component carrier according to claim 1, wherein the component and the IC substrate are indirectly electrically connected by an electrically conductive material or are directly electrically connected by means of thermal compression bonding.

4. The component carrier according to claim 1, wherein, in a vertical direction (Z), the component is located above the IC substrate in the cavity, or wherein, in a vertical direction (Z), the IC substrate is located above the component in the cavity.

5. The component carrier according to claim 1, wherein the component and the IC substrate are functionally coupled.

6. The component carrier according to claim 1, wherein the component carrier comprises a first further component stacked with the IC substrate.

7. The component carrier according to claim 6, wherein the component and the first further component are arranged on two opposing main surfaces of the IC substrate.

8. The component carrier according to claim 5, wherein the component and the first further component are arranged side by side on the same main surface of the IC substrate.

9. The component carrier according to claim 1, wherein the component carrier comprises a second further component being surface mounted on the stack.

10. The component carrier according to claim 1, wherein the IC substrate comprises a plurality of electrically conductive layer structures, and wherein an integration density of the electrically conductive layer structures of the IC substrate is higher than an integration density of electrically conductive layer structures of the stack.

11. The component carrier according to claim 1, wherein the component comprises an active component.

12. The component carrier according to claim 1, comprising at least one of the following: wherein the component comprises at least one pad being oriented downwardly in a vertical direction (Z); wherein the component comprises at least one pad being oriented upwardly in a vertical direction (Z).

13. The component carrier according to claim 1, wherein the cavity is formed in an electrically insulating core layer of the electrically insulating layer structure.

14. The component carrier according to claim 1, wherein the first further component comprises at least one of a further active component, a passive component, a heat removal block.

15. The component carrier according to claim 1, wherein the component carrier comprises an optical pathway formed partially by at least one of the stack or partially by the component.

16. The component carrier according to claim 1, wherein the IC substrate comprises a further redistribution structure.

17. The component carrier according to claim 1, wherein the IC substrate is electrically coupled with the at least one electrically conductive layer structure of the stack.

18. The component carrier according to claim 1, wherein the inlay substrate is embedded in electrically insulating material.

19. A method of manufacturing a component carrier, the method comprising: forming a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure; forming a cavity in the stack; at least partially embedding an inlay substrate in the cavity, wherein the inlay substrate comprises a component and an IC substrate stacked one above the other, providing a first redistribution structure that electrically connects the component to a first component carrier main surface, and providing a second redistribution structure that electrically connects the IC substrate to a second component carrier main surface being opposed to the first component carrier main surface.

20. The method according to claim 19, the method further comprising at least one of the following steps: inserting the component or the IC substrate in the cavity and thereafter stacking the respective other one of the component and the IC substrate thereon in the cavity; stacking the component and the IC substrate before embedding the component and the IC substrate in the cavity; pressing the component in a first electrically insulating layer of the electrically insulating layer structure, so that the component becomes at least partially embedded by the first electrically insulating layer; pressing the IC substrate in a second electrically insulating layer of the electrically insulating layer structure, so that the IC substrate becomes at least partially embedded by the second electrically insulating layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0092] FIG. 1 shows a cross-sectional view of a stack of a component carrier with an inlay substrate, according to an exemplary embodiment of the disclosure.

[0093] FIG. 2 shows a cross-sectional view of a stack of a component carrier as known in the art.

[0094] FIG. 3 and FIG. 4 show a cross-sectional view of a stack of a component carrier with an inlay substrate and a surface mounted component, according to an exemplary embodiment of the disclosure.

[0095] FIG. 5 and FIG. 6 illustrate cross-sectional views of different configurations of a component carrier with an inlay substrate and a plurality of surface mounted components, according to exemplary embodiments of the disclosure.

[0096] FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, and FIG. 12 show different steps in the manufacturing of a component carrier comprising an inlay substrate, according to exemplary embodiments of the disclosure.

[0097] FIG. 13 shows a component carrier with an inlay substrate and a plurality of surface mounted components, according to an exemplary embodiment of the disclosure.

[0098] FIG. 14 shows a cross-sectional view of a stack of a component carrier with an inlay substrate comprising an interposer structure, according to an exemplary embodiment of the disclosure.

[0099] FIG. 15 shows a cross-sectional view of a stack of a component carrier comprising an interposer structure as known in the art.

[0100] FIG. 16 shows a cross-sectional view of a stack of a component carrier structure according to an exemplary embodiment of the disclosure, demonstrating electrical paths.

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

[0101] The illustrations in the drawings are schematically presented. It is noted that in different figures, similar or identical elements or features are provided with the same reference signs. In order to avoid unnecessary repetitions, elements or features which have already been elucidated with respect to a previously described embodiment are not elucidated again at a later position of the description.

[0102] Furthermore, spatially relative terms, such as “front” and “back”, “above” and “below”, “left” and “right”, et cetera are used to describe an element's relationship to another element(s) as illustrated in the figures. Thus, the spatially relative terms may apply to orientations in use which differ from the orientation depicted in the figures. Obviously, all such spatially relative terms refer to the orientation shown in the figures only for ease of description and are not necessarily limiting, as an apparatus according to an embodiment of the disclosure can assume orientations different than those illustrated in the figures when in use.

[0103] FIG. 1 shows a cross-sectional view of a stack 101 of a component carrier 100 with an inlay substrate 110, according to an exemplary embodiment of the disclosure. The component carrier 100 comprises a stack 101 comprising an electrically conductive layer structure 102 and an electrically insulating layer structure 103, a cavity 104 in the stack 101, and an inlay substrate 110 embedded in the cavity 104, wherein the inlay substrate 110 comprises a component 105 stacked on top of an IC substrate 106. The electrically insulating layer structure 103 comprises an electrically insulating core layer 120, electrically insulating material 115, and electrically insulating layers 116 covering a top main surface and a bottom main surface of the component carrier 100. The component carrier 100 is further provided with electrically conductive through connections 111, formed as vias, and electrically connecting the layers of the electrically conductive layer structure 102. In accordance with an exemplary embodiment of the disclosure, the electrically insulating material 115 comprises or consists of prepreg. As can also be taken from FIG. 1, the component carrier 100 comprises a redistribution structure 109, arranged underneath the IC substrate 106. The stack 101 of the component carrier 100 has an overall height or thickness H1 in a vertical stacking direction Z. H1 is significantly lower than H2 (compare FIG. 2 described above), although the component carriers 100 and 200 substantially have the same functionality, provided by similar electronic elements 105, 106 and 205, 206, respectively.

[0104] Hence, by at least partially embedding an inlay 110 comprising the component 105 and the IC substrate 106 according to exemplary embodiments of the disclosure, the electronic elements are protected by the stack 101, but are still electronically and functionally connected to the component carrier 100. In addition, the component carrier 100 has a very compact design when compared to conventional component carriers, which becomes apparent from H1 being smaller than H2.

[0105] FIG. 3 shows a cross-sectional view of a stack 101 of a component carrier 100 with an inlay substrate 110 and a surface mounted component 108 (i.e., mounted on a surface of the component carrier 100), according to an embodiment of the disclosure. In this example, in a vertical direction Z, the component 105 is located above the IC substrate 106 in the cavity 104. In some embodiments, which are for example illustrated in FIG. 13, a first further component 107 may also be stacked with the IC substrate 106. However, in the example shown in FIG. 3, a second further component 108 is surface mounted on a bottom main surface of the component carrier 100. The second further component 108 and the IC substrate 106 are electrically connected. Furthermore, there are provided solder balls 114, which may serve as mounting points for even further components. As can also be taken from FIG. 3, there is provided a first redistribution structure 109a that electrically connects the component 105 to a first component carrier main surface (e.g., a top main surface), and a second redistribution structure 109b that electrically connects the IC substrate 106 to a second component carrier main surface (e.g., a bottom main surface) being opposed to the first component carrier main surface.

[0106] The component carrier 100 depicted in FIG. 4 shows a similar configuration. However, in this example, the second further component 108 is surface mounted on a top main surface of the component carrier 100 and accordingly, the IC substrate 106 is stacked on top of the component 105 in the cavity 104.

[0107] In both examples, as shown in FIGS. 3 and 4, the surface mounted second further component 108 is electrically coupled with the embedded IC substrate 106 in the cavity 104. Thus, the component 105, which is also electrically and/or functionally coupled to the IC substrate 106, is also (indirectly) electrically and/or functionally coupled to the second further component 108.

[0108] FIG. 5 and FIG. 6 show cross-sectional views of different configurations of a component carrier 100 with an inlay substrate 110 and a plurality of surface mounted components 108, 112, and 117, according to exemplary embodiments of the disclosure. In comparison to the examples of the disclosure depicted for example in FIG. 3 and FIG. 4, the component carriers 100 of FIG. 5 and FIG. 6 further comprise a third further component 112 and a fourth further component 117. All further components 108, 112, and 117 are surface mounted via solder balls 114 and are thus directly or indirectly electrically and/or functionally connected to one another and also to the IC substrate 106 or the component 105, respectively.

[0109] In FIG. 5, the first further component 108 is surface mounted on the bottom main surface of the component carrier 100 and directly electrically connected to the IC substrate 106. The component carrier also comprises a first and second redistribution structure 109a, 109b and the IC substrate 106 is electrically connected to the component 105 stacked on top of the IC substrate 106.

[0110] In FIG. 6, the IC substrate 106 is, however, stacked on top of the component 105. The first further component 108 is surface mounted, via solder balls 114, on a top main surface of the component carrier 100, and electrically and/or functionally connected (coupled) to the IC substrate 106 and thus also electrically and/or functionally coupled to the component 105 in the cavity 104.

[0111] FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, and FIG. 12 show different steps in the manufacturing of a component carrier 100 comprising an inlay substrate 110, according to exemplary embodiments of the disclosure.

[0112] In FIG. 7 a stack 101 is provided comprising an electrically conductive layer structure 102 and an electrically insulating layer structure 103, which is comprised of the electrically insulating core layer 120. In the exemplary embodiment shown in FIG. 7 to FIG. 10, the stack 101 is placed on a release layer 113 (e.g., a temporary carrier) and fixed thereon, e.g., by use of an adhesive.

[0113] In FIG. 8 a cavity 104 is formed, e.g., by one of laser or mechanical drilling, etching, cutting, or a similar and suitable procedure.

[0114] In FIG. 9 an inlay substrate 110, comprising a component 105 stacked on top and electrically and functionally coupled to an IC substrate 106, is placed within the cavity 104. The component 105 and the IC substrate 106 may be stacked before embedding the component 105 and the IC substrate 106 in the cavity 104. Here, the IC substrate 106 comprises a further redistribution structure 109c.

[0115] In FIG. 10 an electrically insulating material 115, such as prepreg, is added. The electrically insulating material 115 fills the voids of the cavity 104 and becomes part of the electrically insulating layer structure 103.

[0116] Alternatively, according to other embodiments of the disclosure, the component 105 or the IC substrate 106 may be placed in the cavity 104 first, and thereafter the respective other one of the component 105 and the IC substrate 106 may be stacked thereon in the cavity 104.

[0117] In yet another embodiment of the disclosure, one of the component 105 or the IC substrate 106 may be pressed in a first electrically insulating layer of the electrically insulating layer structure 103 in the cavity 104, so that it becomes at least partially embedded by the first electrically insulating layer. Subsequently, the respective other one of the component 105 or the IC substrate 106 may be pressed in a second electrically insulating layer of the electrically insulating layer structure 103, so that it also becomes at least partially embedded by the second electrically insulating layer and so that the component 105 and the IC substrate 106 become electrically and/or functionally connected. By pressing one of the component 105 or the IC substrate 106, or the prefabricated inlay substrate 110, into the cavity 104, any excess electrically insulating material 115 is displaced. Preferably, the first electrically insulating layer and/or the second electrically insulating layer comprises prepreg.

[0118] In FIG. 11 after embedding the component 105 and the IC substrate 106 in the cavity 104, the stack 101 is removed from the release layer 113.

[0119] In FIG. 12 electrically conductive layer structures 102, electrically insulating layers 116, and electrically conductive through connections 111 are formed. The component carrier 100 may then be subject to further manufacturing steps, which are not shown in detail, but which may for example result in a component carrier 100 as depicted in one of the FIGS. 3 to 6 described in detail above.

[0120] FIG. 13 shows a component carrier 100 with an inlay substrate 110 and a plurality of surface mounted components 108, 112, and 117, according to an exemplary embodiment of the disclosure. The embodiment shown in FIG. 13 may be compared to the embodiment depicted in FIG. 5 described above. However, as has been mentioned earlier, the component carrier 100 comprises a component 105, an IC substrate 106, and additionally, a first further component 107 stacked with the IC substrate 106, wherein the component 105 and the first further component 107 are arranged on two opposing main surfaces of the IC substrate 106. The IC substrate 106 is electrically and/or functionally connected to both, the component 105 and the first further component 107. Hence, the IC substrate 106 serves as a substrate for both, the component 105 and the first further component 106, which may contribute to a compact design of the component carrier 100.

[0121] FIG. 14 shows a component carrier 100 with an inlay substrate 110 according to a further exemplary embodiment and similar to the one shown in FIG. 1. However, components 105, 107, and 108 are arranged on a top main surface of the component carrier, and in the inlay substrate 110, there is comprised an interposer structure 118 electrically connected to both the components 105, 107, and 108 and to the IC substrate 106, which is also comprised by the inlay substrate 110 and stacked with the interposer structure 118. However, it is noted that in addition to the interposer structure 118, according to a further exemplary embodiment, the inlay substrate 110 may of course further comprise one or more components 105, 107, 108, stacked with the IC substrate 106 and/or the interposer structure 118. As can further be taken from FIG. 14, the interposer structure enables connecting a plurality of components 105, 107, 108 comprising a plurality of electrical contacts, to the IC substrate 106 comprising fewer electrical contacts. Furthermore, the height H1 of the component carrier 100 is significantly reduced to the height H2 of the prior art component carrier 200, which is shown in FIG. 15. This advantageous arrangement for saving vertical space is effected by embedding the inlay substrate 110 in the cavity 104. In contrast, component carrier 200 has all elements, i.e., the components 205, the interposer structure 218, and the IC substrate 206, surface mounted to the stack 201.

[0122] FIG. 16 shows the component carrier 100 of FIG. 5 according to a further exemplary embodiment. However, in FIG. 16, the component carrier 100 does not comprise vertical electrically conductive through connections 111. Furthermore, in order not to obscure the Figure, the inlay substrate 110 is depicted without any further elements shown. FIG. 16 demonstrates with reference numerals 1610 and the dashed line an electrical path in a vertical direction, as would be expected if vertical electrically conductive through connections 111 were provided.

[0123] However, by embedding the inlay substrate 110 according to an embodiment, the electrical path, now represented by dotted lines 1611, leads from surface mounted components 112, 117 via the top lay of the electrically conductive layer structure 102 through the inlay substrate 110 and its elements (i.e., interposer structure 118, component, IC substrate 106, etc.) via a bottom layer of the electrically conductive layer structure 102 to a component 108 (or vice versa). In other words, instead of (or in addition to) providing electrically conductive through connections 111, as may be known from the prior art, further electronic elements may be integrated into a vertical electrical path and may facilitate said electrical path 1611.

[0124] It should be noted that the term “comprising” does not exclude other elements or steps and the article “a” or “an” does not exclude a plurality. Also, elements described in association with different embodiments may be combined.

[0125] Implementation of the disclosure is not limited to the preferred embodiments shown in the figures and described above. Instead, a multiplicity of variants is possible which variants use the solutions shown and the principle according to the disclosure even in the case of fundamentally different embodiments.

REFERENCE SIGNS

[0126] H1 Height of stack [0127] H2 Height of stack (prior art) [0128] X Horizontal direction [0129] Y Horizontal direction [0130] Z Vertical (stacking) direction [0131] 100 Component Carrier [0132] 101 Stack [0133] 102 Electrically conductive layer structure [0134] 103 Electrically insulating layer structure [0135] 104 Cavity [0136] 105 Component [0137] 106 IC substrate [0138] 107 First further component [0139] 108 Second further component [0140] 109a First redistribution structure [0141] 109b Second redistribution structure [0142] 109c Further redistribution structure [0143] 110 Inlay substrate [0144] 111 Electrically conductive through connection [0145] 112 Third further component [0146] 113 Release layer [0147] 114 Solder ball [0148] 115 Electrically insulating material, prepreg [0149] 116 Electrically insulating layer, solder resist [0150] 117 Fourth further component [0151] 118 Interposer structure [0152] 120 Electrically insulating core layer [0153] 200 Component carrier (prior art) [0154] 201 Stack (prior art) [0155] 205 Component (prior art) [0156] 206 IC substrate (prior art) [0157] 218 Interposer structure (prior art) [0158] 1610 Electric pathway (prior art) [0159] 1611 Electric pathway