METHOD FOR PROGRAMMING CHARGE TRAP FLASH MEMORY

Abstract

The present disclosure provides a method for programming charge trap flash memory, including: enabling a channel of a charge trap storage component, to form a transverse electric field between a source and a drain, to generate primary electrons flowing from the source to the drain; colliding, by the primary electrons after a preset time, with the drain to generate electron holes; applying voltages to the drain and a substrate, where the electron holes are accelerated downward by the action of the electric field to collide with the substrate, to generate secondary electrons; and applying voltages to a gate and the substrate, to form a vertical electric field, wherein the secondary electrons generate tertiary electrons under the action of the vertical electric field and the tertiary electrons are injected into an insulating storage medium layer of the charge trap storage component, to complete a programming operation.

Claims

1. A method for programming charge trap flash memory, comprising: S1) providing a charge trap storage component, enabling a channel of the charge trap storage component, and forming a transverse electric field between a source and a drain of the charge trap storage component, to generate primary electrons flowing from the source to the drain; S2) after a preset time, making the primary electrons collide with the drain to generate electron holes; S3) applying voltages to the drain and a substrate of the charge trap storage component, wherein the electron holes are accelerated downward by the action of the electric field to collide with the substrate, to generate secondary electrons; wherein the voltage applied to the substrate of the charge trap storage component is lower than the voltage applied to the drain, and the voltage difference is not lower than 5 V; and S4) applying voltages to a gate and the substrate of the charge trap storage component, to form a vertical electric field, wherein the secondary electrons generate tertiary electrons under the action of the vertical electric field and the tertiary electrons are injected into an insulating storage medium layer of the charge trap storage component, to complete a programming operation.

2. The method for programming charge trap flash memory as in claim 1, wherein the charge trap storage component comprises: a silicon oxide nitride oxide silicon (SONOS) component, a polysilicon alumina nitride oxide silicon (SANOS) component, a metal alumina nitride oxide silicon (MANOS) component, or a nitride read only memory (NROM) component.

3. The method for programming charge trap flash memory as in claim 1, wherein the forming the transverse electric field comprises: applying voltages to the source and the drain of the charge trap storage component, wherein the voltage applied to the source of the charge trap storage component is lower than the voltage applied to the drain of the charge trap storage component.

4. The method for programming charge trap flash memory as in claim 1, wherein the preset time is from 10 ns to 100 ns.

5. (canceled)

6. The method for programming charge trap flash memory as in claim 1, wherein at operation S4), the voltage applied to the substrate of the charge trap storage component is lower than the voltage applied to the gate.

7. The method for programming charge trap flash memory as in claim 1, wherein before the operation S1), the method further comprises pre-erasing the charge trap storage component to eliminate residual charges in the insulating storage medium layer.

8. The method for programming charge trap flash memory as in claim 7, wherein the pre-erasing is implemented by: applying voltages to the gate and the drain of the charge trap storage component, to reach a band-to-band tunneling (BTBT) condition and generate second electron holes, wherein the second electron holes are injected into the insulating storage medium layer to neutralize residual electrons in the insulating storage medium layer.

9. The method for programming charge trap flash memory as in claim 8, wherein the voltage applied to the drain of the charge trap storage component is higher than the voltage applied to the gate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1 is a schematic flowchart of a method for programming charge trap flash memory according to the present disclosure.

[0028] FIG. 2 is a schematic structural diagram of a SONOS component according to the present disclosure.

[0029] FIG. 3 is a schematic diagram illustrating the operation of pre-erasure in a method for programming charge trap flash memory according to the present disclosure.

[0030] FIG. 4 is a schematic diagram of a principle of pre-erasure in a method for programming charge trap flash memory according to the present disclosure.

[0031] FIG. 5 is a schematic diagram illustrating the operation of forming a transverse electric field in a method for programming charge trap flash memory according to the present disclosure.

[0032] FIG. 6 is a schematic diagram illustrating the operation of generating secondary electrons in a method for programming charge trap flash memory according to the present disclosure.

[0033] FIG. 7 is a schematic diagram illustrating the operation of injecting tertiary electrons into a silicon nitride (SiN) layer in a method for programming charge trap flash memory according to the present disclosure.

REFERENCE NUMERALS

[0034] 1 Substrate [0035] 2 Source region [0036] 3 Drain region [0037] 4 Tunnel oxide layer [0038] 5 Silicon nitride layer [0039] 6 High-temperature oxide layer [0040] 7 Polysilicon layer [0041] 8 Self-aligned metal silicide layer [0042] S1 to S4 Various Operations

DETAILED DESCRIPTION

[0043] The following describes implementations of the present disclosure using specific embodiments. A person skilled in the art may easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. The present disclosure may also be implemented or applied through other different specific implementations. Various details in this specification may also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure.

[0044] Reference is made to FIG. 1 to FIG. 7. It should be noted that the drawings provided in this embodiment only exemplify the basic idea of the present disclosure. Therefore, only the components related to the present disclosure are shown in the drawings, and are not drawn according to the quantities, shapes, and sizes of the components during actual implementation. During actual implementation, the types, quantities, and proportions of the components may be randomly changed, and the layout pattern of the components may be more complicated.

[0045] As shown in FIG. 1 to FIG. 7, the present disclosure provides a method for programming charge trap flash memory, and the method for programming charge trap flash memory comprises the following operations:

[0046] Operation S1) Provide a charge trap storage component, enable a channel of the charge trap storage component, form a transverse electric field between a source and a drain of the charge trap storage component, in order to generate primary electrons flowing from the source to the drain.

[0047] Specifically, a charge trap storage component is provided. The charge trap storage component includes, but is not limited to, a SONOS component, a SANOS component, a MANOS component, or an NROM component. The MANOS component further includes a tantalum nitride oxide silicon (TANOS) component and other MANOS components according to different metal materials, the NROM component is an improved structure of the SONOS component, and the SONOS component is a charge trap storage component that is most commonly used. Any charge trap storage component structure comprising an insulating storage medium layer is applicable to the present disclosure, and details are not described herein.

[0048] For example, as shown in FIG. 2, the charge trap storage component may be a SONOS component, and the SONOS component comprises a substrate 1, a source region 2, and a drain region 3 formed in the substrate 1. Further, a Tunnel Oxide layer 4, a SiN layer 5, a high-temperature oxide (HTO) layer 6, a polysilicon (Poly) layer 7, and a self-aligned metal silicide (salicide, used as a control gate) layer 8 may be sequentially formed above the substrate 1. In this embodiment, the substrate 1 may be a P-type substrate, and the source region 2 and the drain region 3 may be N-type doped regions. During actual use, the structure and material(s) of the SONOS component may be adjusted as required, without limitation.

[0049] Specifically, as shown in FIG. 5, in this embodiment, voltages V.sub.G, V.sub.S, and V.sub.D are respectively applied to a gate, a source, and a drain of the SONOS component, in order to enable a channel of the SONOS component and form a transverse electric field between the source and the drain of the SONOS component, and in order to generate primary electrons flowing from the source to the drain. In this embodiment, the voltage V.sub.G applied to the gate of the SONOS component may be a positive voltage, which turns on the SONOS component. For example, the voltage V.sub.G applied to the gate may be about 4.3 V (or higher than 4.3 V, which includes, but is not limited to 5 V, 5.5 V, 6 V, or 7 V). During actual use, any voltage that can turn on the SONOS component may be applied to the gate of the SONOS component, which is not limited to this embodiment.

[0050] The voltage V.sub.S applied to the source of the SONOS component is lower than the voltage V.sub.D applied to the drain of the SONOS component, in order to form the transverse electric field. In this embodiment, the voltage V.sub.S applied to the source of the SONOS component may be about 0 V, and the voltage V.sub.D applied to the drain may be about 6 V. For example, the difference between the voltage V.sub.S applied to the source and the voltage V.sub.D applied to the drain is not lower than 5 V, the difference between the voltage V.sub.S applied to the source and the voltage V.sub.D applied to the drain and specific voltage values thereof may be set according to actual device parameters, and details are not described herein.

[0051] In another implementation of the present disclosure, before operation S1) is performed, the method further comprises pre-erasing the charge trap storage component to eliminate residual charges in an insulating storage medium of the charge trap storage component.

[0052] As shown in FIG. 3 and FIG. 4, voltages are applied to the gate and the drain of the SONOS component, to reach a BTBT condition and generate electron holes, where the electron holes are injected into the SiN layer 5 (an insulating storage medium layer) to neutralize residual electrons in the SiN layer 5. The voltage V.sub.D applied to the drain of the SONOS component may be higher than the voltage V.sub.G applied to the gate. For example, the voltage V.sub.G applied to the gate of the SONOS component may be about −5 V, and the voltage V.sub.D applied to the drain of the SONOS component may be about 5 V, in order to reach a BTBT condition to generate the electron holes to neutralize the residual electrons in the SiN layer 5. During actual use, the voltage V.sub.G applied to the gate and the voltage V.sub.D applied to the drain may be set based on parameters such as the dimensions and material(s) of the SONOS component.

[0053] Operation S2) After a preset time, make the primary electrons collide with the drain to generate electron holes.

[0054] Specifically, for example, the preset time may be from 10 ns to 100 ns. During actual use, the preset time may be adjusted based on factors such as the electric field, as long as the primary electrons is able to collide with the drain to generate the electron holes, which is not limited to this embodiment.

[0055] Operation S3) Apply voltages to the drain and a substrate of the charge trap storage component, wherein the electron holes are accelerated downward by the action of the electric field to collide with the substrate, to generate secondary electrons.

[0056] Specifically, as shown in FIG. 6, in this embodiment, voltages are respectively applied to the drain and a substrate of the SONOS component, and the voltage V.sub.B applied to the substrate of the SONOS component may be lower than the voltage V.sub.D applied to the drain, provided that the difference between the voltage V.sub.B applied to the substrate and the voltage V.sub.D applied to the drain can enable relatively heavy electron holes to accelerate to collide with the substrate to generate relatively light electrons.

[0057] For example, the difference between the voltage V.sub.B applied to the substrate and the voltage V.sub.D applied to the drain may not be lower than about 5 V, 9 V, or 10 V, details of which are not described herein. In this embodiment, the voltage V.sub.B applied to the substrate may be about −4 V, and the voltage V.sub.D applied to the drain may be about 7 V. For simplicity of operation, the voltage V.sub.D applied to the drain may continue to have the voltage value in the previous operation (i.e., about 6 V), and only the value of the voltage V.sub.B applied to the substrate is adjusted. The specific voltage values may be set as required, and are not limited to this embodiment.

[0058] Operation S4) Apply voltages to a gate and the substrate of the charge trap storage component, to form a vertical electric field, wherein the secondary electrons generate tertiary electrons under the action of the vertical electric field and the tertiary electrons are injected into an insulating storage medium layer of the charge trap storage component, to complete a programming operation.

[0059] Specifically, as shown in FIG. 7, in this embodiment, voltages are respectively applied to a gate and the substrate of the SONOS component to form a vertical electric field, and the voltage V.sub.B applied to the substrate of the SONOS component is lower than the voltage V.sub.G applied to the gate, provided that the difference between the voltage V.sub.B applied to the substrate and the voltage V.sub.G applied to the gate can transform the secondary electrons into tertiary electrons and inject the tertiary electrons into the SiN layer 5 of the SONOS component through the Tunnel Oxide layer 4.

[0060] For example, the difference between the voltage V.sub.B applied to the substrate and the voltage V.sub.G applied to the gate may not be lower than about 9 V, 10 V, or 12 V, the details of which are not described herein. In this embodiment, the voltage V.sub.B applied to the substrate may be about −5 V, and the voltage V.sub.G applied to the gate may be about 6 V. For simplicity of operation, the voltage V.sub.B applied to the substrate may continue to have the voltage value (about −4 V) in the previous operation, and only the value of the voltage V.sub.G applied to the gate is adjusted. The specific voltage values may be set as required, and are not limited to this embodiment.

[0061] In the method for programming charge trap flash memory according to the present disclosure, programming is performed based on tertiary electron excitation. During programming, both a transverse electric field and a vertical electric field are utilized, in order to greatly improve the programming efficiency and reduce the power consumption. In addition, the read and write currents during programming may be high, damage to the Tunnel Oxide layer may be small, and the device reliability may be greatly improved, which, together with the low-cost advantage of the charge trap storage component, offers a promising future for the charge trap flash memory.

[0062] In summary, the present disclosure provides a method for programming charge trap flash memory, comprising: providing a charge trap storage component, and enabling a channel of the charge trap storage component, forming a transverse electric field between a source and a drain of the charge trap storage component, to generate primary electrons flowing from the source to the drain; colliding, by the primary electrons after a preset time, with the drain to generate electron holes; applying voltages to the drain and a substrate of the charge trap storage component, where the electron holes are accelerated downward by the action of the electric field to collide with the substrate, to generate secondary electrons; and applying voltages to a gate and the substrate of the charge trap storage component, to form a vertical electric field, where the secondary electrons form tertiary electrons under the action of the vertical electric field and the tertiary electrons are injected into an insulating storage medium layer of the charge trap storage component, to complete a programming operation.

[0063] In the method for programming charge trap flash memory according to the present disclosure, during programming, tertiary electrons are generated by using a transverse electric field and a vertical electric field, which can effectively increase the read and write currents of a charge trap storage component, reduce the power consumption, and improve the device reliability, which, together with the low-cost advantage of the charge trap storage component, offers a promising future for the charge trap flash memory. Therefore, the present disclosure effectively overcomes various shortcomings in the prior art, and has a high industrial value.

[0064] The foregoing embodiments merely exemplify the principles and effects of the present disclosure, but are not intended to limit the present disclosure. Any person skilled in the art may make modifications or changes on the foregoing embodiments without departing from the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical idea of the present disclosure shall be covered by the claims of the present disclosure.