Diode and Power Circuit

Abstract

A diode and a power circuit are provided. The diode may include: a first electrode layer; a drift layer located above the first electrode layer, a doping concentration of the drift layer is less than that of the first electrode layer; and the drift layer includes an active region and a terminal region surrounding the active region; a second electrode layer disposed in the active region, where the second electrode layer and the drift layer are doped with impurities of different properties; and the second electrode layer includes a first region and a second region surrounding the first region, and the first region and the second region are separated by a first insulation trench, where the first region is connected to a power supply through a first conductor, and the second region is connected to the power supply through a second conductor, a first resistor, and the first conductor sequentially.

Claims

1-12. (canceled)

13. A diode, comprising: a first electrode layer; a drift layer located above the first electrode layer, wherein the drift layer and the first electrode layer are doped with impurities of a same property, a second doping concentration of the drift layer is less than a first doping concentration of the first electrode layer, and the drift layer comprises an active region and a terminal region surrounding the active region; and a second electrode layer disposed in the active region, wherein the second electrode layer and the drift layer are doped with impurities of different properties, the second electrode layer comprises a first region and a second region surrounding the first region, and the first region and the second region are separated by a first insulation trench, a first conductor disposed above the first region; a second conductor disposed above the second region; and a first resistor disposed between the first conductor and the second conductor, wherein the first region is connected to a power supply through the first conductor, and the second region is connected to the power supply through the second conductor, the first resistor, and the first conductor sequentially.

14. The diode according to claim 13, wherein a second depth by which the second region extends into the active region is greater than a first depth by which the first region extends into the active region.

15. The diode according to claim 13, wherein the first region comprises a plurality of third regions above the active region, adjacent third regions in the plurality of third regions are separated by a second insulation trench, and a fourth depth by which the second insulation trench extends into the active region is greater than a third depth by which a third region of the plurality of third regions extends into the active region.

16. The diode according to claim 13, wherein a barrier layer is disposed between the first region and the active region, and the barrier layer is configured to slow down migration of a carrier between the first region and the active region.

17. The diode according to claim 13, wherein the first resistor is made of polycrystalline silicon.

18. The diode according to claim 13, wherein a first semiconductor layer is disposed between the drift layer and the first electrode layer, the drift layer and the first semiconductor layer are doped with impurities of the same property, and a third doping concentration of the first semiconductor layer is between the second doping concentration of the drift layer and the first doping concentration of the first electrode layer.

19. The diode according to claim 13, wherein the first region and the second region are doped with an acceptor impurity, and the first electrode layer and the drift layer are doped with a donor impurity, or wherein the first region and the second region are doped with a donor impurity, and the first electrode layer and the drift layer are doped with an acceptor impurity.

20. The diode according to claim 13, wherein at least one field limiting ring is disposed in the terminal region.

21. The diode according to claim 20, wherein a metal field plate is disposed above the field limiting ring.

22. The diode according to claim 21, wherein the diode further comprises a resistive field plate surrounding the metal field plate.

23. The diode according to claim 13, wherein the diode further comprises a cut-off ring surrounding an upper portion of the terminal region.

24. A power circuit, comprising: an insulated gate bipolar transistor; and a diode, the diode including: a first electrode layer; a drift layer located above the first electrode layer, wherein the drift layer and the first electrode layer are doped with impurities of a same property, a second doping concentration of the drift layer is less than a first doping concentration of the first electrode layer, and the drift layer comprises an active region and a terminal region surrounding the active region; and a second electrode layer disposed in the active region, wherein the second electrode layer and the drift layer are doped with impurities of different properties, the second electrode layer comprises a first region and a second region surrounding the first region, and the first region and the second region are separated by a first insulation trench, a first conductor disposed above the first region; a second conductor disposed above the second region; and a first resistor disposed between the first conductor and the second conductor, wherein the first region is connected to a power supply through the first conductor, and the second region is connected to the power supply through the second conductor, the first resistor, and the first conductor sequentially.

25. The power circuit according to claim 24, wherein a second depth by which the second region extends into the active region is greater than a first depth by which the first region extends into the active region.

26. The power circuit according to claim 24, wherein the first region comprises a plurality of third regions above the active region, adjacent third regions in the plurality of third regions are separated by a second insulation trench, and a fourth depth by which the second insulation trench extends into the active region is greater than a third depth by which a third region of the plurality of third regions extends into the active region.

27. The power circuit according to claim 24, wherein a barrier layer is disposed between the first region and the active region, and the barrier layer is configured to slow down migration of a carrier between the first region and the active region.

28. The power circuit according to claim 24, wherein the first resistor is made of polycrystalline silicon.

29. The power circuit according to claim 24, wherein a first semiconductor layer is disposed between the drift layer and the first electrode layer, the drift layer and the first semiconductor layer are doped with impurities of the same property, and a third doping concentration of the first semiconductor layer is between the second doping concentration of the drift layer and the first doping concentration of the first electrode layer.

30. The power circuit according to claim 24, wherein the first region and the second region are doped with an acceptor impurity, and the first electrode layer and the drift layer are doped with a donor impurity, or wherein the first region and the second region are doped with a donor impurity, and the first electrode layer and the drift layer are doped with an acceptor impurity.

31. The power circuit according to claim 24, wherein at least one field limiting ring is disposed in the terminal region.

32. The power circuit according to claim 31, wherein a metal field plate is disposed above the field limiting ring.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0037] FIG. 1 is a schematic structural diagram of a diode;

[0038] FIG. 2 is a schematic structural diagram of a power circuit;

[0039] FIG. 3 is a schematic structural diagram of a diode;

[0040] FIG. 4A is a schematic structural diagram of a diode according to an embodiment of this application;

[0041] FIG. 4B is a top view of the diode shown in FIG. 4A;

[0042] FIG. 5 is a schematic structural diagram of a diode according to an embodiment of this application;

[0043] FIG. 6A is a schematic structural diagram of a diode according to an embodiment of this application;

[0044] FIG. 6B is a top view of the diode shown in FIG. 6A; and

[0045] FIG. 7 is a schematic structural diagram of a diode according to an embodiment of this application.

DESCRIPTION OF EMBODIMENTS

[0046] The following describes technical solutions of the embodiments in this application with reference to accompanying drawings. It is clear that the described embodiments are merely some but not all of embodiments of this application.

[0047] A diode is widely used, is an important power element, and may be applied to a plurality of power circuits, such as an inverter circuit, a rectifier circuit, and a freewheeling circuit.

[0048] FIG. 2 shows a power circuit that can convert a direct current into an alternating current. The power circuit may be a three-phase inverter circuit that includes three bridge arms. The three bridge arms are configured to generate a U phase, a V phase, and a W phase. Two switching elements may be disposed on each bridge arm in series. By controlling connection and disconnection of the switching elements on different bridge arms, a direct current may be converted into an alternating current, so that an alternating current motor may be driven. The switching element on the bridge arm generally includes a diode and an IGBT. In other words, the diode is one of critical components of the power circuit.

[0049] It may be understood that FIG. 2 is merely used as an example to describe a purpose of the diode, but does limit the purpose of the diode. There are other purposes of the diode, which are not enumerated herein.

[0050] When the diode changes from an on state to an off state, under an action of a reverse voltage, a large quantity of carriers stored in a terminal region are extracted through an electrode layer. A hole is extracted through a P-type anode layer, and an electron is extracted through an N-type cathode layer. Due to factors such as diffusion of a P-type impurity, an edge of the P-type anode layer is curve-shaped. The curved edge is closer to the terminal region, and therefore a large quantity of holes in the terminal region are extracted through the curved edge, resulting in high current density and a large amount of heat. In addition, curvature effect of the curved edge causes an electric field to concentrate, thereby generating an avalanche, so that currents of the curved edge are further concentrated, thereby generating more heat. The heat may burn the diode.

[0051] The reverse voltage refers to a voltage at which the diode is in an off state. In other words, the reverse voltage is applied to the diode, and the diode enters the off state. A forward voltage is opposite to the reverse voltage. When the forward voltage is applied to the diode, the diode enters an on state. A carrier is a particle with a charge that may move freely. In the field of semiconductors, the carrier generally refers to an electron and a hole. In other words, the electron and the hole may be collectively referred to as a carrier, the electron is one type of the carrier, and the hole is another type of the carrier. The hole is also referred to as an electron hole (electron hole), and is a vacancy left on a covalent bond after one electron is lost on the covalent bond.

[0052] FIG. 3 shows a solution. In this solution, an outer region of a P-type anode layer does not cover a metal electrode. When a diode is on, an electric potential of the outer region is lower than an electric potential of a central region, efficiency of injecting carriers into a terminal region through the outer region is low, and fewer carriers are injected. When the diode is off, a small quantity of carriers are extracted through the outer region, so as to avoid a risk of burning caused by current concentration in the outer region. In this manner, if a width of the outer region covering the metal electrode is small, effect of suppressing current concentration in the outer region is not obvious. A risk of burning caused by current concentration still exists. If the width of an outer region covering the metal electrode is large, an area of the central region covering the metal electrode is small, so that a conduction characteristic of the diode is affected.

[0053] Referring to FIG. 4A, an embodiment of this application provides a diode, including an electrode layer 200 and a drift layer 300 disposed on one side of the electrode layer 200. For ease of description, a direction of a side of the electrode layer 200 facing the drift layer 300 may be referred to as an upper direction of the electrode layer 200, that is, the drift layer 300 is located above the electrode layer 200. Correspondingly, a direction of a side of the electrode layer 200 away from the drift layer 300 may be referred to as a lower direction of the electrode layer 200. In addition, in the following description, for layers or components located above the electrode layer 200, an upper direction of the layers or components refers to a direction away from the electrode layer 200, and a lower direction refers to a direction close to the electrode layer 200.

[0054] As shown in FIG. 4A, the drift layer 300 includes an active region 310 and a terminal region 320. The terminal region 320 surrounds the active region 310. In other words, the active region 310 is a central region of the drift layer 300, and the terminal region 320 is an edge region of the active region 310.

[0055] An electrode layer 100 is disposed at an upper portion of the active region 310. The electrode layer 100 may be divided into a region 110 and a region 120. The region 120 surrounds the region 110, or the region 120 is located around the region 110. In other words, the region 110 is a central region of the electrode layer 100, and the region 120 is an edge region of the electrode layer 100. The upper portion of the active region 310 refers to an end of the active region 310 away from the electrode layer 200.

[0056] As shown in FIG. 4A, an insulation trench 130 is disposed between the region 110 and the region 120. In other words, the region 110 and the region 120 are separated by an insulation trench 130. The insulation trench 130 is insulated. In an example, a depth of the insulation trench 130 is from 4 um to 7 um.

[0057] As shown in FIG. 4A, the insulation trench 130 may include an insulation layer 131. The insulation layer 131 forms a periphery of the insulation trench 130, so that the insulation trench 130 is insulated. In this way, an electric field of the region 110 may be prevented from extending into the region 120. In some embodiments, the insulation layer 131 may be made of silicon dioxide.

[0058] A conductor 140 is disposed at an upper portion of the region 110. The conductor 140 is in contact with the region 110, so that the region 110 may be connected to a power supply A1 (not shown) through the conductor. A conductor 160 is disposed at an upper portion of the region 120. The conductor 160 is in contact with the region 120. There is a resistor 150 between the conductor 140 and the conductor 160. In other words, the conductor 140 and the conductor 160 are connected by the resistor 150. The conductor 160 is not directly connected to the power supply A1, but is connected to the power supply A1 through the resistor 150 and the conductor 140. Therefore, the region 120 is connected to the power supply A1 through the conductor 160, the resistor 150, and the conductor 140 sequentially.

[0059] When the diode is on, the resistor 150 enables an electric potential of the region 120 to be lower than an electric potential of the region 110, that is, the resistor 150 may reduce the electric potential of the region 120. In this way, efficiency of injecting carriers into the terminal region 320 by the region 120 is low. Therefore, when the diode is off, fewer carriers flow through the region 120, thereby suppressing current concentration in the region 120, and suppressing a risk of burning caused by current concentration in the region 120. In addition, when the diode is off, the carriers flow through the resistor 150 through the region 120, and an electric potential of the resistor 150 is increased, thereby reducing an electric potential difference between the region 120 and the electrode layer 200, further reducing the carriers that flow through the region 120, and reducing a risk of burning caused by current concentration in the region 120. In addition, a capability of the resistor 150 for blocking a carrier or a resistance value of the resistor 150 may be adjusted by a material or a wiring length of the resistor 150, without occupying an excessive area of the electrode layer 100, so that an area of the region 110 may be ensured, and impact on a conduction characteristic of the diode is small.

[0060] In this embodiment of this application, the resistor 150 is an object whose resistivity is between a conductor and an insulator. The resistor has a large resistivity, which may block a current from passing through, but not completely block the current from passing through. In some embodiments, the resistor 150 may be specifically polycrystalline silicon. In this embodiment of this application, a conductor (for example, the conductor 140 or the conductor 160) is an object that has an extremely low resistivity and is easy to conduct a current. In some embodiments, the conductor may be a metal or a metal electrode, such as a tungsten electrode or an aluminum electrode. In other embodiments, the conductor may be another object having a good conductivity. A material of the conductor is not specifically limited in this embodiment of this application.

[0061] In addition, in the embodiments of this application, “contact” may be understood as “adjacent”, and generally means that two objects in a block shape or a sheet shape are adjacent to each other, or one of the two objects is located on a surface of the other object. In addition, in this embodiment of this application, “connection” may mean direct contact of two objects. The “connection” may also mean that two objects are connected by a third object, that is, one side or one end of the third object is in contact with one of the two objects, and the other side or the other end of the third object is in contact with the other one of the two objects.

[0062] In some embodiments, referring to FIG. 4B, a part of the conductor 140 that is in contact with the resistor 150 is staggered with the conductor 160 in a thickness direction, and has a preset distance. Accordingly, the resistor 150 may have a length in the thickness direction. Therefore, in a case in which a small area of the electrode layer 100 is occupied, a wiring length of the resistor 150 connecting the conductor 140 and the conductor 160 may be increased, and a capability of the resistor 150 for blocking a carrier or a resistance value of the resistor 150 is increased.

[0063] The vertical direction shown in FIG. 4A may correspond to a y-axis direction in a three-dimensional coordinate system, a width direction corresponds to an x-axis direction in the three-dimensional coordinate system, and the thickness direction shown in FIG. 4B corresponds to a z-axis direction in the three-dimensional coordinate system.

[0064] The conductor 140 may be used as an electrode B1 of the diode. A conductor 210 located below the electrode layer 200 may be used as an electrode B2 of the diode. The electrode B1 may be an anode (anode) of the diode, and the electrode B2 may be a cathode (cathode) of the diode. Alternatively, the electrode B1 may be a cathode (cathode) of the diode, and the electrode B2 may be an anode (anode) of the diode. That is, the electrode B1 may be an anode or a cathode; and the electrode B2 may be an anode or a cathode. When the electrode B1 is an anode, the electrode B2 is a cathode; and when the electrode B2 is an anode, the electrode B1 is a cathode.

[0065] In some embodiments, the electrode B1 is an anode, and the electrode B2 is a cathode. In this case, the electrode layer 100 may be a P (positive) semiconductor, and is used as a P-type anode region. The P-type semiconductor refers to a semiconductor doped with a P-type impurity. The P-type impurity may also be referred to as an acceptor impurity (acceptor impurity), and is an impurity that may provide a hole for a semiconductor material, for example, a group III element such as B, Al, Ga, and In.

[0066] The electrode layer 200 may be an N (negative) semiconductor, and is used as an N-type cathode region. The N-type semiconductor refers to a semiconductor doped with an N-type impurity. The N-type impurity may also be referred to as a donor impurity (donor impurity), and is an impurity that may provide an electron for a semiconductor material, for example, a group V element such as phosphorus, arsenic, and antimony.

[0067] In some embodiments, the electrode B2 is an anode, and the electrode B1 is a cathode. In this case, the electrode layer 100 is an N-type semiconductor, and is used as an N-type cathode region. The electrode layer 200 is a P-type semiconductor layer, and is used as a P-type anode region.

[0068] Properties of an impurity doped into the drift layer 300 and an impurity doped into the electrode layer 200 are the same. That is, when the electrode layer 200 is a P-type semiconductor, the drift layer 300 is also a P-type semiconductor. That is, when the electrode layer 200 is an N-type semiconductor, the drift layer 300 is also an N-type semiconductor. A doping concentration of the impurity in the drift layer 300 is lower than a doping concentration of the impurity in the electrode layer 200. In other words, the drift layer 300 is a lightly doped semiconductor, and the electrode layer 200 is a heavily doped semiconductor. Light doping means that less impurities are doped into a semiconductor. Heavy doping, corresponding to the light doping, means that a large quantity of impurities is doped into a semiconductor. In other words, doping may be classified into light doping and heavy doping based on a quantity of impurities to be doped.

[0069] In some embodiments, there is a semiconductor layer 400 between the drift layer 300 and the electrode layer 200. Properties of an impurity doped into the semiconductor layer 400 and an impurity doped into the electrode layer 200 are the same. That is, when the electrode layer 200 is a P-type semiconductor, the semiconductor layer 400 is also a P-type semiconductor. That is, when the electrode layer 200 is an N-type semiconductor, the semiconductor layer 400 is also an N-type semiconductor. A doping concentration of the impurity in the semiconductor layer 400 is lower than the doping concentration in the electrode layer 200, but is higher than the doping concentration in the drift layer 300. That is, the doping concentration of impurities in the electrode layer 200, the doping concentration of impurities in the semiconductor layer 400, and the doping concentration of impurities in the drift layer 300 decreases sequentially.

[0070] The semiconductor layer 400 may also be referred to as a field stop layer, and may prevent an electric field in the drift layer 300 from extending to the electrode layer 200, thereby avoiding electric leakage of the diode at the electrode layer 200, reducing a risk of breakdown of the diode, and improving reliability of the diode.

[0071] Returning to FIG. 4A, in some embodiments, at least one field limiting ring (FLR) 321 is disposed at an upper portion of the terminal region 320. The at least one field limiting ring 321 is embedded into the terminal region 320 from an upper surface of the terminal region. The field limiting ring 321 is also used as a field limiting ring junction of the electrode layer 100. Correspondingly, the electrode layer 100 is used as a main junction of the field limiting ring 321. Properties of an impurity doped into the field limiting ring 321 and an impurity doped into the electrode layer 100 are the same. That is, when the electrode layer 100 is a P-type semiconductor, the field limiting ring 321 is also a P-type semiconductor. That is, when the electrode layer 100 is an N-type semiconductor, the field limiting ring 321 is also an N-type semiconductor. The field limiting ring 321 may increase a breakdown voltage of the electrode layer 100. Specifically, when a reverse voltage V1 applied to the electrode layer 100 is lower than a breakdown voltage Vb of the electrode layer 100, the electric field may be extended to the field limiting ring. When the reverse voltage V1 applied to the electrode layer 100 increases, the increased voltage is borne by the field limiting ring 321. In this way, the field limiting ring 321 is equivalent to a voltage divider of the electrode layer 100, and may increase the breakdown voltage of the electrode layer 100.

[0072] Still referring to FIG. 4A, in some embodiments, a field plate (FP) 323 is disposed above the field limiting ring 321. For example, a field plate 323 may be a metal field plate (MFP). The field plate 323 may increase the breakdown voltage of the electrode layer 100. Specifically, silicon dioxide is used as a protective layer on an upper surface of the terminal region 320, that is, the upper surface is covered with a silicon dioxide layer. Because there are movable charges and traps in the silicon dioxide layer, there is a positive charge on an interface between the silicon dioxide layer and the terminal region 320, and another charge may also be attached to a surface of the silicon dioxide layer. These charges cause concentration and instability of an electric field on a surface of the terminal region 320, thereby affecting a withstand voltage characteristic of the electrode layer 100. The field plate 323 may disperse an electric field of a surface of the terminal region 320, thereby improving a withstand voltage level of the electrode layer 100, that is, increasing the breakdown voltage of the electrode layer 100.

[0073] On the surface of the terminal region 320, a dielectric layer 325 is covered between adjacent field plates 323. The dielectric layer 325 may also be referred to as an insulation layer, and may be used as a protective layer on the surface of the terminal region 320. In some embodiments, the dielectric layer 325 may be made of silicon dioxide.

[0074] Still referring to FIG. 4A, in some embodiments, the field plate 323 is surrounded by a field plate 324, that is, the field plate 324 is disposed around the field plate 323. For example, the field plate 324 may be a resistive field plate (RFP). For example, the field plate 324 may be made of polycrystalline silicon. The field plate 324 may also disperse the electric field on the surface of the terminal region 320, thereby increasing the breakdown voltage of the electrode layer 100.

[0075] In some embodiments, a cut-off ring 322 is disposed at an outer edge of an upper portion of the terminal region 320. That is, the cut-off ring 322 surrounds the upper portion of the terminal region 320. Properties of an impurity doped into the cut-off ring 322 and an impurity doped into the terminal region 320 are the same. That is, when the terminal region 320 is an N-type semiconductor, the cut-off ring 322 is an N-type semiconductor. That is, when the terminal region 320 is a P-type semiconductor, the cut-off ring 322 is a P-type semiconductor. In addition, a doping concentration of the cut-off ring 322 is greater than a doping concentration of the terminal region 320. The cut-off ring 322 may increase a breakdown voltage of the terminal region 320. Specifically, the cut-off ring 322 may cut off an electric field in the terminal region 320 that passes through a side wall of the terminal region 320, so as to avoid leakage of the diode at the side wall of the terminal region 320, thereby reducing a risk of breakdown of the diode, and improving reliability of the diode.

[0076] The structure of the diode is described above with reference to FIG. 4A and FIG. 4B. Next, a solution for preparing the semiconductor device shown in FIG. 4A is described by using an example.

[0077] A silicon wafer (for example, float-zone silicon (float-zone silicon)) having a thickness and a certain doping concentration may be selected as the drift layer 300.

[0078] An upper surface structure of the drift layer 300 may be prepared first. Specifically, the field limiting ring 321, the cut-off ring 322, and the electrode layer 100 may be prepared by an ion implantation doping process and a push knot process. Then, an oxide layer (for example, a silicon dioxide layer) is deposited on an upper surface of the drift layer 300 to be used as a mask. Etching is performed in a region corresponding to the insulation trench 130 to obtain a U-shaped groove, and an oxide layer on a surface of the region 120 is etched off. Then, a U-shaped insulation layer is prepared in a U-shaped groove in a thermal growth manner, and an insulation layer is prepared on a surface of the region 120, so as to obtain an insulation layer 131. A resistor 150 (for example, polycrystalline silicon) is then deposited on the insulation layer 131. Afterwards, an insulation layer is deposited on the resistor 150. The oxide layer corresponding to the conductor 140 in the region 110 and the oxide layer corresponding to the conductor 160 in the region 120 are etched off, and the oxide layer or the insulation layer corresponding to the conductor in the resistor 150 is etched off. Finally, the conductor 140 and the conductor 160 are deposited in a corresponding region. The “corresponding conductor” refers to a position that needs to or is to contact the conductor.

[0079] In addition, for preparation processes of the field plate 323, the field plate 324, and the dielectric layer 325, reference may be made to the description in the prior art. Details are not described herein again.

[0080] In this way, the upper surface structure of the drift layer 300 may be prepared.

[0081] Then, the drift layer 300 may be flipped over to prepare a lower surface structure of the drift layer 300. Specifically, impurities may be injected into a lower end of the drift layer 300 by an ion implantation doping process and a push knot, to prepare the semiconductor layer 400 and the electrode layer 200. Energy of an ion beam used to prepare the semiconductor layer 400 is higher than that of an ion beam used to prepare the electrode layer 200. Then, the conductor 210 may be prepared on a side that is of the electrode layer 200 and that is away from the drift layer 300.

[0082] Therefore, the diode shown in FIG. 4A may be prepared.

[0083] In addition, the foregoing describes only an example of a preparation process of the diode shown in FIG. 4A, and does not constitute a limitation. In another embodiment, the diode shown in FIG. 4A may be prepared by using another process. Details are not described herein again.

[0084] Referring to FIG. 5, an embodiment of this application further provides a diode. The diode includes an electrode layer 200, and a drift layer 300 disposed on one side of the electrode layer 200. The drift layer 300 includes an active region 310 and a terminal region 320. The terminal region 320 surrounds the active region 310. An electrode layer 100 is disposed at an upper portion of the active region 310. The electrode layer 100 may be divided into a region 110 and a region 120. The region 120 surrounds the region 110. An insulation trench 130 is disposed between the region 110 and the region 120.

[0085] A conductor 140 is disposed at an upper portion of the region 110. The conductor 140 is in contact with the region 110, so that the region 110 may be connected to a power supply A1 through the conductor. A conductor 160 is disposed at an upper portion of the region 120. The conductor 160 is in contact with the region 110. There is a resistor 150 between the conductor 140 and the conductor 160. The conductor 160 is not directly connected to the power supply A1, but is connected to the power supply A1 through the resistor 150 and the conductor 140. Therefore, the region 120 is connected to the power supply A1 through the conductor 160, the resistor 150, and the conductor 140 sequentially.

[0086] Still referring to FIG. 5, in some embodiments, a semiconductor layer 400 is disposed between the electrode layer 200 and the drift layer 300.

[0087] In some embodiments, at least one field limiting ring 321 is disposed at an upper portion of the terminal region 320. A field plate 323 is disposed above the field limiting ring 321. On the surface of the terminal region 320, a dielectric layer 325 is covered between adjacent field plates 323. The field plate 323 is surrounded by a field plate 324. A cut-off ring 322 is disposed at an outer edge of an upper portion of the terminal region 320.

[0088] For specific implementations and functions of the components in the diode shown in FIG. 5, reference may be made to the foregoing descriptions of the diode shown in FIG. 4A.

[0089] Different from the diode shown in FIG. 4A, in the diode shown in FIG. 5, a depth by which the region 120 extends into the active region 310 is greater than a depth by which the region 110 extends into the active region 310. Referring to FIG. 5, a direction of an extension depth is downward in a vertical direction. The extension depth specifically refers to a degree of downward depth along the vertical direction. An extension depth of the region in the active region 310 may also be understood as a degree to which a lower end of the region is close to the electrode layer 200. As an extension depth of the region in the active region 310 is larger, a lower end of the region is closer to the electrode layer 200. The extension depth may be referred to as a junction depth for short. The lower end of the region is an end of the region closest to the electrode layer 200. In the diode shown in FIG. 5, a junction depth of the region 120 is large, and an interface between the region 120 and the drift layer 300 is large, so that an electric field of the interface may be dispersed, thereby suppressing generation of heat, reducing a risk that the diode is burned, and improving reliability of the diode.

[0090] In addition, the diode shown in FIG. 5 may be prepared with reference to a preparation process of the diode shown in FIG. 4A. A difference is that when the diode shown in FIG. 5 is prepared, duration of push knot processing performed on the region 120 is greater than duration of push knot processing performed on the region 110, so that a junction depth of the region 120 is greater than a junction depth of the region 110.

[0091] Therefore, the diode shown in FIG. 5 may be prepared.

[0092] In addition, the foregoing describes only an example of a preparation process of the diode shown in FIG. 5, and does not constitute a limitation. In another embodiment, the diode shown in FIG. 5 may be prepared by using another process. Details are not described herein again.

[0093] Referring to FIG. 6A and FIG. 6B, an embodiment of this application further provides a diode. The diode includes an electrode layer 200, and a drift layer 300 disposed on one side of the electrode layer 200. The drift layer 300 includes an active region 310 and a terminal region 320. The terminal region 320 surrounds the active region 310. An electrode layer 100 is disposed at an upper portion of the active region 310. The electrode layer 100 may be divided into a region 110 and a region 120. The region 120 surrounds the region 110. An insulation trench 130 is disposed between the region 110 and the region 120. For example, a depth by which the region 120 extends into the active region 310 is greater than a depth by which the region 110 extends into the active region 310.

[0094] A conductor 140 is disposed at an upper portion of the region 110. The conductor 140 is in contact with the region 110, so that the region 110 may be connected to a power supply A1 through the conductor. A conductor 160 is disposed at an upper portion of the region 120. The conductor 160 is in contact with the region 110. There is a resistor 150 between the conductor 140 and the conductor 160. The conductor 160 is not directly connected to the power supply A1, but is connected to the power supply A1 through the resistor 150 and the conductor 140. Therefore, the region 120 is connected to the power supply A1 through the conductor 160, the resistor 150, and the conductor 140 sequentially.

[0095] Still referring to FIG. 6A, in some embodiments, a semiconductor layer 400 is disposed between the electrode layer 200 and the drift layer 300.

[0096] In some embodiments, at least one field limiting ring 321 is disposed at an upper portion of the terminal region 320. A field plate 323 is disposed above the field limiting ring 321. On the surface of the terminal region 320, a dielectric layer 325 is covered between adjacent field plates 323. The field plate 323 is surrounded by a field plate 324. A cut-off ring 322 is disposed at an outer edge of an upper portion of the terminal region 320.

[0097] For specific implementations and functions of the components in the diode shown in FIG. 6A, reference may be made to the foregoing descriptions of the diode shown in FIG. 4A or FIG. 5.

[0098] Different from the diode shown in FIG. 4A, in the diode shown in FIG. 6A, the region 110 includes a plurality of regions 111, and two adjacent regions 111 in the plurality of regions 111 are separated by an insulation trench 170. In addition, as shown in FIG. 6A, a depth by which the insulation trench 170 extends into the active region 310 is greater than a depth by which the region 111 extends into the active region 310. In this way, when the diode is in an on state, the insulation trench 170 may block or slow down migration of carriers in the region 111 to the terminal region 320, thereby reducing a quantity of carriers in the terminal region 320. Therefore, when the diode is off, a quantity of carriers that are extracted through the region 120 is also small, thereby further reducing current density of the region 120, suppressing heat generation, reducing a risk that the diode is burned, and improving reliability of the diode.

[0099] In addition, the diode shown in FIG. 6A may be prepared with reference to a preparation process of the diode shown in FIG. 4A. A difference is that when the diode shown in FIG. 6A is prepared, the insulation trench 170 is also prepared while the insulation trench 130 is prepared, so as to divide the region 110 into a plurality of regions 111. A preparation process of the insulation trench 170 is the same as that of the insulation trench 130. Details are not described herein again. In some embodiments, when the diode shown in FIG. 6A is prepared, the duration of the push-junction processing of the region 120 is greater than the duration of the push-junction processing of the region 110, so that the junction depth of the region 120 is greater than the junction depth of the region 110.

[0100] Therefore, the diode shown in FIG. 6A may be prepared.

[0101] In addition, the foregoing describes only an example of a preparation process of the diode shown in FIG. 6A, and does not constitute a limitation. In another embodiment, the diode shown in FIG. 6A may be prepared by using another process. Details are not described herein again.

[0102] Referring to FIG. 7, an embodiment of this application further provides a diode. The diode includes an electrode layer 200, and a drift layer 300 disposed on one side of the electrode layer 200. The drift layer 300 includes an active region 310 and a terminal region 320. The terminal region 320 surrounds the active region 310. An electrode layer 100 is disposed at an upper portion of the active region 310. The electrode layer 100 may be divided into a region 110 and a region 120. The region 120 surrounds the region 110. An insulation trench 130 is disposed between the region 110 and the region 120. For example, a depth by which the region 120 extends into the active region 310 is greater than a depth by which the region 110 extends into the active region 310.

[0103] A conductor 140 is disposed at an upper portion of the region 110. The conductor 140 is in contact with the region 110, so that the region 110 may be connected to a power supply A1 through the conductor. A conductor 160 is disposed at an upper portion of the region 120. The conductor 160 is in contact with the region 110. There is a resistor 150 between the conductor 140 and the conductor 160. The conductor 160 is not directly connected to the power supply A1, but is connected to the power supply A1 through the resistor 150 and the conductor 140. Therefore, the region 120 is connected to the power supply A1 through the conductor 160, the resistor 150, and the conductor 140 sequentially.

[0104] Still referring to FIG. 7, in some embodiments, a semiconductor layer 400 is disposed between the electrode layer 200 and the drift layer 300.

[0105] In some embodiments, at least one field limiting ring 321 is disposed at an upper portion of the terminal region 320. A field plate 323 is disposed above the field limiting ring 321. On the surface of the terminal region 320, a dielectric layer 325 is covered between adjacent field plates 323. The field plate 323 is surrounded by a field plate 324. A cut-off ring 322 is disposed at an outer edge of an upper portion of the terminal region 320.

[0106] For specific implementations and functions of the components in the diode shown in FIG. 7, reference may be made to the foregoing descriptions of the diode shown in FIG. 4A, FIG. 5, or FIG. 6A.

[0107] Different from the diode shown in FIG. 4A, in the diode shown in FIG. 7, a barrier layer 112 is disposed below the region 110, that is, the barrier layer 112 is disposed between the region 110 and the active region 310. Properties of an impurity doped into the barrier layer 112 and an impurity doped into the region 110 are different. Specifically, when the region 110 is doped with a P-type impurity, the barrier layer 112 is doped with an N-type impurity. When the region 110 is doped with an N-type impurity, the barrier layer 112 is doped with a P-type impurity. A property of the impurity doped into the barrier layer 112 is different from a property of the impurity doped into the region 110. In other words, a property of the impurity doped into the barrier layer 112 is the same as a property of the impurity doped into the drift layer 300. Compared with a doping concentration of the drift layer 300, a doping concentration of the barrier layer 112 is higher.

[0108] In some embodiments, as shown in FIG. 7, the region 110 includes a plurality of regions 111, and two adjacent regions 111 in the plurality of regions 111 are separated by an insulation trench 170. In addition, a barrier layer 112 is disposed below the region 111.

[0109] When the diode is in an on state, the barrier layer 112 may slow down migration of carrier in the region 111 or the region 110 to the active region 310, thereby reducing carriers diffused to the terminal region 320, and reducing a quantity of carriers in the terminal region 320. Therefore, when the diode is off, a quantity of carriers that are extracted through the region 120 is also small, thereby further reducing current density of the region 120, suppressing heat generation, reducing a risk that the diode is burned, and improving reliability of the diode.

[0110] In addition, when the diode shown in FIG. 7 is prepared, when an upper surface structure of the drift layer 300 is prepared, the barrier layer 112 may be prepared at a corresponding position of the drift layer 300 first. For example, the barrier layer 112 is prepared by an ion implantation doping process. Then, a field limiting ring 321, a cut-off ring 322, an electrode layer 100, and the like are prepared. For details, reference may be made to the foregoing descriptions of the diode preparation process shown in FIG. 4A.

[0111] In some embodiments, when the diode shown in FIG. 7 is prepared, the insulation trench 170 is also prepared while the insulation trench 130 is being prepared, so as to divide the region 110 into a plurality of regions 111.

[0112] In some embodiments, when the diode shown in FIG. 7 is prepared, the duration of the push knot processing of the region 120 is greater than the duration of the push knot processing of the region 110, so that the junction depth of the region 120 is greater than the junction depth of the region 110.

[0113] The insulation trench 130 may be prepared first. Then, by the ion implantation doping process, an impurity C1 is injected into a region in which the barrier layer 112 is located, to prepare the barrier layer 112, and an impurity C2 is injected into the region 120. Then, a region above the barrier layer 112 is etched off, and the region 110 is deposited, to prepare the region 110. Alternatively, the insulation trench 130 and the insulation trench 170 may be prepared first. Then, the impurity C1 is injected into the region in which the barrier layer 112 is located by the ion implantation doping process, to prepare the barrier layer 112, and the impurity C2 is injected into the region 120. Then, the region on the barrier layer 112 is etched off, and the region 111 is deposited, to prepare the region 111. Properties of the impurity C1 and the impurity C2 are different.

[0114] Then, in the insulation trench 130 and the insulation trench 170 and on the upper surfaces of the region 110 and the region 120, an insulator is deposited in an epitaxial growth manner. Afterwards, the insulator is etched, and a resistor is deposited in the etched insulator in an epitaxial growth manner, so as to prepare an insulation layer 131 and a resistor 150. Next, the insulator on the upper surface of the region 110 is etched off, and then the conductor 140 is prepared.

[0115] For a preparation process of another component in the diode shown in FIG. 7, reference may be made to the foregoing descriptions of the preparation process of the diode shown in FIG. 4A. Details are not described herein again.

[0116] Therefore, the diode shown in FIG. 7 may be prepared.

[0117] In addition, the foregoing describes only an example of a preparation process of the diode shown in FIG. 7, and does not constitute a limitation. In another embodiment, the diode shown in FIG. 7 may be prepared by using another process. Details are not described herein again.

[0118] In the description of the embodiments of this application, the described specific features, structures, materials, or characteristics may be combined in a suitable manner in any one or more of the embodiments or examples.

[0119] It may be understood that in the descriptions of the embodiments of this application, words such as “exemplary”, “example”, or “for example” are used to represent giving an example, an illustration, or a description. Any embodiment or design scheme described by “exemplary”, “example” or “for example” in embodiments of this application should not be explained as being more preferred or having more advantages than another embodiment or design scheme. To be precise, the words such as “exemplary”, “example”, or “for example” are intended to present a related concept in a specific manner.

[0120] In the descriptions of the embodiments of this application, the term “and/or” describes only an association relationship for describing associated objects and represents that three relationships may exist. For example, A and/or B may represent the following three cases: only A exists, only B exists, and both A and B exist. In addition, unless otherwise specified, the term “a plurality of” means two or more. For example, a plurality of systems refer to two or more systems, and a plurality of terminals refer to two or more terminals.

[0121] In addition, the terms “first” and “second” are merely intended for a purpose of description, and shall not be understood as an indication or implication of relative importance or implicit indication of serial numbers of indicated technical features. Therefore, a feature limited by “first” or “second” may explicitly or implicitly include one or more features. The terms “include”, “comprise”, “have” and their variants mean “including but not limited to” unless specifically emphasized otherwise.

[0122] It can be understood that, the foregoing embodiments are merely intended for describing the technical solutions of this application, but for limiting this application. Although this application is described in detail with reference to the foregoing embodiments, a person of ordinary skill in the art should understand that modifications to the technical solutions recorded in the foregoing embodiments or equivalent replacements to some technical features thereof may still be made, without departing from the scope of the technical solutions of embodiments of this application.

[0123] The foregoing descriptions are merely specific implementations of this application, but are not intended to limit the protection scope of this application. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in the present invention shall fall within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.