ENCODER APPARATUS

Abstract

An incremental encoder apparatus including: a scale including a series of periodic features defining an optical incremental scale, and at least one magnetic reference mark; and a readhead. The readhead includes at least one incremental sensor configured to detect light from the optical incremental scale and to output at least one signal dependent thereon, and at least two analogue Hall sensors, each including at least two output terminal pairs, and each configured to switch repeatedly between each output terminal pair so as to reduce any inherent offset in the output of the analogue Hall sensor. The apparatus is configured to determine the presence of the reference mark from the outputs of the at least two analogue Hall sensors.

Claims

1. An incremental encoder apparatus comprising: a scale comprising a series of periodic features defining an optical incremental scale, and at least one magnetic reference mark; and a readhead comprising: at least one incremental sensor configured to detect light from the optical incremental scale and to output at least one signal dependent thereon, and at least two analogue Hall sensors, each comprising at least two output terminal pairs, and each configured to switch repeatedly between each output terminal pair so as to reduce any inherent offset in the output of the analogue Hall sensor, in which the apparatus is configured to generate a reference mark signal from the outputs of the at least two analogue Hall sensors.

2. An incremental encoder apparatus as claimed in claim 1, in which the apparatus is configured to determine a difference signal which is proportional to the difference of the outputs of the two analogue Hall sensors, and in which the apparatus is configured to generate a reference mark signal using said difference signal.

3. An incremental encoder apparatus as claimed in claim 2, in which the apparatus is configured to differentially amplify the outputs of the analogue Hall sensors to obtain said difference signal.

4. An incremental encoder apparatus as claimed in claim 2, in which the apparatus is configured to generate a reference mark signal in response to said signal crossing a predetermined threshold.

5. An incremental encoder apparatus as claimed in claim 1, in which the apparatus is configured to at least partially filter noise caused by said switching between the output terminal pairs.

6. An incremental encoder apparatus as claimed in claim 1, in which the apparatus is configured to at least partially filter noise having a frequency at which the switching occurs.

7. An incremental encoder apparatus as claimed in claim 1, in which the apparatus comprises a multi-pole filter configured to filter noise present in the output of the analogue Hall sensor.

8. An incremental encoder apparatus as claimed in claim 7, in which the multi-pole filter comprises at least first and second single-pole low-pass filters configured to filter noise present in the output of the analogue Hall sensor.

9. An incremental encoder apparatus as claimed in claim 1, in which the reference mark signal is repeatable to one period of the incremental scale, in at least one direction of travel.

10. An incremental encoder apparatus as claimed in claim 9, configured to generate a pair of phase-offset periodic incremental signals, and in which the reference mark signal is repeatable to ½ signal period.

11. An incremental encoder apparatus as claimed in claim 1, in which the ratio of the extent of the magnetic reference mark in the measuring dimension, to the incremental scale period is at least 50:1, optionally at least 75:1, for example at least 100:1.

12. An incremental encoder apparatus as claimed in claim 1, in which the period of the incremental scale is not greater than 50 μm.

13. An incremental encoder apparatus as claimed in claim 1, in which the extent of the magnetic reference mark in the measuring dimension is at least 0.5 mm.

14. An incremental encoder apparatus as claimed in claim 1, in which the apparatus comprises means for applying a positive phase shift to the outputs of the chopper-based Hall sensors.

15. An incremental encoder apparatus as claimed in claim 5, in which the apparatus comprises a filter comprising a zero configured to produce a positive phase shift in the filter.

16. A readhead for an encoder apparatus comprising: at least one incremental sensor configured to detect light from an optical incremental scale and to output at least one signal dependent thereon, and at least two analogue Hall sensors, each comprising at least two output terminal pairs, and each configured to switch repeatedly between each output terminal pair so as to reduce any inherent offset in the output of the analogue Hall sensor, in which the apparatus is configured to determine the presence of a magnetic reference mark from the outputs of the at least two analogue Hall sensors.

Description

[0030] Embodiments of the invention will now be described, by way of example only, with reference to the following drawings in which:

[0031] FIG. 1 is an overview diagram of an encoder according to the present invention;

[0032] FIG. 2 is a perspective view of the scale and readhead of the encoder of FIG. 1

[0033] FIGS. 3 and 4 illustrate the generation of an interference fringe;

[0034] FIG. 5 illustrates the intensity profile of an interference fringe falling on an incremental photodetector;

[0035] FIG. 6 illustrates the reference mark detectors and processing circuitry within the readhead;

[0036] FIGS. 7a and 7b illustrate signal pulses output from the sensors used to detect the reference mark, a difference signal generated therefrom, and its relationship with respect to the incremental signals;

[0037] FIGS. 8a and 8b illustrate the sensors used for detecting the magnetic reference mark in more detail;

[0038] FIG. 9 illustrates circuitry according to one embodiment which can be used for processing the output of the sensors used for detecting the magnetic reference mark to determine the presence of the reference mark;

[0039] FIG. 10 illustrates circuitry according to another embodiment which can be used for processing the output of the sensors used for detecting the magnetic reference mark to determine the presence of the reference mark; and

[0040] FIGS. 11a and 11b respectively schematically illustrate the gain frequency response (bode plots) of the circuitry of FIGS. 9 and 10.

[0041] With reference to FIGS. 1 and 2, an incremental optical encoder 2 comprises a scale 4 and a readhead 14. The scale 4 comprises an optical incremental track 6 and a magnetic reference mark track 8. The optical incremental track comprises a series of alternately spaced light reflective 10 and non-reflective 12 lines, extending in the x-direction, and spaced apart in the y-direction. The magnetic reference mark track 8 comprises at least one magnetic feature 80 forming a magnetic reference mark. As will be understood, the depicted relative sizes of the incremental features and the magnetic reference mark is schematic for ease of illustration purposes. For example, whilst it can be desirable for the reference mark to be as small as possible, practically the reference mark has to be sufficiently large to enable the reference mark detector arrangement to reliably detect the reference mark. Accordingly, especially when magnetic reference marks are used in combination with high resolution optical incremental scales, the ratio of the extent of the reference mark to the period of the incremental scale features can be quite large, for example 50:1 or higher.

[0042] The readhead 14, mounted in register with the scale 4 and offset therefrom in the z-direction, is movable relative to the scale 4 in the y-direction. The readhead 14 includes a light source (not shown) directing light toward the scale 4 which, in conjunction with light reflected from the scale 4 (and optionally one or more optical components within the readhead, such as gratings, e.g. diffraction gratings), generate a periodic light pattern in the readhead 14. Relative movement of the scale 4 and readhead 14 results in a corresponding cyclic change in a resultant field, and thereby a cyclically varying light intensity modulation (e.g. movement of the periodic light pattern such as a fringe, for example an interference fringe). A plurality of photodetectors in the readhead, generate a plurality of electrical signals corresponding to the modulating light intensity. These electrical signals are combined to generate a pair of sinusoidally varying signals Q1, Q2, having a quadrature relationship, which are outputs of respective incremental signal lines 15 and 17. Possible optical configurations for the readhead, and the generation of signals Q1, Q2 is known per se from e.g. GB1504691, WO86/03833, WO87/07944, WO01/63215, and WO2017/042570.

[0043] For instance, the readhead 14 might include a diffraction grating located so as to interact with light from the scale to produce an interference fringe at a detector in the readhead. An example of how an interference fringe could be generated is explained in more detail with reference to FIGS. 3 and 4. As will be understood,

[0044] FIG. 3 is a very simplified illustration of the actual optical situation encountered in an encoder apparatus. In particular, in FIG. 3 only one light ray from the source is illustrated whereas in fact an area of the incremental track 6 is illuminated by the light source. Accordingly, in reality the optical situation shown in FIG. 3 is repeated many times over along the length of the scale (i.e. over the area that is illuminated by the source), hence producing a long interference pattern at the detector, which is schematically illustrated in FIG. 4. Also, for illustrative purposes only the +/−1.sup.st orders are shown (e.g. as will be understood the light will be diffracted into multiple orders, e.g. +/−3.sup.rd, +/−5.sup.th, etc diffraction orders). The light is diffracted by the series of periodic features 10, 12 in the incremental track 6 of the scale 4, and the diffraction orders propagate toward the diffraction grating where the light is diffracted again before forming a resultant field (in this case an interference fringe, but could for example be modulated spot(s)) at the incremental detector. As shown in FIG. 4, the resultant field (in this case the interference fringe) 26 is produced by the recombination of diffracted orders of light from the diffraction grating and scale 4.

[0045] For the sake of simplicity of illustration the ray diagrams in FIGS. 3 and 4 are shown as transmissive ray diagrams (that is the light is shown as being transmitted through each of the scale and index grating), whereas in reality at least one of these could be reflective. For example, the rays could be reflected by the scale 6 as described above in connection with FIGS. 1 and 2.

[0046] The incremental detector 22 detects the interference fringe 26 to produce a signal which is output by the readhead 14 to an external device such as the interface 30.

[0047] In particular, relative movement of the readhead 14 and scale 4 causes movement of the interference fringes 26 relative to the incremental detector, the output of which can be processed to provide an incremental up/down count which enables an incremental measurement of displacement. For instance, as mentioned above, the readhead 14 can provide two signals in quadrature (that are 90 degrees out of phase from each other), and are commonly labelled as SIN and COS signals (even though they may not actually be sine or cosine signals), and in this case are labelled Q1 and Q2. If desired, the quadrature signals can be interpolated to provide an accurate measurement of the position of the readhead to less than one period of the repeating scale pattern. The provision of such quadrature signals by an encoder apparatus is well known in order to provide an indication of direction as well as relative movement of the readhead and scale.

[0048] In the embodiment described, the incremental detector 22 is in the form of an electrograting, which in other words is a photo-sensor array which comprises two or more sets of interdigitated/interlaced/interleaved photo-sensitive sensor elements (also referred to herein as “photodetectors” or “fingers”). Each set can, for example, detect a different phase of the interference fringe 26 at the detector 22. An example of an electrograting is illustrated in FIG. 5, in which a part of an incremental detector 22 is shown, and in which the fingers/photodiodes of four sets of photodiodes (A, B, C and D) are interdigitated/interleaved to form an array of sensor elements extending along the length “L” of the sensor. The sets of photodiodes are arranged in a repeating arrangement, having a period “p” (and hence a frequency “f′ being 1/”p″). The intensity of the interference fringe as it falls on the detector 22 is schematically illustrated by the line 26.

[0049] As shown, in the embodiment described, the individual fingers/photodiodes/sensor elements extend substantially perpendicular to the length L of the incremental detector 22. Also, the individual fingers/photodiodes/sensor elements are substantially rectangular in shape. As will be understood, the invention is also applicable to other shaped and arranged sensor elements.

[0050] The output from each finger/photodiode in a set is combined to provide a single output, thereby resulting in four channel outputs: A′, B′, C′ and D′. These outputs are then used to obtain the quadrature signals Q1, Q2 (or SIN, COS). In particular, A′-C′ is used to provide a first signal (Q1) and B′-D′ is used to provide a second signal (Q2) which is 90 degrees out of phase from the first signal. Although in the specific embodiment the electrograting comprises four sets of photodiodes providing four the channels A′, B′, C′ and D′, this need not necessarily be the case. For example, the electrograting could comprise two sets of photodiodes providing just two channels A′ and B′.

[0051] The quadrature signals Q1, Q2 form the basis of an incremental count corresponding to the displacement of the readhead 14 relative to a reference position on the scale 10. Further, if desired, It is possible to resolve the movement of the readhead 14 relative to the scale 10 to within a fraction of a single cycle of the quadrature signals Q1, Q2; the signals Q1, Q2 may be thought of as generating a circular Lissajous FIG. 20 when viewed one against the other, with a single cycle of quadrature signals corresponding to one rotation about the circle. Sub-cycle resolution may thus be achieved by dividing the circle into an equal number of segments.

[0052] Attention will now turn to the readhead's magnetic reference mark detector arrangement. As illustrated in FIG. 6, the readhead's 14 magnetic reference mark detector arrangement comprises two individual magnetic reference mark sensors 60, 62 which each output a signal which changes when they pass over the reference mark 80. The signals are received by reference mark circuitry 70 which processes the output of the sensors 60, 62 in order to detect the presence of the reference mark and output a reference mark signal on output 19 to downstream electronics. This reference mark signal could be used in various ways. For example, the raw reference mark signal output from circuity 70 could be used as the datum signal for verifying the incremental count. Optionally, the reference mark signal output from circuitry 70 could be used in a subsequent process for determining the datum signal. For instance, the reference mark signal output from circuitry 70 could be used as (or to generate) a gate signal for selecting one of a series of pre-generated datum signals which occur at the same phase position once every cycle of an interpolated incremental signal (e.g. as described in more detail in WO2017203210). Either way, the reference mark signal is repeatable to a single scale period.

[0053] An overview of how the circuity 70 generates the reference mark signal will now be provided with reference to FIGS. 7a and 7b. As schematically illustrated in FIG. 7a, when each of the reference mark sensors 60, 62 pass the reference mark 80, their output changes (in this case, rises and then falls to provide a signal spike). Because the reference mark sensors 60, 62 are offset in the measuring direction, the spike/pulse in signal reported by one of the sensors lags behind the other. Their outputs are combined to determine a difference signal (“DIFF”), wherein DIFF=the output of sensor 60 minus the output of sensor 62. As shown in FIG. 7b, one way of determining the presence of the reference mark is to determine when the DIFF signal passes a threshold T level (as will be understood, a different threshold may be used for determining the reference mark when the readhead is moving in the other direction). The occurrence of this event can be signalled to downstream electronics by changing the voltage on the output 19 (e.g. from low to high as schematically illustrated by line 58 in FIG. 7b). When the downstream electronics (which may or may not be within the readhead 14) (e.g. an interpolator/interface) receives said transition on the voltage on the output 19, it then can use the reference mark signal as desired. For example, in one embodiment it can cause a reference mark gating signal to be generated the next time the Lissajous of the Q1 and Q2 signals is between 0° and 90° (as schematically illustrated by the gating signal 59 in FIG. 7b). In an alternative embodiment, a pair of thresholds can be used, and the reference mark signal could comprise pulling the voltage on the output 19 high (or low) when the difference signal is between the pair of thresholds. Again, such a signal could itself be output to a controller as a reference mark signal, or it could be used in other ways; for example, to gate one of a series of pre-generated datum signals which occur at the same phase position once every cycle of an interpolated incremental signal.

[0054] As shown in FIG. 8a, each reference mark sensor 60, 62, comprises an analogue Hall sensor 61, 63, and processor/circuitry 64, 65 configured to process the output of the Hall sensor in order to provide a signal proportional to the magnetic field across the Hall sensor. Each analogue Hall sensor has four terminals, a, b, c and d. When the analogue Hall sensor passes over the reference mark 80, there is a change in the voltage across the Hall sensor, Accordingly, the voltage across a diametrically opposed pair of terminals (e.g. a & c) can be monitored to determine the presence of the reference mark. However, in order to minimise the adverse effects of offset voltages, and drift (e.g. due to temperature variations, strain, etc), it is known to periodically switch between the pairs of the analogue Hall sensor used for the supply and output. For example, as shown in FIG. 8a, terminal pair a and c is used for the output and terminal pair b and d are used for the supply, but this can be switched such that, as shown in FIG. 8b, terminal pair a and c is used for the supply and terminal pair b and d are used for the output. The frequency of such switching is typically at least 50 kHz, is normally in the order of hundreds of kHz, and for example in this embodiment is approximately 200 kHz. Such chopper-based analogue Hall sensors are known, and for example are available from Allegro MicroSystems L.L.0 and are described, for instance, in their patent U.S. Pat. No. 5,621,319.

[0055] As will be understood, in order for a reference mark to function as a good reference mark, it is important that the reference mark signal generated therefrom is always issued at the same point along the scale. In particular, it is desirable that the reference mark signal is repeatable to one unit resolution of the incremental system. For example, it is desirable for the reference mark signal to always be issued at the same count position. However, it has been found that this is difficult to achieve when using such chopper-based analogue Hall sensors. In particular, whilst such chopper-based analogue Hall sensors can be useful for minimising the adverse effects of any offset voltage and any drift issues, it has been found that the outputs of such sensors can be noisy due to the chopping/switching, and such “chopper/switching noise” can he sufficiently high so as affect the repeatability of the reference mark signal. This appears to be compounded by virtue of the reference mark signal being derived from the outputs of two chopper-based analogue Hall sensors, in particular being derived from the difference of the outputs of two chopper-based analogue Hall. This is because in some instances the chopper/switching noise constructively interferes and at other times destructively interferes, which in turn can significantly shift the position at which the OFF signal crosses the threshold.

[0056] In instances in which such chopper/switching noise does adversely affect the repeatability of the reference mark signal, it has been found that the circuitry 70 can be configured to at least partially filter such chopper/switching noise, so as to thereby improve the repeatability of the reference mark signal. One such arrangement is illustrated in FIG. 9. Here, the circuitry 70 comprises a filtered differential amplifier 72, a further filter 74, and a comparator 76. The outputs from each of the reference mark sensors 60, 62 are fed to the filtered differential amplifier to obtain the DIFF signal. This DIFF signal is filtered by the filter 74 before being analysed by the comparator 76 to determine if it has passed the threshold T. If so, then the signal on output 19 is raised to indicate that the reference mark has been detected.

[0057] As shown, in FIG. 9, the filtered differential amplifier 72. comprises “first” 91 and “second” 93 resistors, a differential amplifier 90 having inputs from the first 60 and second 62 chopper-based analogue Hall sensors, and also first and second RC (resistor-capacitor) filters, (the first RC filter comprising a “third” resistor 92 and a “first” capacitor 94 and the second RC filter comprising a “fourth” resistor 96 and a “second” capacitor 98). The ratio of the “third” resistor 92 to the “first” resistor 91 and the ratio of the “fourth” resistor 96 to the “second” resistor 9:3 sets the gain of the differential amplifier. The resistors 92, 96 and capacitors 94, 98 of the first and second RC filters are configured so as to act as a first single-pole low-pass filter. The combination of the “third” resistor 92 and the “first” capacitor 94, and of the “fourth” resistor 96 and the “second” capacitor “98” set the filter breakpoint. As also illustrated in FIG. 9, the RC filter 74 comprises a resistor 77 and a capacitor 78, configured so as to act as a second single-pole low-pass filter. Together, the first and second single-pole filters, effectively provide a multi-pole filter (arrangement/circuitry). The effect of these two poles on the gain of the differential amplifier 72 is schematically illustrated in FIG. 11a.

[0058] As will be understood, other ways of providing a multi-pole filter (arrangement/circuitry) include providing a single two-pole low-pass filter. Preferably, the break point (also known as the break frequency) of the poles is at least within an order of magnitude of each other, and ideally are substantially the same. The use of a multi-pole filter (arrangement/circuitry) has been found to be particularly beneficial in filtering out the chopper-noise because it helps to maximise the break point frequency so as to reduce circuit delay, so as to in turn maximise the speed at which the reference mark is repeatable. For example, the present inventors have found that even when using chopper-based Hall sensors, they are able to achieve repeatability of the reference mark up to speeds of 0.125 m/s (metres per second), in a system having an incremental scale pitch of 20 μm (microns) and with a magnetic reference mark having an extent of 2 mm (millimetres) in the measuring direction of the scale, and they are able to achieve repeatability of the reference mark up to speeds of 0.25 m/s, in a system having an incremental scale pitch of 40 μm (microns) and with a magnetic reference mark having an extent of 2 mm in the measuring direction of the scale.

[0059] The inventors found that the chopper-based analogue Hall sensors have an inherent operating bandwidth which introduces a negative phase shift into the Hall sensor outputs, which worsens with increasing operating speeds (of the readhead and scale). A negative phase shift is also introduced by the filtering arrangement of FIG. 9. This negative phase shift results in the position of the reference mark output shifting relative to the COS and SIN incremental signals. This can prevent the reference mark being repeatable to within one unit of resolution, especially at higher operating speeds.

[0060] Referring to FIG. 10, there is shown a circuit, similar to that of FIG. 9 (and like parts share like reference numerals), but which has been configured to create a positive phase shift, so as to cancel out the effect of the negative phase shift from the analogue Hall sensors. This produces a reference mark output that has significantly better repeatability and higher operating speeds.

[0061] As shown, similar to the embodiment of FIG. 9, the circuit comprises first and second RC (resistor-capacitor) filters, (the first RC filter comprising the “third” resistor 92 and the “first” capacitor 94 and the second RC filter comprising the “fourth” resistor 96 and the “second” capacitor 98). These form the main low pass filter element and set the filter break point. In other words the resistors 92, 96 and capacitors 94, 98 of the first and second RC filters are configured so as to act as a single-pole low-pass filter.

[0062] In contrast to the embodiment of FIG. 9, additional RC filters are located in-line between the analogue Hall sensors 60, 62 and the differential amplifier 90. In particular, as shown, one RC filter (comprising a resistor 100 and capacitor 99) is located in-line between the first analogue Hall sensor 60 and the differential amplifier 90. Also, another RC filter (comprising a resistor 101 and capacitor 102) is located in-line between the second analogue Hall sensor 62 and the differential amplifier 90. These additional RC-filters are configured to introduce a single zero and another pole into the system. The zero produces a positive phase shift in the filter, which cancels out the effect of the negative phase shift inherent to the Hall sensors and the filtering electronics. FIG. 11b schematically illustrates the effect the arrangement of FIG. 10 can have on the gain of the differential amplifier 72′. As shown, the gain rises at the zero, flattens off at the first pole, and drops at the second pole.

[0063] The ratio of the resistors 92 to (91+100) and also 96 to (93+101) set the DC gain of the differential amplifier.

[0064] It can be preferred that the resistance of resistors 91 and 93 are the same, the resistance of resistors 100 and 101 are the same, and the capacitance of capacitors 99 and 102 are the same, so that the effect on the outputs of the first 60 and second 62 Hall sensors are the same. However, as will be understood, this need not necessarily be the case.

[0065] As will be understood, the resistance of the resistors 91, 92, 93, 96, 100 and 101, and the capacitance of the capacitors 94, 98, 99 and 102, will be selected depending on the particular requirements of the encoder, and for instance on the desired zero and pole frequencies. For example, the pole frequencies for the arrangement of FIG. 9 (and FIG. 11a) can be determined as follows:

[00001]$\begin{array}{cc}\mathrm{Pole}1\mathrm{frequency}\left(\mathrm{Hz}\right)=\frac{1}{2\pi .Math.C94.Math.R92}=\frac{1}{2\pi .Math.C98.Math.R96}& \left(1\right)\\ \mathrm{Pole}2\mathrm{frequency}\left(\mathrm{Hz}\right)=\frac{1}{2\pi .Math.C78.Math.R77}& \left(2\right)\end{array}$

[0066] (where: C78=capacitor 78; C94=capacitor 94; C98=capacitor 98; R77=resistor 77; R92=resistor 92; R96=resistor 96).

[0067] Also, the zero and pole frequencies for the arrangement of FIG. 10 (and FIG. 11b) can be determined as follows:

[00002]$\begin{array}{cc}\mathrm{Zero}\mathrm{frequency}\left(\mathrm{Hz}\right)=\frac{1}{2\pi .Math.C99.Math.R100}=\frac{1}{2\pi .Math.C102.Math.R101}& \left(3\right)\\ \mathrm{Pole}1\mathrm{frequency}\left(\mathrm{Hz}\right)=\frac{1}{2\pi }\left(\frac{1}{C99.Math.R100}+\frac{1}{C99.Math.R91}\right)=\frac{1}{2\pi }\left(\frac{1}{C102.Math.R101}+\frac{1}{C102.Math.R93}\right)& \left(4\right)\\ \mathrm{Pole}2\mathrm{frequency}\left(\mathrm{Hz}\right)=\frac{1}{2\pi .Math.C94.Math.R92}=\frac{1}{2\pi .Math.C98.Math.R96}& \left(5\right)\end{array}$

[0068] (where: C94=capacitor 94; C98=capacitor 98; C99=capacitor 99; C102=, capacitor 102; R91=resistor 91; R92=resistor 92; R93=resistor 93; R96=resistor 96; R100=resistor 100; R101=resistor 101).

[0069] It should be noted that an advantage of the design of FIG. 10 is that the main low pass filter provided by the first and second RC (resistor-capacitor) filters can have a lower cut off frequency, thus filtering out more chopper noise compared to the design of FIG. 9, because the delay/phase shift can be compensated by the introduction of the zero into the filter (arrangement/circuitry).

[0070] In the embodiment of FIG. 10, the differential amplifier circuitry 72 does not comprise the RC filter 74 located after the differential amplifier 90 that was present in the embodiment of FIG. 9. However, such an additional differential amplifier could be included if desired.

[0071] In the above described embodiments, the incremental detector is located on the same side of the scale as the light source used to illuminate the scale (and so it is what is commonly referred to as a reflective system). However, it will be understood that other arrangements are possible. For example, at least the incremental detector could be located on a side of the scale opposite to the light source used to illuminate the scale (and so could be what is commonly referred to as a transmissive system).