Advanced gate drivers for silicon carbide bipolar junction transistors

Abstract

A gate driver circuit comprises a sensor, an amplifier, a regulator and a gate driver. The sensor is configured to sense a collector-emitter voltage and includes a first resistor and a second resistor connected in series, a high voltage diode connected between the series connected first and second resistors and a first capacitor connected parallel to the second resistor. The amplifier is configured to amplify a sensor output voltage and includes a non-inverting operational amplifier controlled by means of a plurality of resistors, a voltage follower connected to an output terminal of the non-inverting operational amplifier through a first diode and a third resistor connected across the first diode and the voltage follower. The regulator is configured to regulate a regulator output voltage based on an amplifier voltage. The gate driver is configured to connect/disconnect the regulator output voltage to the base terminal of the BJT.

Claims

1. A gate driver circuit, comprising: a sensor connected between a collector terminal and an emitter terminal of a bipolar junction transistor (BJT), the sensor configured to sense and measure a collector-emitter voltage V.sub.CE; a regulator connected to an amplifier having an amplifier output voltage and configured to regulate a regulator output voltage based on the amplifier output voltage; and a gate driver connected to a regulator output terminal of the regulator and configured to connect/disconnect the regulator output voltage to a base terminal of the BJT; wherein the output voltage of the regulator is controlled by an inductor and a capacitor connected at the regulator output terminal.

2. The gate driver circuit of claim 1 wherein the sensor comprises a first resistor and a second resistor connected in series, a high voltage diode with an anode connected between the series connected first and second resistors and the cathode connected to the collector terminal of the BJT and a first capacitor connected parallel to the second resistor.

3. The gate driver circuit of claim 1 wherein the amplifier comprises a non-inverting operational amplifier controlled by means of a plurality of resistors, a voltage follower connected to an output terminal of the non-inverting operational amplifier by means of a first diode and a third resistor connected across the voltage follower and the first diode configured to provide the output of the amplifier.

4. The gate driver circuit of claim 1 wherein the output voltage of the regulator is controlled by an inductor and a capacitor connected at a regulator output terminal.

5. The gate driver circuit of claim 1 wherein the sensor is a high voltage decoupling diode.

6. The gate driver circuit of claim 1 wherein the sensor is a Zener diode voltage clamp.

7. The gate driver circuit of claim 1 wherein the sensor is configured to measure the collector-emitter voltage V.sub.CE during the ON state of the BJT.

8. The gate driver circuit of claim 1 wherein a high voltage decoupling diode protects the circuitry comprising the amplifier and the regulator, from high voltage during the OFF state of the BJT.

9. The gate driver circuit of claim 1 wherein the sensor output voltage is proportional to the collector current of the BJT with an additional offset.

10. The gate driver circuit of claim 1 wherein the amplifier output is used as a voltage reference to the regulator.

11. The gate driver circuit of claim 1 wherein the regulator is a synchronous buck converter.

12. The gate driver circuit of claim 1 wherein the regulator provides voltage to the gate driver to provide a continuous supply of base current to maintain the BJT in ON state with minimal conduction losses.

13. The gate driver circuit of claim 12 wherein the gate driver optimizes the base current based on the collector-emitter voltage by adjusting the supply voltage of the gate driver thereby minimizing the power consumption.

14. The gate driver circuit of claim 12 wherein the gate driver output voltage is adjusted during the conducting state of the BJT.

15. The gate driver circuit of claim 12 wherein the gate driver optimizes the base current by monitoring the effect of temperature on the DC current gain.

16. A gate driver circuit for a Silicon Carbide Bipolar Junction Transistor (SiC BJT), comprising: a sensor connected between a collector terminal and an emitter terminal of the SiC BJT and configured to sense and measure a collector-emitter voltage V.sub.CE, the sensor having a first resistor and a second resistor connected in series, a high voltage diode with an anode connected between the series connected first and second resistors and the cathode connected to the collector terminal of the SiC BJT and a first capacitor connected parallel to the second resistor; a regulator connected to an amplifier having an amplifier voltage and configured to regulate a regulator output voltage based on the amplifier voltage; and a gate driver connected to the regulator output terminal of the regulator and configured to provide an instantaneous base current based on the collector-emitter voltage of the SiC BJT; whereby the regulator regulates the voltage of the gate driver to generate the instantaneous proportional base current based on the collector-emitter voltage and monitor the effect of temperature on the DC current gain during the conducting state of the SiC BJT thereby minimizing the driver losses.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Elements in the figures have not necessarily been drawn to scale in order to enhance their clarity and improve understanding of these various elements and embodiments of the invention. Furthermore, elements that are known to be common and well understood to those in the industry are not depicted in order to provide a clear view of the various embodiments of the invention, thus the drawings are generalized in form in the interest of clarity and conciseness.

(2) FIG. 1 illustrates a block diagram of a gate driver circuit of a silicon carbide bipolar junction transistor (SiC BJT) in accordance with the preferred embodiment of the present invention;

(3) FIG. 2 illustrates a circuit diagram of the gate driver circuit of the SiC BJT in accordance with the preferred embodiment of the present invention;

(4) FIG. 3 illustrates a block diagram of the gate driver circuit of the SiC BJT in accordance with one embodiment of the present invention;

(5) FIG. 4 illustrates a graph illustrating the waveforms generated at different stages of the gate driver circuit of the SiC BJT in accordance with an exemplary embodiment of the present invention;

(6) FIG. 5 illustrates graphs that show the reduction of the driver power consumption with respect to the output power of the converter of the present gate driver circuit and different existing gate drivers in accordance with the exemplary embodiment of the present invention; and

(7) FIG. 6 illustrates a flowchart of a method for optimizing the base current of the SiC BJT utilizing the gate driver circuit in accordance with the preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

(8) In the following discussion that addresses a number of embodiments and applications of the present invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and changes may be made without departing from the scope of the present invention.

(9) Various inventive features are described below that can each be used independently of one another or in combination with other features. However, any single inventive feature may not address any of the problems discussed above or only address one of the problems discussed above. Further, one or more of the problems discussed above may not be fully addressed by any of the features described below.

(10) As used herein, the singular forms “a”, “an” and “the” include plural referents unless the context clearly dictates otherwise. “And” as used herein is interchangeably used with “or” unless expressly stated otherwise. As used herein, the term ‘about” means +/−5% of the recited parameter. All embodiments of any aspect of the invention can be used in combination, unless the context clearly dictates otherwise.

(11) Unless the context clearly requires otherwise, throughout the description and the claims, the words ‘comprise’, ‘comprising’, and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to”. Words using the singular or plural number also include the plural and singular number, respectively. Additionally, the words “herein,” “wherein”, “whereas”, “above,” and “below” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of the application.

(12) The description of embodiments of the disclosure is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. While the specific embodiments of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

(13) Referring to FIGS. 1-2, a block diagram and a circuit diagram of a gate driver circuit 100 of a silicon carbide bipolar junction transistor (SiC BJT) 102 in accordance with the preferred embodiment of the present invention are illustrated respectively. SiC BJTs have very low specific on-resistance and offer high temperature operation due to the lack of gate oxide. This makes them very suitable for power switches and for applications with high power densities. A continuous supply of base current I.sub.B is needed to maintain the SiC BJT in the ON state. The gate driver circuit 100 of the present embodiment provides the continuous base current Is based on the collector-emitter voltage V.sub.CE of the SiC BJT 102. The present invention provides a proportional base current driver circuit 100 that adjusts the base current I.sub.b to the instantaneous collector current I.sub.C by estimating the collector-emitter voltage V.sub.CE and at the same time monitoring the effect of temperature on the DC current gain.

(14) The collector-emitter voltage V.sub.CE drop across the BJT 102 during the ON state is used to estimate the collector current I.sub.C, rather than measuring the current directly. Hence, the collector-emitter voltage V.sub.CE measurement is used to determine the required base current I.sub.b to drive the SiC BJT 102. As the operating temperature of the BJT 102 increases, the amount of t h e base current Is required for the same collector current increases, because the DC current gain decreases with temperature. Moreover, the on-resistance of SiC BJTs also increases with temperature, which for the same collector current I.sub.C results in a higher collector-emitter voltage drop. This increase in the voltage drop compensates for the decrease of the DC current gain, which offers the possibility of accomplishing temperature-sensitivity without measuring the temperature.

(15) The gate driver circuit 100 of the present embodiment comprises a sensor 110 connected across a collector terminal 104 and an emitter terminal 106 of the BJT 102, an amplifier 122, a regulator 134 and a gate driver 144 connected to a base terminal 108 of the BJT 102. The sensor 110 is configured to sense and measure a collector-emitter voltage V.sub.CE across the collector terminal 104 and the emitter terminal 106 during the ON state of the BJT 102. The sensor 110 comprises a first resistor 112 and a second resistor 114 connected in series, a high voltage diode 116 with an anode 152 connected between the series connected first and second resistors 112, 114 and the cathode 154 connected to the collector terminal 104 of the BJT 102 and a first capacitor 118 connected parallel to the second resistor 114. The sensor 110 can, preferably, be a high voltage decoupling diode. In one embodiment, the sensor 110 is a Zener diode voltage clamp. The sensor 110 provides a sensor output voltage V.sub.m based on the measured collector-emitter voltage V.sub.CE. The sensor 110 detects changes in the temperature of the BJT via its on-state resistance. The amplifier 122 is connected to a sensor output terminal 120 and is configured to amplify the sensor output voltage V.sub.m. The measured values of the sensor output V.sub.m indicates that with the increase in the collector current I.sub.C, the sensor output V.sub.m is also increased. Thus, the sensor output voltage V.sub.m is proportional to the collector-emitter voltage V.sub.CE which in turn is proportional to the collector current I.sub.C of the BJT 102 with an additional offset.

(16) The high voltage decoupling diode 116 protects the circuitry comprising the amplifier and the regulator, from high voltage during the OFF state of the BJT 102. The sensor 110 of the present embodiment senses the collector current I.sub.C by measuring the collector-emitter voltage V.sub.CE and thus eliminates the need for the high bandwidth current sensors and the digital signal processors otherwise required to process collector current I.sub.C.

(17) In some other embodiments, sensors such as resistive voltage divider, Zener limiting diode and low voltage MOSFET may be used.

(18) The amplifier 122 comprises a non-inverting operational amplifier 124 controlled by means of a plurality of resistors 126, a voltage follower 128 connected to the output of the non-inverting operational amplifier 128 by means of a first diode 130 and a third resistor 132 connected across the first diode 130 and the voltage follower 128. The amplifier 122 is selected to provide high gain, good noise immunity and with the ability to modify gain depending on the requirement of the base current Is based on collector-emitter voltage V.sub.CE. The amplifier 122 amplifies the sensor output voltage V.sub.m to provide an amplifier output voltage V.sub.ref. The regulator 134 is connected to an amplifier output terminal 140. The regulator 134 is configured to regulate a regulator output voltage V.sub.cc based on the amplifier output voltage V.sub.ref. The regulator 134, for example, is a non-isolated synchronous buck converter. The amplifier output voltage V.sub.ref is used as a voltage reference for the regulator 134. The gate driver 144 is connected to a regulator output terminal 142 and is configured to connect/disconnect the regulator output voltage V.sub.cc to the base terminal of the BJT. With the regulator output voltage V.sub.cc, the gate signals are generated internally in accordance with the amplifier output voltage V.sub.ref. The regulator 134 regulates the voltage of the gate driver 144 to generate the instantaneous proportional base current Is based on the collector-emitter voltage V.sub.CE during the conducting state of the BJT 102 and thereby minimizing the driver losses.

(19) The power losses during the conduction state of the BJT 102 are determined by the collector current I.sub.C and the On-resistance. The power losses generated in the gate driver 144 can be calculated with base current I.sub.B, the base-emitter saturation voltage (V.sub.BE(sat)), the internal base resistance (R.sub.Bint), the external base resistance (R.sub.Bext) and the driver resistance (R.sub.driver).

(20) A Pulse width modulated (PWM) signal 146 is used for controlling the gate driver 144 output. The regulator 134 provides voltage supply to the gate driver 144 to provide the continuous supply of base current Is to maintain the BJT 102 in ON state with minimal conduction losses. The regulator 134, for example, can be an integrated circuit (IC) with a synchronous buck converter inside (LTC3600). Thus, the gate driver circuit 100 of the present invention optimizes the base current I.sub.B based on the collector-emitter voltage V.sub.CE by adjusting the voltage applied to the gate driver 144 by the regulator 134. The output voltage of the regulator 134 is controlled by an inductor 136 and a capacitor 138 connected to the regulator output terminal 142. The gate driver 144 output voltage is adjusted during the conducting state of the BJT 102. Thus, the operation of the present invention includes the flow of collector current I.sub.C through the BJT that results in a voltage drop across the collector-emitter terminals V.sub.CE, which is measured by the sensor 110. The output of the sensor V.sub.m is conditioned with the amplifier 122 that generates the amplifier output V.sub.ref for the regulator 134. The regulator 134 buffers the amplifier output V.sub.ref to output the voltage V.sub.cc that causes the gate driver 144 to generate the required base current Is to flow through the BJT 102 to keep it in ON state. Output voltage of the regulator 134 is dependent on the temperature of the SiC BJT 102. The gate driver 144 optimizes the base current by monitoring the effect of temperature on the DC current gain of the BJT.

(21) FIG. 3 illustrates a block diagram of the gate driver circuit 100 of the SiC BJT 102 employing an isolated regulator 150. In this embodiment of the present invention, an isolated regulator topology is utilized. The collector-emitter voltage V.sub.CE of the BJT 102 is measured by the sensor 110 and provided to the amplifier 122 which amplifies the sensor output voltage as illustrated in FIG. 1. In this embodiment, the amplified amplifier output voltage is then applied to the isolated regulator 150. The isolated regulator 150 of this embodiment is based on Flyback, Push-Pull, Half/full-Bridge, etc. The isolated regulator 150 is combined with an opto-coupler 148, digital isolator or pulse transformer, for the PWM 146 signal. This embodiment illustrates the gate driver circuit with the isolated regulator for a universal high/low side driver.

(22) FIG. 4 illustrates a graph illustrating the waveforms generated at different stages of the gate driver circuit 100 of the SiC BJT 102 in accordance with an exemplary embodiment of the present invention. The graphs summarize experimental results of the gate driver circuit 100 of the present embodiment used to control the SiC BJT 102. In the example illustrated in FIG. 4, a Boost converter at room temperature for an output power of 1.6 kW is utilized. The pulse width modulated (PWM) control signal 146 for the SiC BJT 102 is shown as waveform P. The waveform of the regulator output voltage V.sub.cc and the regulator output current I.sub.L through the inductor 136 is illustrated by Q and R respectively. The continuous base current I.sub.B proportional to the regulator output voltage V.sub.cc is shown by the waveform S.

(23) FIG. 5 illustrates graphs depicting the driver power consumption with respect to the output power of the converter of the present gate driver circuit 100 and an existing gate driver in accordance with the exemplary embodiment of the present invention. A Boost converter was utilized for this purpose. Experiments were carried out on the existing gate driver and the gate driver circuit 100 of the present invention at room temperature. Graphs were calibrated at different output power of the Boost converter. Graphs A, B and C show the variation of the driver power consumption with respect to the output power of the Boost converter of the existing gate driver for different values of external base resistance. Graph D shows the variation of the driver power consumption with respect to the output power of the Boost converter of the gate driver circuit 100 of the present embodiment. The graphs reveal that the gate driver circuit 100 of the present embodiment reduced the driver power consumption by a factor of 4 compared to the existing gate driver.

(24) The reduction of the driver power consumption offered by embodiments of this invention is more noticeable in converters where the inductor current ripple is large (e.g., converters operated in Discontinuous Conduction Mode or Resonant Converters) and converters in applications where the operating temperature of the SiC BJT is expected to fluctuate within a large temperature window.

(25) Thus, the present invention 100 provides the proportional base current Is based on the collector-emitter voltage V.sub.CE and eliminates high bandwidth current sensors and micro-controllers. Embodiments of this invention also provide a standalone gate driver circuit that replaces other switch and driver combinations using IGBTs or MOSFETs, without any modifications at the converter level.

(26) FIG. 6 illustrates a flowchart of a method for optimizing the base current of the SiC BJT utilizing the gate driver circuit in accordance with the preferred embodiment of the present invention. The method comprises the steps of: providing the gate driver circuit having a sensor, an amplifier, a regulator and a gate driver as indicated in block 202. Sensing and measuring a collector-emitter voltage by the sensor based on a collector current during the conducting state of the BJT as indicated in block 204. As indicated in block 206, providing the measured sensor voltage to the amplifier of the gate driver circuit and generating an amplifier output voltage and providing the amplifier output voltage to the regulator and generating a regulated voltage based on the collector-emitter voltage of the BJT as indicated in block 208. Applying the regulated voltage output of the regulator to the gate driver as indicated in block 210 and optimizing the base current of the BJT based on the regulated voltage output of the regulator and the collector-emitter voltage of the BJT as indicated in block 212.

(27) The present invention provides a novel design of the gate driver circuit 100 with minimal power consumption, adjusts the base current Is to the instantaneous collector current I.sub.C by adjusting the driver voltage supply V.sub.cc, based on the effect of temperature on the DC current gain. The driver circuit 100 of the present embodiment can be implemented in any power electronics converter topology including DC/DC converters, inverters etc.

(28) Embodiments of this invention also provide a standalone driver circuit that can replace other switch plus driver combinations using IGBTs or MOSFETs, without any modifications at the converter level.

(29) The foregoing description of the preferred embodiment of the present invention has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the present invention not be limited by this detailed description, but by the claims and the equivalents to the claims appended hereto.