SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE

Abstract

A semiconductor device is provided that includes a frontside and a backside, four sidewalls, a first solder/glue connection on the frontside and a second solder/glue connection on the backside. The semiconductor device is either connected as a chip scale package to a printed circuit board or inside a semiconductor package via one of the four sidewalls, so that the first solder/glue connection and the second solder/glue connection are visible for a visual solder/glue inspection.

Claims

1. A semiconductor device comprising: a frontside and a backside; four sidewalls; and a first solder or glue connection on the frontside and a second solder or glue connection on the backside, wherein the semiconductor device is connected to a printed circuit board via one of the four sidewalls, so that the first solder or glue connection and the second solder or glue connection are visible for a visual solder or glue inspection.

2. The semiconductor device as claimed in claim 1, wherein the semiconductor device further comprises an isolating layer on the four sidewalls.

3. The semiconductor device as claimed in claim 2, wherein the isolating layer is a ceramic, parylene or equivalent coating.

4. The semiconductor device as claimed in claim 2, wherein the isolating layer is a mould.

5. An automotive part comprising a semiconductor device as claimed in claim 1.

6. An automotive part comprising a semiconductor device as claimed in claim 2.

7. An automotive part comprising a semiconductor device as claimed in claim 3.

8. An automotive part comprising a semiconductor device as claimed in claim 4.

9. A method of forming a semiconductor device as claimed in claim 1.

10. A method of forming a semiconductor device as claimed in claim 2.

11. A method of forming a semiconductor device as claimed in claim 3.

12. A method of forming a semiconductor device as claimed in claim 4.

13. A method of forming a semiconductor device as claimed in claim 4, wherein the creation of the isolating layer on the four sidewalls comprises the steps of: singulating dies; coating the semiconductor device with ceramic, parylene, or other protection layer; and opening contacts on the frontside and the backside using a bump planarization tool.

14. A method of forming a semiconductor device as claimed in claim 4, wherein the creation of the isolating layer on the four sidewalls comprises the steps of: singulating dies; overmolding the semiconductor device; opening contacts on the frontside and the backside by a grinding; and singulating the overmolded semiconductor device.

15. A method of forming a semiconductor device as claimed in claim 4, wherein the creation of the isolating layer on the four sidewalls comprises the steps of: singulating dies; coating the semiconductor device with ceramic, parylene, or other protection layer; and opening contacts on the frontside and the backside using grinding.

16. A method of forming a semiconductor device as claimed in claim 4, wherein the creation of the isolating layer on the four sidewalls comprises the steps of: singulating dies; coating the semiconductor device with ceramic, parylene, or other protection layer; and opening contacts on the frontside and the backside using etching.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] So that the manner in which the features of the present disclosure can be understood in detail, a more particular description is made with reference to embodiments, some of which are illustrated in the appended figures. It is to be noted, however, that the appended figures illustrate only typical embodiments and are therefore not to be considered limiting of its scope. The figures are for facilitating an understanding of the disclosure and thus are not necessarily drawn to scale. Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying figures, in which like reference numerals have been used to designate like elements, and in which:

[0032] FIG. 1 shows a known QFN leadframe package.

[0033] FIG. 2 illustrates a semiconductor device according to an embodiment of the disclosure.

[0034] FIG. 3 illustrates method steps for manufacturing a semiconductor device according to an embodiment of the disclosure.

[0035] FIG. 4 illustrates method steps for manufacturing a semiconductor device according to an embodiment of the disclosure.

DETAILED DESCRIPTION

[0036] According to an embodiment of the disclosure a vertical designed device, e.g. a diode, a transistor, etc., comprises a solderable/glueable backside metallization and a solderable/glueable front side contact, e.g. a copper-tin (CuSn) bump, will be coated on side walls with a protection layer.

[0037] During coating, the devices will be mounted on a carrier, e.g. dicing foil, which prevents the backside from being covered.

[0038] The frontside contacts, if not protected during coating, needs to be re-opened after coating.

[0039] Bump planarization, grinding, polishing, etching or equivalent technology can be used for this purpose.

[0040] An embodiment of the disclosure is shown in FIG. 3. In this case the device is coated by a ceramic or a parylene or a coating. The method comprises the steps: [0041] step 300: singulate dies [0042] step 302: coat devices with a protection layer, e.g. ceramic, parylene, etc. [0043] step 304: open contact using a bump planarization tool, grinder, or an equivalent technology

[0044] An embodiment of the disclosure is shown in FIG. 4. In this case a mould type side wall protection is applied. The method comprises the steps: [0045] step 306: singulate dies [0046] step 308: overmold devices [0047] step 310: open contact by a grinding, etching, laser or an equivalent technology [0048] step 312: singulate overmolded devices

[0049] According to an embodiment of the disclosure shown in FIG. 2, a semiconductor device 200 will be mounted with the sidewall to the PCB 202.

[0050] The semiconductor device 200 comprises a frontside 206, a backside 208 a first sidewall 214 and a second sidewall 216. The other two sidewalls are not visible in FIG. 2. The semiconductor device further comprises a first solder connection 210 on the frontside 206 and a second solder connection 212 on the backside 208. The semiconductor device 200 is connected to printed circuit board 202 via the first sidewall 214 or via the second sidewall 216 or via other two sidewalls that are not visible in FIG. 2. The first solder/glue connection 210 and the second solder/glue connection 212 are in this way visible, i.e. automatic optical inspection (AOI) of the solder/glue connection quality is enabled.

[0051] The semiconductor device with such a solderable/glueable side wall contact on a chip scale package allows automatic optical inspection of the solderable/glueable side wall contact. This is favourable in various applications, especially in automotive applications.

[0052] In other words, the semiconductor device is assembled on its original sidewall 214 or 216 or other two sidewalls and the frontside 206 and the backside 208 are used to place the solder/glue connections 210 and 212. The solder connections 210 and 212 are in such a semiconductor device representing side wettable flanks. I.e. that means that the semiconductor device is mounted with the angle of 90°. Such mounting allows automatic optical inspection.

[0053] In this embodiment a die area is used for DSN devices by keeping vertical current flow through silicon. It is not required to bring all contacts of a device on one plane like it is done for a conventional DSN.

[0054] The wafer thickness, instead of the die area, is generating required distance, i.e. pitch, between the contacts.

[0055] Additionally, se secure that there are no shortcuts, a four-sided protection of the sidewalls using epoxy, ceramic, parylene, etc. can be used. Thus, in such a vertical DSN semiconductor device, the solderable contacts are on the both sides of the DSN semiconductor device, while the non-contact areas are protected by an isolating layer, since it is mounted to the printed circuit board on the sidewall. Die thickness defines the terminal pitch for diodes and for transistors the collector or drain pitch to the other contacts.

[0056] Particular and preferred aspects of the disclosure are set out in the accompanying independent claims. Combinations of features from the dependent and/or independent claims may be combined as appropriate and not merely as set out in the claims.

[0057] The scope of the present disclosure includes any novel feature or combination of features disclosed therein either explicitly or implicitly or any generalisation thereof irrespective of whether or not it relates to the claimed disclosure or mitigate against any or all of the problems addressed by the present disclosure. The applicant hereby gives notice that new claims may be formulated to such features during prosecution of this application or of any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in specific combinations enumerated in the claims.

[0058] Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub combination.

[0059] The term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality. Reference signs in the claims shall not be construed as limiting the scope of the claims.