Metal oxide semiconductor field effect transistor and method of manufacturing same

Abstract

A Field Effect Transistor (FET) device and a method for manufacturing it are disclosed. The FET device contains a graphene layer, a composite gate dielectric layer disposed above the graphene layer, wherein the composite gate layer is passivated with fluorine, and a metal gate disposed above the composite gate dielectric layer. The method disclosed teaches how to manufacture the FET device.

Claims

1. A field-effect transistor comprising: a graphene layer; a composite gate dielectric layer passivated with fluorine above the graphene layer, wherein the composite gate dielectric layer comprises a SiO.sub.2 layer directly on the graphene layer, and a HfO.sub.2 layer on the SiO.sub.2 layer; and a metal gate disposed above the composite gate dielectric layer.

2. The field-effect transistor of claim 1, wherein the SiO.sub.2 layer is about 1-2 nm thick.

3. The field-effect transistor of claim 1, further comprising a substrate layer supporting the graphene layer.

4. The field-effect transistor of claim 3, further comprising a source and a drain on the substrate layer.

5. The field-effect transistor of claim 1, wherein the HfO.sub.2 layer is in direct contact with the SiO.sub.2 layer.

6. A method comprising: forming a graphene mesa from a graphene layer on a wafer; and forming a composite gate dielectric layer passivated with fluorine above the graphene mesa, wherein the composite gate dielectric layer comprises a SiO.sub.2 layer on the graphene mesa, and a HfO.sub.2 layer on the SiO.sub.2 layer.

7. The method of claim 6, further comprising applying Rapid Thermal Annealing to the graphene mesa.

8. The method of claim 6, further comprising forming one or more ohmic contacts on the wafer.

9. The method of claim 8, further comprising applying Rapid Thermal Annealing to the one or more ohmic contacts.

10. The method of claim 6, wherein the forming of the composite gate dielectric layer comprises applying fluorine plasma to the composite gate dielectric layer to passivate the composite gate dielectric layer with the fluorine.

11. The method of claim 6, further comprising forming a gate metal layer above the composite gate dielectric layer.

12. The method of claim 6, wherein the SiO.sub.2 layer is about 1-2 nm thick.

13. The method of claim 6, wherein the forming of the composite gate dielectric layer comprises depositing the HfO.sub.2 layer using an Atomic Layer Deposition (ALD) process.

14. The method of claim 6, wherein the forming of the composite gate dielectric layer comprises processing the composite gate dielectric layer with a CF.sub.4 plasma process to passivate the composite gate dielectric layer with the fluorine.

15. The method of claim 6, wherein the HfO.sub.2 layer is in direct contact with the SiO.sub.2 layer.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) FIG. 1 depicts a MOSFET according to some embodiments presently disclosed.

(2) FIG. 2a depicts Atomic Force Microscopy image of HfO.sub.2 material according to some embodiments presently disclosed.

(3) FIG. 2b depicts Scanning Electron Microscope image of HfO.sub.2 material according to some embodiments presently disclosed.

(4) FIG. 3a depicts leakage current of HfO.sub.2 material according to some embodiments presently disclosed.

(5) FIG. 3b depicts a dielectric constant of HfO.sub.2 material according to some embodiments presently disclosed.

(6) FIG. 4a depicts graphs representing I-V curve of HfO.sub.2/Graphene MOSFETs with fluorine passivation and without fluorine passivation according to some embodiments presently disclosed.

(7) FIG. 4b depicts graphs representing extrinsic gm curve of HfO.sub.2/Graphene MOSFETs with fluorine passivation and without fluorine passivation according to some embodiments presently disclosed.

(8) FIGS. 5a-e depict a process for forming a MOSFET according to some embodiments presently disclosed.

(9) In the following description, like reference numbers are used to identify like elements. Furthermore, the drawings are intended to illustrate major features of exemplary embodiments in a diagrammatic manner. The drawings are not intended to depict every feature of every implementation nor relative dimensions of the depicted elements, and are not drawn to scale.

DETAILED DESCRIPTION

(10) In the following description, numerous specific details are set forth to clearly describe various specific embodiments disclosed herein. One skilled in the art, however, will understand that the presently claimed invention may be practiced without all of the specific details discussed below. In other instances, well known features have not been described so as not to obscure the invention.

(11) In some embodiments presently disclosed, a graphene MOSFETs according to the present disclosure comprises a composite gate dielectric layer such as, for example, SiO2/HfO2. In some embodiments presently disclosed, a fluorine is implemented to passivate, for example, a stack of SiO.sub.2/HfO.sub.2 gate dielectric films using, for example, high-pressure and low-damage CF.sub.4 plasma treatment. According to some embodiments, the fluorine may bond with broken bonds within HFO.sub.2 grown by atomic layer deposition (ALD). In some embodiments presently disclosed incorporation of fluorine reduces the hysteresis and improves gm in the graphene MOSFETs.

(12) According to one aspect, a field-effect transistor is presently disclosed. The field-effect transistor comprises a graphene layer, a composite gate dielectric layer disposed above the graphene layer, wherein the composite gate layer is passivated with fluorine, and a metal gate disposed above the composite gate dielectric layer.

(13) According to another aspect, a method is presently disclosed. The method comprises forming a graphene layer, forming a graphene mesa in the graphene layer, and forming a composite gate dielectric layer above the graphene mesa.

(14) Referring to FIG. 1, a MOSFET 10 is shown according to some embodiments presently disclosed. In some embodiments presently disclosed, the MOSFET 10 comprises a substrate 15, a graphene layer 20 disposed above the substrate 15, a composite gate dielectric layer 25 disposed above the graphene layer 20, and a metal gate 30 disposed above the graphene layer 20. In some embodiments, the composite gate dielectric layer 25 comprises, for example, a stack of SiO.sub.2 and HfO.sub.2. In some embodiments, the HfO.sub.2 is deposited using Atomic Layer Deposition (ALD) process. In some embodiments, the electron-beam-assisted evaporated SiO.sub.2 is about 1-2 nm thick. In some embodiments, the metal gate 30 comprises Ti/Pt/Au, Pt/Au or Al metal gates.

(15) In some embodiments presently disclosed, the SiO.sub.2 and HfO.sub.2 gate dielectric layer 25 is processed with CF.sub.4 plasma process for fluorine incorporation before forming the gate metal 30. In some embodiments, the CF.sub.4-based fluorination process is done with CF.sub.4/O.sub.2 plasma with a ratio of, for example, 24:3. In some embodiments, the pressure was 90 milli-torr with low RF power of 50 W. In some embodiments, the CF.sub.4-based fluorination process is applied for about 5 min.

(16) Referring to FIG. 2a, Atomic Force Microscopy image of HfO.sub.2 material is shown disposed above a graphene FETs. Referring to FIG. 2b, Scanning Electron Microscope image of HfO.sub.2 material is shown disposed above a graphene FETs. Both FIGS. 2a-b show smooth coverage without cracking or pinholes. Without the SiO.sub.2 layer beneath the HFO.sub.2, the HFO.sub.2 may develop line cracks.

(17) Referring to FIGS. 3a-b, HfO.sub.2 dielectric layer 25 has negligible gate leakage current of ˜pA/um.sup.2 (shown in FIG. 3a) and a dielectric constant of about 16 (shown in FIG. 3b).

(18) FIG. 4a depicts a graph 35 representing I-V curve of HfO.sub.2/Graphene MOSFETs with fluorine passivation and depicts a graph 40 representing I-V curve of HfO.sub.2/Graphene MOSFETs without fluorine passivation. FIG. 4b depicts a graph 45 representing extrinsic gm curve of HfO.sub.2/Graphene MOSFETs with fluorine passivation and depicts a graph 50 representing extrinsic gm curve of HfO.sub.2/Graphene MOSFETs without fluorine passivation. As shown in FIGS. 4a-b, the hysteresis is greatly reduced and on-state current is improved from 1.2 A/mm to 1.8 mA/mm at Vds=1 V. The gm was improved from 200 mS/mm to 350 mS/mm at Vds=1 V.

(19) According to some embodiments presently disclosed, a process for forming a MOSFET according to the present disclosure is described with reference to FIGS. 5a-e. Referring to FIG. 5a, a graphene wafer 65 is formed using, for example, chemical vapor deposition or epitaxial deposition methods. Referring to FIG. 5b, a graphene mesa 70 is formed. In some embodiments, a 350° C. 3 minute Rapid Thermal Annealing process is applied to the graphene mesa 70. Referring to FIG. 5c, graphene ohmic contact 75 and/or 76 are formed. In some embodiments, a 350° C. 3 minute Rapid Thermal Annealing process is applied to the graphene ohmic contact 75 and/or 76. Referring to FIG. 5d, a high dielectric constant (K) gate dielectric layer 80 is deposited above the graphene mesa 70. In some embodiments, the high dielectric constant (K) gate dielectric layer 80 is treated with fluorine plasma. Referring to FIG. 5e, gate metal layer 85 is deposited above the gate dielectric layer 80.

(20) While several illustrative embodiments of the invention have been shown and described, numerous variations and alternative embodiments will occur to those skilled in the art. Such variations and alternative embodiments are contemplated, and can be made without departing from the scope of the invention as defined in the appended claims.

(21) As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. The term “plurality” includes two or more referents unless the content clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains.

(22) The foregoing detailed description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will be apparent to practitioners skilled in the art. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom. Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean “one and only one” unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for . . . ” and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase “step(s) for . . . .”