TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Abstract

A transistor structure including a substrate, a gate structure, first pocket doped regions, second pocket doped regions, and source/drain extension regions, and source/drain regions is provided. The gate structure is located on the substrate. The first pocket doped regions are located in the substrate aside the gate structure. A dopant of the first pocket doped region includes a group IVA element. The second pocket doped regions are located in the substrate aside the gate structure. A depth of the second pocket doped region is greater than a depth of the first pocket doped region. The source/drain extension regions are located in the first pocket doped regions. The source/drain regions are located in the substrate aside the gate structure. The source/drain extension region is located between the source/drain region and the gate structure.

Claims

1. A transistor structure, comprising: a substrate; a gate structure located on the substrate; first pocket doped regions located in the substrate aside the gate structure, wherein a dopant of the first pocket doped region comprises a group IVA element; second pocket doped regions located in the substrate aside the gate structure, wherein a depth of the second pocket doped region is greater than a depth of the first pocket doped region; source/drain extension regions located in the first pocket doped regions; and source/drain regions located in the substrate aside the gate structure, wherein the source/drain extension region is located between the source/drain region and the gate structure.

2. The transistor structure according to claim 1, wherein the dopant of the first pocket doped region comprises carbon or germanium.

3. The transistor structure according to claim 1, wherein the source/drain region is connected to the source/drain extension region.

4. The transistor structure according to claim 1, further comprising: first contact doped regions located in the substrate aside the gate structure, wherein the source/drain region is located in the first contact doped region, and a dopant of the first contact doped region comprises the group IVA element.

5. The transistor structure according to claim 4, further comprising: second contact doped regions located in the first contact doped regions, wherein a depth of the second contact doped region is greater than a depth of the source/drain region.

6. The transistor structure according to claim 1, further comprising: spacers located on sidewalls of the gate structure, wherein the source/drain extension region is located under the spacer.

7. A transistor structure, comprising: a substrate; a gate structure located on the substrate; source/drain regions located in the substrate aside the gate structure; and contact doped regions located in the substrate aside the gate structure, wherein the source/drain region is located in the contact doped region, and a dopant of the contact doped region comprises a group IVA element.

8. A manufacturing method of a transistor structure, comprising: providing a substrate; forming a gate structure on the substrate; forming first pocket doped regions in the substrate aside the gate structure, wherein a dopant of the first pocket doped region comprises a group IVA element; forming second pocket doped regions in the substrate aside the gate structure, wherein a depth of the second pocket doped region is greater than a depth of the first pocket doped region; forming source/drain extension regions in the first pocket doped regions; and forming source/drain regions in the substrate aside the gate structure, wherein the source/drain extension region is located between the source/drain region and the gate structure.

9. The manufacturing method of the transistor structure according to claim 8, wherein a method of forming the first pocket doped region comprises a cold implant.

10. The manufacturing method of the transistor structure according to claim 9, wherein a temperature of the cold implant is −20° C. to −100° C.

11. The manufacturing method of the transistor structure according to claim 9, wherein an implant energy of the cold implant is 5 keV to 15 keV.

12. The manufacturing method of the transistor structure according to claim 9, wherein an implant dose of the cold implant is 5×10.sup.13 atoms/cm.sup.2 to 5×10.sup.15 atoms/cm.sup.2.

13. The manufacturing method of the transistor structure according to claim 9, wherein a tilt angle of the cold implant is 3 degrees to 15 degrees.

14. The manufacturing method of the transistor structure according to claim 8, further comprising: forming first contact doped regions in the substrate aside the gate structure, wherein the source/drain region is located in the first contact doped region, and a dopant of the first contact doped region comprises the group IVA element.

15. The manufacturing method of the transistor structure according to claim 14, wherein a method of forming the first contact doped region comprises a cold implant.

16. The manufacturing method of the transistor structure according to claim 15, wherein a temperature of the cold implant is −20° C. to −100° C.

17. The manufacturing method of the transistor structure according to claim 15, wherein an implant energy of the cold implant is 10 keV to 20 keV.

18. The manufacturing method of the transistor structure according to claim 15, wherein an implant dose of the cold implant is 1×10.sup.14 atoms/cm.sup.2 to 1×10.sup.16 atoms/cm.sup.2.

19. The manufacturing method of the transistor structure according to claim 15, wherein a tilt angle of the cold implant is 0 degrees.

20. The manufacturing method of the transistor structure according to claim 14, further comprising: forming second contact doped regions in the first contact doped regions, wherein a depth of the second contact doped region is greater than a depth of the source/drain region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0028] FIG. 1A to FIG. 1F are cross-sectional views illustrating a manufacturing process of a transistor structure according to some embodiments of the invention.

DESCRIPTION OF THE EMBODIMENTS

[0029] The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the invention. For the sake of easy understanding, the same components in the following description will be denoted by the same reference symbols. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0030] FIG. 1A to FIG. 1F are cross-sectional views illustrating a manufacturing process of a transistor structure according to some embodiments of the invention.

[0031] Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate such as a silicon substrate. In some embodiments, an isolation structure 102 may be formed in substrate 100. The isolation structure 102 is, for example, a shallow trench isolation (STI) structure. The material of the isolation structure 102 is, for example, silicon oxide.

[0032] A gate structure 104 is formed on the substrate 100. The gate structure 104 may include a dielectric layer 106 and a conductive layer 108. The dielectric layer 106 is located on the substrate 100. The dielectric layer 106 can be used as a gate dielectric layer. The material of the dielectric layer 106 is, for example, silicon oxide. The conductive layer 108 is located on the dielectric layer 106. The conductive layer 108 can be used as a gate. The material of the conductive layer 108 is, for example, doped polysilicon. In some embodiments, the gate structure 104 may further include at least one of a metal silicide layer 110 and a hard mask layer 112. The metal silicide layer 110 is located on the conductive layer 108. The material of the metal silicide layer 110 is, for example, tungsten silicide (WSi). The hard mask layer 112 is located on the metal silicide layer 110. The material of the hard mask layer 112 is, for example, silicon oxide.

[0033] In some embodiments, the method of forming the dielectric layer 106, the conductive layer 108, the metal silicide layer 110, and the hard mask layer 112 may include the following steps. First, a dielectric material layer (not shown), a conductive material layer (not shown), a metal silicide material layer (not shown), and a hard mask material layer (not shown) may be sequentially formed on the substrate 100. Then, the hard mask material layer, the metal silicide material layer, the conductive material layer, and the dielectric material layer may be patterned by a lithography process and an etching process to form the hard mask layer 112, the metal silicide layer 110, and the conductive layer 108, and the dielectric layer 106.

[0034] Referring to FIG. 1B, pocket doped regions 114 are formed in the substrate 100 aside the gate structure 104. In some embodiments, the depth of the pocket doped region 114 is, for example, 170 angstroms (Å) to 300 angstroms. The dopant of the pocket doped region 114 includes a group IVA element. The dopant of pocket doped region 114 may include carbon, silicon, germanium, tin, or lead. In some embodiments, the dopant of pocket doped region 114 may be carbon or germanium. In the present embodiment, the dopant of the pocket doped region 114 is, for example, carbon, but the invention is not limited thereto. The method of forming the pocket doped region 114 may be a cold implant. Throughout the description, the term “cold implant” refers to an ion implantation process performed at low temperature. In some embodiments, the temperature of the cold implant used to form the pocket doped region 114 may be −20° C. to −100° C. In some embodiments, the implant energy of the cold implant used to form the pocket doped region 114 may be 5 keV to 15 keV. In some embodiments, the implant dose of the cold implant used to form the pocket doped region 114 may be 5×10.sup.13 atoms/cm.sup.2 to 5×10.sup.15 atoms/cm.sup.2. In some embodiments, the tilt angle of the cold implant used to form the pocket doped region 114 may be 3 degrees to 15 degrees. In some embodiments, when the dopant of the pocket doped region 114 is carbon, the gas source of the cold implant may be carbon dioxide gas (CO.sub.2 gas).

[0035] Pocket doped regions 116 are formed in the substrate 100 aside the gate structure 104. The depth of the pocket doped region 116 is greater than the depth of the pocket doped region 114. The pocket doped region 116 may have a first conductivity type (e.g., N-type conductivity type). Hereinafter, the first conductivity type and the second conductivity type may be one and the other of an N-type conductivity type and a P-type conductivity type, respectively. In the present embodiment, the first conductivity type is, for example, an N-type conductivity type, and the second conductivity type is, for example, a P-type conductivity type, but the invention is not limited thereto. In other embodiments, the first conductivity type may be a P-type conductivity type, and the second conductivity type may be an N-type conductivity type. In the present embodiment, the pocket doped region 116 may have the N-type conductivity type, and the dopant of the pocket doped region 116 is, for example, arsenic (As). The method of forming the pocket doped region 116 is, for example, an ion implantation method.

[0036] Source/drain extension regions 118 are formed in the pocket doped regions 114. In some embodiments, the source/drain extension region may be referred to as “lightly doped drain (LDD) region. The source/drain extension region 118 may have the second conductivity type (e.g., P-type conductivity type). In the present embodiment, the source/drain extension region 118 may have the P-type conductivity type, and the dopant of the source/drain extension region 118 is, for example, boron (B) or boron difluoride (BF.sub.2). The method of forming the source/drain extension region 118 is, for example, an ion implantation method.

[0037] Referring to FIG. 1C, spacers 120 may be formed on the sidewalls of the gate structure 104. The spacer 120 may be a single-layer structure or a multilayer structure. The material of the spacer 120 is, for example, silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the method of forming the spacer 120 may include the following steps. First, a spacer material layer (not shown) may be conformally formed on the substrate 100, the isolation structure 102, and the gate structure 104. Then, an etch-back process (e.g., dry etching process) is performed on the spacer material layer to form the spacer 120.

[0038] Source/drain regions 122 are formed in the substrate 100 aside the gate structure 104. The source/drain extension region 118 is located between the source/drain region 122 and the gate structure 104. The source/drain region 122 may be connected to the source/drain extension region 118. The depth of the source/drain region 122 may be greater than the depth of source/drain extension region 118. The source/drain region 122 may have the second conductivity type (e.g., P-type conductivity type). In the present embodiment, the source/drain region 122 may have the P-type conductivity type, and the dopant of the source/drain region 122 is, for example, boron (B) or boron difluoride (BF.sub.2). The method of forming the source/drain region 122 is, for example, an ion implantation method.

[0039] Referring to FIG. 1D, a dielectric layer 124 may be formed on the substrate 100, the isolation structure 102, the gate structure 104, and the spacer 120. The dielectric layer 124 may be a single-layer structure or a multilayer structure. The material of the dielectric layer 124 is, for example, silicon oxide, silicon nitride, or a combination thereof. The method of forming the dielectric layer 124 is, for example, a chemical vapor deposition method.

[0040] Referring to FIG. 1E, openings OP may be formed in the dielectric layer 124. The opening OP may expose the source/drain region 122. In some embodiments, the opening OP may be formed by removing a portion of the dielectric layer 124 by a lithography process and an etching process. In some embodiments, during the process of forming the opening OP, a portion of the source/drain region 122 may be removed.

[0041] Referring to FIG. 1F, contact doped regions 126 may be formed in the substrate 100 aside the gate structure 104. The source/drain region 122 is located in the contact doped region 126. In some embodiments, the depth of the contact doped region 126 is, for example, 250 angstroms to 400 angstroms. The dopant of the contact doped region 126 may include a group IVA element. The dopant of the contact doped region 126 may include carbon, silicon, germanium, tin, or lead. In some embodiments, the dopant of the contact doped region 126 may be carbon or germanium. In the present embodiment, the dopant of the contact doped region 126 is, for example, carbon, but the invention is not limited thereto. The method of forming the contact doped region 126 may be a cold implant. In some embodiments, the temperature of the cold implant used to form the contact doped region 126 may be −20° C. to −100° C. In some embodiments, the implant energy of the cold implant used to form the contact doped region 126 may be 10 keV to 20 keV. In some embodiments, the implant dose of the cold implant used to form the contact doped region 126 may be 1×10.sup.14 atoms/cm.sup.2 to 1×10.sup.16 atoms/cm.sup.2. In some embodiments, the tilt angle of the cold implant used to form the contact doped region 126 may be 0 degrees. In some embodiments, when the dopant of the contact doped region 126 is carbon, the gas source of the cold implant may be carbon dioxide gas.

[0042] Contact doped regions 128 may be formed in the contact doped regions 126. The depth of the contact doped region 128 may be greater than the depth of the source/drain region 122. In some embodiments, the depth of the contact doped region 128 is, for example, 100 angstroms to 200 angstroms. The contact doped region 128 may have the second conductivity type (e.g., P-type conductivity type). In the present embodiment, the contact doped region 128 may have the P-type conductivity type, and the dopant of the contact doped region 128 is, for example, boron (B) or boron difluoride (BF.sub.2). The method of forming the contact doped region 128 is, for example, an ion implantation method.

[0043] Based on the above, in the manufacturing method of the transistor structure 10 of some embodiments, the source/drain extension regions 118 are formed in the pocket doped regions 114, and the dopant of the pocket doped region 114 includes a group IVA element. Therefore, the pocket doped region 114 can suppress the dopant in the source/drain extension region 118 from diffusing, thereby effectively suppressing the short channel effect and the punch through effect and reducing the leakage current. In addition, in the manufacturing method of the transistor structure 10 of some embodiments, the contact doped regions 126 are formed in the substrate 100 aside the gate structure 104, the source/drain region 122 is located in the contact doped region 126, and the dopant of the contact doped region 126 may include a group IVA element. Therefore, the contact doped region 126 can suppress the dopant in the source/drain region 122 from diffusing, thereby effectively suppressing the short channel effect and the punch through effect and reducing the resistance value. In some embodiments, the manufacturing method of the transistor structure 10 may further include forming the contact doped regions 128 in the contact doped regions 126. Since the contact doped region 126 can suppress the dopant in the contact doped region 128 from diffusing, the short channel effect and the punch through effect can be effectively suppressed, and the resistance value can be reduced.

[0044] Hereinafter, the transistor structure 10 of the above embodiment is described with reference to FIG. 1F. In addition, although the method for forming the transistor structure 10 is described by taking the above method as an example, the invention is not limited thereto.

[0045] Referring to FIG. 1F, the transistor structure 10 includes a substrate 100, a gate structure 104, pocket doped regions 114, pocket doped regions 116, source/drain extension regions 118, and source/drain regions 122. The transistor structure 10 may be a P-type metal oxide semiconductor (PMOS) transistor structure or an N-type metal oxide semiconductor (NMOS) transistor structure. In the present embodiment, the transistor structure 10 is, for example, a PMOS transistor structure, but the invention is not limited thereto. The gate structure 104 is located on substrate 100. The pocket doped regions 114 are located in the substrate 100 aside the gate structure 104. The dopant of the pocket doped region 114 includes a group IVA element. The pocket doped regions 116 are located in the substrate 100 aside the gate structure 104. The depth of the pocket doped region 116 is greater than the depth of the pocket doped region 114. The source/drain extension regions 118 are located in pocket doped regions 114. The source/drain regions 122 are located in the substrate 100 aside the gate structure 104. The source/drain extension region 118 is located between the source/drain region 122 and the gate structure 104.

[0046] In some embodiments, the transistor structure 10 may further include contact doped regions 126. The contact doped regions 126 are located in the substrate 100 aside the gate structure 104. The source/drain region 122 may be located in the contact doped region 126.

[0047] The dopant of the contact doped region 126 may include a group IVA element. In some embodiments, the transistor structure 10 may further include contact doped regions 128. The contact doped regions 128 are located in the contact doped regions 126. The depth of the contact doped regions 128 may be greater than the depth of the source/drain regions 122. In some embodiments, the transistor structure 10 may further include spacers 120. The spacers 120 are located on the sidewalls of the gate structure 104. The source/drain extension region 118 may be located under the spacer 120.

[0048] In the above embodiment, although the transistor structure 10 includes both the pocket doped region 114 and the contact doped region 126, the invention is not limited thereto. In other embodiments, the transistor structure 10 includes the pocket doped region 114 but does not include the contact doped region 126. In other embodiments, the transistor structure includes the contact doped region 126 but does not include the pocket doped region 114.

[0049] In some embodiments, the transistor structure 10 may be applied to a complementary metal oxide semiconductor (CMOS) under array (CuA) architecture or a CMOS near array (CnA) architecture.

[0050] Furthermore, the remaining components in the transistor structure 10 may refer to the description of the above embodiments. Moreover, the details (e.g., the material and the forming method) of the components in the transistor structure 10 have been described in detail in the above embodiments, and the description thereof is not repeated here.

[0051] Based on the above, in the transistor structure 10 of some embodiments, the source/drain extension regions 118 are located in the pocket doped regions 114, and the dopant of the pocket doped region 114 includes a group IVA element. Therefore, the pocket doped region 114 can suppress the dopant in the source/drain extension region 118 from diffusing, thereby effectively suppressing the short channel effect and the punch through effect and reducing the leakage current. In the transistor structure 10 of some embodiments, the source/drain region 122 is located in the contact doped region 126, and the dopant of the contact doped region 126 includes a group IVA element. Therefore, the contact doped region 126 can suppress the dopant in the source/drain region 122 from diffusing, thereby effectively suppressing the short channel effect and the punch through effect and reducing the resistance value. In some embodiments, the transistor structure 10 may further include the contact doped regions 128, and the contact doped regions 128 are located in the contact doped regions 126. Since the contact doped region 126 can suppress the dopant in the contact doped region 128 from diffusing, the short channel effect and the punch through effect can be effectively suppressed, and the resistance value can be reduced.

[0052] In summary, in the transistor structure and the manufacturing method thereof of the aforementioned embodiments, the doped region including a group IVA element can suppress the dopant in the source/drain extension region and/or the source/drain region from diffusing, so the short channel effect can be effectively suppressed.

[0053] Although the invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention is defined by the attached claims not by the above detailed descriptions.