BACK-CONTACT SOLAR CELL, AND PRODUCTION THEREOF

Abstract

The invention relates to a method for producing a back-contact solar cell (10), and to a back-contact solar cell (10) comprising a semiconductor substrate (12), in particular a silicon wafer, comprising a front side (16) and a back side (14), the solar cell (10) comprising electrodes (36) of a first polarity and electrodes (38) of a second polarity on the back side, characterized in that that the electrodes (36) of the first polarity are located on a highly doped silicon layer (20) of the first polarity, the highly doped silicon layer (20) being located on a first passivation layer (18) located on the semiconductor substrate, and the electrodes (38) of the second polarity directly electrically and mechanically contacting the semiconductor substrate (12) via highly doped base regions (30) of the second polarity of the semiconductor substrate (12).

Claims

1.-17. (canceled)

18. A back-contact solar cell comprising a semiconductor substrate, in particular a silicon wafer, comprising a front side and a back side, the solar cell comprising electrodes of a first polarity and electrodes of a second polarity on the back side, the electrodes of the first polarity being arranged on a highly doped silicon layer of the first polarity, the highly doped silicon layer being arranged on a first passivation layer arranged on the semiconductor substrate, and the electrodes of the second polarity directly electrically and mechanically contacting the semiconductor substrate via highly doped base regions of the second polarity of the semiconductor substrate, characterized in that the highly doped base regions of the second polarity are formed within the doped base regions of the second polarity on the back side of the solar cell, a dopant concentration in the highly doped base regions being higher than a dopant concentration in the doped base regions, and the dopant concentration in the highly doped base regions being higher than a dopant concentration of a doped region on the front side of the solar cell.

19. The back-contact solar cell according to claim 18, wherein a second passivation layer is arranged on surface regions of the back side not contacted by the electrodes of the first polarity and not by the electrodes of the second polarity, the second passivation layer being thicker than the first passivation layer.

20. A method for producing a back-contact solar cell according to claim 18, a semiconductor substrate of the solar cell comprising an, in particular polished or textured, back side and an, in particular textured, front side, the method comprising the following steps: applying a first passivation layer, in particular comprising silicon dioxide, to a surface of the back side; separation of an, in particular, full-coverage, highly doped silicon layer of a first polarity to the first passivation layer on the back side; applying a dielectric layer on the back side, exposing base regions of the semiconductor substrate on the back side by locally removing the dielectric layer, and the highly doped silicon layer of the first polarity and the first passivation layer on the back side; locally removing a portion of the semiconductor substrate in the base regions; characterized in that the method a step for attaching a precursor layer comprising a dopant, in particular phosphorous, on the back side and in that by a high temperature step, in which the dopant from the precursor layer diffuses into the base regions on the back side, the doping is increased in the base regions on the back side, and in that highly doped base regions are generated by locally increasing the dopant concentration in the doped base regions on the back side.

21. The method according to claim 20, wherein the first passivation layer is also applied to a surface of the front side.

22. The method according to claim 20, wherein exposing the base regions of the semiconductor substrate on the back side comprises etching of the highly doped silicon layer of the first polarity and/or etching of the first passivation layer and/or etching of a portion of the semiconductor substrate, locally in the base regions.

23. The method according to claim 22, wherein the etching comprises isotropic etching for polishing regions, and/or the etching comprises anisotropic etching for texturing regions.

24. The method according to claim 22, wherein the step for attaching a precursor layer comprising a dopant, in particular phosphorus, on the back side, also comprises attaching the precursor layer on the front side.

25. The method according to claim 24, wherein, by means of the high-temperature step in which the dopant diffuses from the precursor layer into the base regions on the back side, the dopant from the precursor layer diffuses into the surface of the front side and a doped region is produced on the front side.

26. The method according to claim 22, wherein the highly doped base regions are produced within the doped base regions on the back side by locally increasing the dopant concentration by laser irradiation.

27. The method according to claim 22, wherein the method comprises a step of removing the precursor layer, in particular phosphorus silicate glass, from the front side and/or from the back side.

28. The method according to claim 22, wherein the method comprises a step of applying a second passivation layer on the back side and/or a third passivation layer on the front side.

29. The method according to claim 28, wherein the method comprises a step of selectively removing the second passivation layer on the back side.

30. The method according to claim 22, wherein the method comprises a step of applying electrodes of a first polarity and electrodes of a second polarity on the back side of the solar cell.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In the drawings:

[0040] FIG. 1 is a schematic view of a detail of a solar cell according to the invention, and

[0041] FIGS. 2a, 2b, 2c, 2d, 2e, 2f, 2g and 2h show a solar cell according to FIG. 1 in various steps of a method for producing the solar cell.

DETAILED DESCRIPTION

[0042] FIG. 1 shows a detail of a solar cell 10 comprising a semiconductor substrate 12, in particular a silicon wafer, a back side 14, and a front side 16 which faces the sun during operation of the solar cell. The silicon wafer 12 can be either n- or p-type doped. The solar cell 10 is explained by way of example on the basis of an n-type doping of the silicon wafer 12, of the “base”.

[0043] The front side 16 of the solar cell 10 is preferably textured. The back side 14 of the solar cell 10 can be polished or textured, in particular in different regions.

[0044] A polycrystalline highly doped p-type silicon layer 20 is provided on the back side 14. This forms a first polarity having a first doping concentration on the back side 14. In the region of the highly doped p-type silicon layer 20, a first passivation layer 18, in particular comprising silicon dioxide, passivates the surface of the silicon wafer 12. Furthermore, doped base regions 24 of a second polarity opposed to the first polarity are provided. The doped base regions 24 on the back side 14 have the same polarity but a higher dopant concentration compared with the semiconductor substrate 12.

[0045] A doped region 28 is located on the front side 16. The doped region 28 likewise has the same polarity but a higher dopant concentration compared with the semiconductor substrate 12.

[0046] Highly doped base regions 30 are formed within the doped base regions 24 on the back side. The highly doped base regions likewise have the second polarity, but a significantly higher dopant concentration than the semiconductor substrate 12, than the doped base regions 24 and than the doped region 28.

[0047] The solar cell 10 further comprises a second passivation layer 32 on the back side 14 and a third passivation layer 34 on the front side 16. The passivation layer 32 at least partially covers the highly doped silicon layer 20, the doped base regions 24 and the highly doped base regions 30, in the regions not contacted by electrodes 36, 38. The second passivation layer 32, for example formed by a dielectric layer or layer stack, preferably has a greater thickness than the first passivation layer 18, preferably a thickness of more than 4 nm. The second passivation layer 32 can consist, for example, of silicon dioxide, silicon nitride or aluminum oxide, or of a layer stack of these layers. The thicknesses and refractive indices of the passivation layer 32 can be optimized such that as much electromagnetic radiation as possible which was not absorbed by the solar cell is reflected back into the solar cell at the back side.

[0048] The third passivation layer 34 on the front side 16 preferably also has a greater thickness than the first passivation layer 18, preferably a thickness of more than 4 nm. The third passivation layer 34 can consist, for example, of silicon dioxide, silicon nitride or aluminum oxide, or of a layer stack of these layers. The thicknesses and refractive indices of the third passivation layer 34 can be optimized in such a way that as much electromagnetic radiation as possible that is incident on the front side 16 is not reflected and absorbed.

[0049] The solar cell 10 comprises, on the back side 14, electrodes 36 of a first polarity and electrodes 38 of a second polarity. The electrodes 36 of the first polarity contact the highly doped silicon layer 20 of the first polarity deposited on the first passivation layer 18. Advantageously, the electrodes 36 do not penetrate the first passivation layer 18. However, it may happen that the electrodes 36 partially penetrate the first passivation layer 18 and contact the semiconductor substrate 12. The electrodes 38 of the second polarity contacted the semiconductor substrate 12 directly electrically and mechanically in the doped base regions 24, preferably only in the highly doped regions 30 of the doped base regions 24.

[0050] Regions not contacted by the electrodes 36, 38 can either be covered and passivated by the layer stack of the first passivation layer 18 and highly doped silicon layer 20 of the first polarity, or by the second passivation layer 32 in the doped base regions 24 and highly doped base regions 30. The second passivation layer 32 can also cover the highly doped silicon layer 20 in the non-contacted regions.

[0051] Preferably, the surface electrically contacted by the electrodes 36 of the second polarity corresponds to the surfaces of the highly doped base regions 30 of the second polarity.

[0052] The production process of the solar cell 10 is explained below with reference to FIGS. 2a to 2h. FIGS. 2a to 2h illustrate the process sequence for the manufacture of a back-contact solar cell 10 having a passivated contact in the region of the highly doped silicon layer 20 and a diffused contact in the region of the highly doped base regions 30. The semiconductor substrate 12 can be n- or p-type doped, as a starting material. The process sequence is explained on the basis of an n-type doping of the wafer, of the “base”.

[0053] FIG. 2a shows the initial form of the silicon wafer 12 having a polished back side 14 and a textured front side 16. According to a further initial form (not shown), both the front and the back side can either be both polished or both textured. According to the embodiment shown, a first passivation layer 18, for example a silicon dioxide, having a thickness of preferably at most approximately 4 nm, is produced on the front side 16 and on the back side 14, for example in a thermal or wet-chemical process or by deposition. Alternatively, according to a further embodiment of the first passivation layer that is not shown, the deposition can take place only on the back side 14.

[0054] In a next step, cf. FIG. 2b, an, in particular full-surface, highly doped silicon layer 20 of a first polarity is deposited on the tunnel layer 18 on the back side 14. In the following, a p-type doping is assumed as the first polarity of the highly doped silicon layer. The deposition of the highly doped p-type silicon layer 20 can take place, for example, by means of plasma-enhanced chemical vapor deposition, PECVD, atmospheric chemical vapor deposition, APCVD, low pressure chemical vapor deposition (LPCVD) or cathode sputtering. The highly doped p-type silicon layer 20 has a thickness of approximately 50 nm to 400 nm. According to a further embodiment which is not shown, the deposition of the highly doped silicon layer can also take place on both sides, on front and back sides.

[0055] The deposition of the highly doped p-type silicon layer 20 can take place in two steps instead of in one. In this case, the deposition of the p-type silicon layer 20 comprises the deposition of undoped silicon and subsequent introduction of a dopant. The dopant is introduced, for example, by means of furnace diffusion or laser diffusion from a doping source applied to the silicon layer, or by means of ion implantation. The dopant is, for example, boron, aluminum or gallium.

[0056] In a next step of the method, cf. FIG. 2c, a dielectric layer 22 is deposited on the back side 14, on the highly doped silicon layer 20. The layer deposition takes place only on the back side 14. A parasitic deposition on the front side 16 cannot be ruled out entirely. The dielectric layer 22 is deposited, for example, by PECVD, APCVD, LPCVD or PVD. The dielectric layer 22 has a greater thickness than the first passivation layer 18 and is thus thicker than 4 nm.

[0057] FIG. 2d shows a further method step of exposing base regions 24 of the semiconductor substrate 12 on the back side 14 by local removal of the dielectric layer 22, of the highly doped silicon layer 20 of the first polarity, and of the first passivation layer 18. Furthermore, the removal of the passivation layer 18 on the front side 16 is shown. In a further embodiment which is not shown, removal of a silicon layer on the front side 16 may also be necessary.

[0058] The exposure of the base regions 24 takes place, for example, by local removal of the dielectric layer 22 by laser irradiation. It is also conceivable that the second dielectric layer 22 is not completely removed.

[0059] The highly doped silicon layer 20, the first passivation layer 18, and optionally a part of the semiconductor substrate 12 can likewise be at least partially locally removed by laser irradiation.

[0060] Alternatively, the highly doped silicon layer 20 and/or the first passivation layer 18 can be partially etched, locally, by a wet-chemical solution. The dielectric layer 22 was advantageously selected such that the wet-chemical solution does not etch the dielectric layer 22, or etches it substantially more slowly than the highly doped silicon layer 20 and the first passivation layer 18. Depending on which layers have already been previously removed by laser irradiation, the wet-chemical solution optionally also etches remaining residues of the dielectric layer 22, the first passivation layer 18 on the front side 16, and optionally a part of the semiconductor substrate on the front side 16 and the back side 14. Alternatively, the first passivation layer 18 can also serve as an etching barrier, such that the first passivation layer and the semiconductor substrate 12 are not etched. In the event that the highly doped silicon layer is also located on the front side 16, this is also etched in a further embodiment (not shown).

[0061] It can be provided for the etching to comprise isotropic etching for polishing regions, and/or for the etching to comprise anisotropic etching for texturing regions. For example, the base regions 24 can be polished by isotropic etching using a wet-chemical solution, on the back side 14. Alternatively, the base regions 24 can be textured by anisotropic etching using a wet-chemical solution, on the back side 14. It can also be advantageous if the front side 16 is textured by anisotropic etching using a wet-chemical solution. Different wet-chemical solutions can be used for removing and optionally texturing and/or polishing the different layers and surfaces.

[0062] FIG. 2e shows the deposition of a precursor layer 26 on the entire back side 14 and the entire front side 16 of the solar cell 10. The deposition on front side 16 and back side 14 takes place, for example, simultaneously. The precursor layers 26 on the front side 16 and the back side 14 can have different properties, for example with regard to the thickness or a dopant quantity contained in the precursor layer 26. On the back side, the precursor layer 26 on the different surfaces, the dielectric layer 22, or the exposed base region 24, can be deposited differently and thus have different properties. The precursor layer 26 is a layer comprising a dopant of a second polarity, in particular a phosphosilicate glass layer, PSG. In order to apply the precursor layer 26, for example a furnace diffusion process can be carried out, in which a phosphosilicate glass layer grows on the highly doped silicon layer 20, on the back side 14 and on the front side 16. The furnace diffusion process can be carried out such that a high proportion of phosphorus is contained in the phosphosilicate glass layer after the furnace diffusion process. Alternatively, the precursor layer 26, for example PSG, can be deposited, for example by means of PECVD, LPCVD or APCVD.

[0063] In a high-temperature step, in which the dopant diffuses from the precursor layer 26 into the base regions 24 on the back side 14 and/or into the surface of the front side 16, the doping in the base regions 24 on the back side 14 is increased and a doped region 28 is produced on the front side 16. The dopant dopes the base regions 24 on the back side 14 according to a second polarity, opposite to the first polarity of the highly doped silicon layer 20, such that doped base regions 24 are generated. The doped base regions 24 on the back side 14 have a higher dopant concentration than the dopant concentration of the semiconductor substrate 12. On the back side 14, the dopant does not diffuse from the precursor layer 26, or only in small amounts, into the highly doped silicon layer 20, since the dielectric layer 22 serves as a diffusion barrier against the dopant from the precursor layer 26. On the front side 16, the doped region 28 on the front side 16 is created by the doping of the surface according to the second polarity. The dopant concentration of the doped region 28 on the front side 16 is higher than the dopant concentration of the semiconductor substrate 12. The high-temperature step is, for example, the furnace diffusion step for applying the precursor layer 26. Alternatively, it can also be an additional high-temperature step.

[0064] The high-temperature step can be carried out, for example, in such a way that only a part of the second dopant diffuses from the precursor layer into the base regions on the back side, such that a significant amount of dopant is then preferably still located in the precursor layer 26. The high-temperature step can also serve to activate the dopant in the highly doped layer 20.

[0065] FIG. 2f shows the creation of highly doped base regions 30 in the doped base regions 24 by locally increasing the dopant concentration, in particular by laser irradiation. As a result of the laser irradiation, the previously deposited precursor layer 26 melts or evaporates, and the surface on the back side is locally heated and melted in the irradiated regions. Further dopant from the precursor layer diffuses into the surface at the irradiated regions and, after cooling and recrystallization, further dopes the irradiated region according to the second polarity, such that the highly doped base regions 30 are produced. The dopant concentration in highly doped base regions 30 is significantly higher than the dopant concentration of the semiconductor substrate 12, the doped base regions 24, and the doped region 28 on the front side 16. By suitable selection of the laser parameters, locally selectively differently highly doped portions can also be produced in the highly doped base regions 30.

[0066] Furthermore, it is provided that, in particular, remaining residues of the precursor layer 26 are removed from the front side 16 and from the back side 14. The removal takes place after the laser irradiation, for example in a wet-chemical cleaning step. Advantageously, remaining residues of the dielectric layer 22 are also removed from the highly doped silicon layer 20 by the wet-chemical cleaning step or by a further post-chemical cleaning step.

[0067] The method further comprises a step for applying a second passivation layer 32 on the back side 14 and a third passivation layer 34 on the front side 16, cf. FIG. 2g. The passivation layers 32, 34 comprise, for example, silicon dioxide, silicon nitride, aluminum oxide or a layer stack of two or more dielectric layers. In this case, the thickness, refractive index and composition of the second passivation layer 32 on the back side 14 can differ from the thickness, refractive index and composition of the third passivation layer 34 on the front side 16. The thicknesses of the passivation layers 32, 34 are advantageously optimized such that the reflection is reduced on the front side 16 and increased on the back side 14. The passivation layers 32, 34 advantageously have a greater thickness than the first passivation layer 18. The thickness of the second passivation layer 32 is advantageously greater than 4 nm. The high-temperature step for the growth of the thermal silicon dioxide, of the passivation layers 32, 34, can also serve to activate the dopant in the highly doped layer 20.

[0068] The method further comprises a step for applying electrodes 36 of a first polarity and electrodes 38 of a second polarity on the back side 14 of the solar cell 10, cf. FIG. 2h. The electrodes 36, 38 can be applied, for example, by means of screen printing, vapor deposition, sputtering or galvanic deposition of one or more metals or other conductive layers. The electrodes 36, 38 can comprise, for example, silver paste, silver/aluminum paste, aluminum paste or pure aluminum, copper, tin, palladium, silver, titanium, nickel, or layer stacks or alloys of the mentioned metals, or other conductive layers, in particular conductive polymers or oxides, or a combination of such layers with metals. The composition and the deposition process of the electrodes 36, 38 can differ for the electrodes 36, 38 of the two polarities. The electrodes 36, 38 can locally penetrate the passivation layer 32, in particular in a high-temperature step after the screen printing, and, depending on the polarity of the electrodes 36, 38, contact either a doped base region 24, the highly doped silicon layer 20, or a highly doped base region 30. Preferably, the electrodes 38 of the second polarity only contact the highly doped base regions 30 and not the doped base regions 24.

[0069] Optionally, prior to applying the electrodes 36, 38, the passivation layer 32 can be selectively removed, for example by laser irradiation, such that the electrodes directly contact the highly doped silicon layer 20 or the locally highly doped base regions 30 exclusively in the selectively removed regions.