Process for the hetero-integration of a semiconductor material of interest on a silicon substrate

Abstract

A process for the hetero-integration of a semiconductor material of interest on a silicon substrate, includes a step of structuring the substrate which comprises a step of producing a growth mask on the surface of the silicon substrate, the growth mask comprising a plurality of masking patterns, two masking patterns being separated by a trench wherein the silicon substrate is exposed; a step of forming a two-dimensional buffer layer made of a 2D material, the buffer layer being free of side bonds on its free surface and being formed selectively on at least one silicon plane of [111] orientation in at least one trench, the step of forming a buffer layer being performed after the structuring step; a step of forming at least one layer of a semiconductor material of interest on the buffer layer. The semiconductor material of interest is preferably a IV-IV, III-V, II-VI semiconductor material and/or a 2D semiconductor material.

Claims

1. A process for the hetero-integration of a semiconductor material of interest on a silicon substrate, comprising: a step of removing a native oxygen from the silicon substrate; a step of structuring the substrate which comprises a step of producing a growth mask on the surface of the silicon substrate, said growth mask comprising a plurality of masking patterns, two masking patterns being separated by a trench wherein the silicon substrate is exposed; a step of forming a two-dimensional buffer layer made of a 2D material, said buffer layer being free of side bonds on its free surface and being formed selectively on a silicon plane of [111] orientation in at least one trench, said step of forming a buffer layer being performed after the structuring step and being performed by an organometallic vapour deposition (MOCVD) technique; a step of forming at least one layer of a semiconductor material of interest on the buffer layer; and a passivation step which consists in depositing an atomic biplane of gallium and selenium onto the silicon plane of [111] orientation so as to form a silicon-gallium-selenium passivated surface on said plane.

2. The process according to claim 1, the semiconductor material of interest being a IV-IV, III-V, II-VI semiconductor material and/or a 2D semiconductor material.

3. The process according to claim 1, the masking patterns being made of a dielectric material.

4. The process according to claim 1, the silicon substrate being a silicon (Si(001)) substrate of [001] orientation and the structuring step also comprising a step of forming at least one silicon facet of [111] orientation in the silicon substrate, so as to form at least a silicon plane of [111] orientation, the facet being produced through a trench.

5. The process according to claim 4, the facet having an inclined surface with an angle of less than 90° relative to the surface of the substrate wherein said facet is formed.

6. The process according to claim 5, two silicon facets of [111] orientation being formed in a trench, each facet having an inclined surface with an angle of less than 90° relative to the surface of the substrate in which said facet is formed.

7. The process according to claim 1, the passivation step being performed between the structuring step and the step of forming the buffer layer.

8. The process according to claim 1, wherein the step of forming at least one buffer layer consists of van der Waals epitaxy and comprises: a first step of nucleating a 2D material on the passivated surface; and a first step of growth of the nuclei obtained on conclusion of the first nucleation step.

9. The process according to claim 1, the step of preparing at least one layer of a semiconductor material of interest consisting of an additional epitaxy step comprising: a second step of nucleating the semiconductor of interest on the buffer layer; and a second step of growth of the nucleation layer obtained on conclusion of the second nucleation step.

10. The process according to claim 1, the width of a trench being less than or equal to 20 μm, preferably less than or equal to 2 μm.

11. The process according to claim 1, the 2D material of the buffer layer being chosen from GaSe, GaS, GaTe, MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, InSe or a combination of said materials.

12. The process according to claim 1, the semiconductor material of interest being chosen from GaAs, GaSb, GaN and AlN.

13. A structure obtained via the hetero-integration process according to claim 1 and comprising: a silicon substrate; a plurality of masking patterns located on the silicon substrate, two masking patterns being separated by a trench; a two-dimensional buffer layer located in each trench; and a layer of a semiconductor material of interest located on the two-dimensional buffer layer and at least in each trench, said layer of a semiconductor material of interest having a density of threading dislocations of less than 10.sup.6/cm.sup.2; and a passivation layer made of silicon-gallium-selenium between the silicon substrate and the two-dimensional buffer layer.

14. The structure according to claim 13, the semiconductor material of interest being a IV-IV, III-V, II-VI semiconductor material and/or a 2D semiconductor material.

15. The structure according to claim 13, the layer of a semiconductor material of interest filling each trench and also extending outside each trench, for example to form a horizontal nanowire.

16. The structure according to claim 13, the layer semiconductor material of interest being a monocrystalline material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other characteristics and advantages of the invention will become apparent with the aid of the following description given for illustrative purposes and without any implied limitation, with reference to the appended figures, among which:

(2) FIG. 1 represents a first variant of selective epitaxial growth according to the prior art;

(3) FIG. 2A and FIG. 2B represent a second variant of selective epitaxial growth according to the prior art;

(4) FIG. 3 represents a third variant of selective epitaxial growth according to the prior art;

(5) FIG. 4A-FIG. 4N represent an example and variants of the hetero-integration process according to the invention.

DETAILED DESCRIPTION

(6) FIGS. 1, 2A, 2B and 3 (prior art) have been described previously and will not be repeated here.

(7) FIGS. 4A to 4N represent an example and variants of the hetero-integration process according to the invention. In this example, the starting silicon substrate 1 has a [001] crystal orientation and may thus be denoted as Si(001).

(8) The process comprises a step of structuring the [001] oriented silicon substrate, which comprises a step of making a growth mask 2 on the surface of said substrate (FIG. 4A). The growth mask 2 comprises masking patterns 20. The growth mask is preferably made of a dielectric material, generally SiO.sub.2 or SiN, which shows selectivity towards etching relative to the silicon substrate. Two consecutive (or adjacent) masking patterns are separated from each other by a distance 1. This distance 1 corresponds in this example to the width of a trench 21. A trench corresponds to an area of the substrate 1 not masked with the dielectric material (or “exposed area”).

(9) The masking patterns may be made starting with a silicon substrate, by performing a thermal oxidation of said substrate, making it possible to deposit an upper layer of silicon oxide (SiO.sub.2 layer), and then by defining trenches by lithography and etching into the SiO.sub.2 layer so as to expose the silicon surface at the bottom of each trench.

(10) At this stage of the process, the trenches have a depth h and a width l (distance between two patterns). The width l of a trench may be between a few tens of nanometres and 20 micrometres. Preferably, the width l of a trench is less than 2 micrometres. The length L of the masking patterns may be greater than several tens of micrometres.

(11) According to the example shown in FIG. 4B, the structuring step comprises a step of chemical etching of the silicon substrate 1 in each trench 21 so as to form silicon facets 31, 32 having a [111] orientation which may be denoted as Si(111). The Si(111) facets form V-shaped grooves in the silicon substrate 1.

(12) The chemical etching may be anisotropic and performed with solutions based on tetramethylammonium or tetraethylammonium hydroxide diluted in water, with ammonia, potassium hydroxide or sodium hydroxide. The temperatures of the solutions during the etching step conventionally range between 20° C. and 100° C.

(13) Prior to the chemical etching, a first step of removing the native oxide (not shown) may be necessary, notably depending on the chemical etching solutions used. This first step of removing the native oxide is generally performed by chemical attack with hydrofluoric acid (HF), typically by exposing the substrate to a dilute hydrofluoric acid solution (for example at a volume concentration of 0.2% to 1%) for 30 to 90 seconds.

(14) After the chemical etching step, the structuring step comprises a second step of removing the native oxide from the silicon so as to obtain deoxidized Si(111) facets 31′, 32′, as shown in FIG. 4C. This second step of removing the native oxide is generally performed by chemical attack with hydrofluoric acid (HF), typically with a dilute hydrofluoric acid solution (for example at a volume concentration of 0.5%) for 30 to 60 seconds.

(15) The chemical etching step to form the Si(111) planes is not necessary if a [111] oriented silicon substrate is used instead of the Si(001) substrate.

(16) The chemical etching step is notably not necessary if a silicon substrate is available which already has at least one silicon plane of [111] orientation: this may mean that the surface of the substrate is made of Si(111), or that the Si(001) substrate already comprises Si(111) facets.

(17) In the case of an Si(111) substrate, the growth mask may be designed on said silicon substrate so that the masking patterns leave parts of the Si(111) substrate exposed. The steps described below may then be performed.

(18) More generally, irrespective of the orientation of the silicon substrate, the masking patterns must leave [111] oriented silicon planes exposed.

(19) In the case of an Si(001) substrate, the [111] oriented planes will typically form a V, the first segment of which forms an angle of +54.74° relative to the substrate and the second segment of which forms an angle of −54.74° relative to the substrate.

(20) In the case of an Si(111) substrate, the exposed Si(111) planes will be substantially at 0° relative to the surface of the substrate.

(21) The process then comprises a step of selective passivation of the Si(111) facets, consisting in depositing on said facets an atomic plane of gallium followed by an atomic plane of selenium (FIG. 4D). This makes it possible to obtain the formation of a passivated silicon surface (also denoted as the “passivation layer” 4) made of Si—Ga—Se, as illustrated in FIG. 4E. This surface is electronically saturated and is stable at high temperature (up to about 650-700° C.). This passivation layer 4 then makes it possible to grow a 2D material by van der Waals epitaxy, as described below.

(22) An atomic plane of Ga thus bonded to an atomic plane of Se may be called an “atomic biplane” and may be seen as a half-sheet of the “2D GaSe” material. Specifically, 2D GaSe denotes two-dimensional gallium selenide (as a sheet) consisting of four atomic planes of sequence Se—Ga—Ga—Se.

(23) The term “electronically passivated surface” or “passivation layer” or “electronically saturated surface” means a surface without side bonds: the gallium and selenium atoms of which the passivation layer is composed have all their valency electrons paired.

(24) To perform this passivation step, the silicon substrate is typically introduced into a growth chamber and the GaSe atomic biplane is deposited via the organometallic vapour deposition technique “MOCVD” (meaning Metal Organic Chemical Vapour Deposition). The MOCVD technique is performed by transporting Ga and Se precursors which are introduced into the growth chamber via a carrier gas, so as to form the passivation layer on the Si(111) facets which are in the trenches of the growth mask (and thus exposed).

(25) To obtain the Si—Ga—Se passivation layer by MOCVD, use is made of organometallic precursors introduced simultaneously into the chamber, which are typically TriMethylGallium (TMGa) and DiisoPropylSelenium (DiPSe), which are gaseous at the working temperature in the process. Alternatively, it may be any other gallium precursor and/or any other selenium precursor.

(26) The carrier gas is typically hydrogen. Alternatively, it may be nitrogen or argon, or any other inert gas from column VIII of the Periodic Table.

(27) The passivation step is generally performed at between 400° C. and 650° C.

(28) The total pressure is adapted as a function of the chamber geometry, but typical values are between 5 and 200 Torr.

(29) The partial pressure of the gallium precursor is generally between 1 and 200 mTorr.

(30) The III/VI molar flow ratio (group III precursor/group VI precursor) is generally between 1 and 10.

(31) According to a particular embodiment, the conditions of the passivation step are: total pressure in the chamber: 10-20 Torr; partial pressure of TMGa: about 10 mTorr; Se/Ga (VI/III) molar flow ratio: about 3-4; temperature: 530-550° C.; growth time t: between 2 and 5 seconds.

(32) The MOCVD technique is advantageous because it enables good reproducibility and high rates of crystal growth. In addition, it is industrially applicable.

(33) Alternatively, use may be made of other chemical vapour deposition (CVD) techniques, such as atomic layer deposition (ALD).

(34) As has been mentioned previously, following the passivation step, the process comprises a step of epitaxy, of the van der Waals epitaxy type, consisting in epitaxially growing a 2D material on the passivation layer 4 so as to form a two-dimensional buffer layer 5, visible in FIG. 4K. This epitaxy step typically comprises a first step of nucleation and a first step of growth or a step of lateral growth of the nuclei. These steps are detailed below.

(35) The term “lateral growth” means that each nucleus grows by extending mainly in the plane of the passivation layer and more generally the plane on which it was deposited.

(36) In the example shown, the buffer layer 5 is made of gallium selenide structured in sheets (2D GaSe). In other words, the buffer layer 5 comprises at least one 2D GaSe sheet.

(37) The first nucleation step is a step of GaSe nucleation. The GaSe nucleation step is performed by depositing grains 51 of GaSe onto the passivation layer 4, visible in FIGS. 4F and 4G. The GaSe nuclei have an initial width equal to a few tens of nanometres.

(38) To perform the nucleation, the substrate is maintained in the growth chamber and the MOCVD technique is used. The precursors that may be used are the same as for the passivation step. The partial pressures of precursor used are less than those of the passivation step.

(39) The carrier gas is typically hydrogen. Alternatively, it may be nitrogen, argon, or any other inert gas from column VIII of the Periodic Table.

(40) The first nucleation step is generally performed at between 400° C. and 650° C.

(41) The total pressure in the chamber has values typically between 5 and 80 Torr.

(42) The partial pressure of the Ga precursor is generally between 1 and 50 mTorr.

(43) The VI/III molar flow ratio depends on the type of precursor. Typical values are between 3 and 4.

(44) According to a particular embodiment, the conditions of the first nucleation step are as follows: total pressure in the chamber: 5-20 Torr; partial pressure of TMGa: about 2-3 mTorr; Se/Ga (VI/III) molar flow ratio: about 3-4; temperature: 530-550° C.

(45) The thickness of the nuclei reaches about 8 Å for a growth time t.sub.1 of between 2 and 3 seconds.

(46) After nucleation, the GaSe nuclei are grown laterally, over several micrometres, as shown in FIGS. 4H and 4I, until at least one continuous sheet is obtained on the [111] oriented facets 52. Each 2D GaSe sheet is crystallographically oriented relative to the Si(111) surface, as illustrated in FIGS. 4J and 4K.

(47) FIG. 4K represents a buffer layer 5 formed by two GaSe sheets located on the passivation layer 4: a lower sheet 52 and an upper sheet 53. The bonding 54 between the lower sheet 52 and the passivation layer 4 and the bonding 55 between the two sheets 52, 53 are weak van der Waals bonds. The outer surface 56 of the upper sheet 53 has no side bonds.

(48) This first growth step, or step of lateral growth of the GaSe grains, is performed at a lower partial pressure and a higher temperature than the first nucleation step.

(49) The substrate is maintained in the growth chamber.

(50) The first growth step, or lateral growth step, is generally performed at between 570° C. and 650° C.

(51) The total pressure in the chamber has values typically between 5 and 80 Torr.

(52) The partial pressure of the Ga precursor is generally between 0.5 and 5 mTorr.

(53) The VI/III molar flow ratio depends on the type of precursor. Typical values are between 3 and 4.

(54) According to a particular embodiment, the conditions of the first growth step are as follows: total pressure in the chamber: 5-20 Torr; partial pressure of TMGa: about 1 mTorr; Se/Ga (VI/III) molar flow ratio: about 3-4; temperature: 600-640° C.

(55) The growth time t.sub.2 to make the GaSe grains completely coalesce as a continuous sheet is about 200 seconds.

(56) To obtain a continuous 2D GaSe sheet (thickness of about 8 Å), a nucleation time t.sub.1 and a lateral growth time t.sub.2 are mandatorily required. As t.sub.2 is very much longer than t.sub.1, t.sub.1 can be ignored and as such about 200 seconds are required for one sheet and, by extension; about 400 seconds are required for two sheets; about 600 seconds are required for three sheets.

(57) The growth rate is thus of the order of 2-3 Å.Math.min.sup.−1.

(58) The buffer layer is formed by one (or more) sheets of the 2D material. In the example shown, the buffer layer 5 is formed by two sheets 52 and 53 of 2D GaSe.

(59) The GaSe buffer layer is stable up to about 950° C. It is free of side bonds. It is thus suitable for growth, without mechanical constraints, of semiconductor materials of interest (IV-IV, III-V, II-VI, 2D materials, etc.) by epitaxy, such as GaAs in the example shown.

(60) Depending on the type of semiconductor material of interest to be epitaxially grown, the GaSe two-dimensional buffer layer can be replaced with a two-dimensional buffer layer made of a 2D material other than GaSe, on condition that the step of passivation of the Si(111) with an atomic plane of gallium Ga followed by an atomic plane of selenium Se is conserved. Examples that may be mentioned include one of the following materials: GaS, GaTe, MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, InSe. Several different layers from among a combination of the materials mentioned previously may be combined. Preferably, the 2D material is a material that is stable up to 1000° C.

(61) The process then comprises an additional epitaxy step consisting in epitaxially growing a semiconductor material of interest, which is typically a IV-IV, III-V, II-VI semiconductor material or a 2D semiconductor material, on the two-dimensional buffer layer. This additional epitaxy step typically comprises a second nucleation step and a second growth step, which is rapid growth at high temperature. These steps are detailed below.

(62) In the example shown, the semiconductor material of interest is gallium arsenide (GaAs). Thus, the second nucleation step is a step of GaAs nucleation. However, the example is not in any way limiting and the process is the same for another semiconductor material from among IV-IV, III-V, II-VI semiconductor materials or 2D semiconductor materials, etc. A semiconductor material of interest may be chosen from the following materials: GaAs, GaSb, GaN, AlN, or a combination of said materials.

(63) The GaAs nucleation step, shown in FIG. 4L, is performed by selective deposition onto the buffer layer 5 of a nucleation layer 6 made of gallium arsenide (GaAs).

(64) The substrate is maintained in the growth chamber and the MOCVD technique is used.

(65) To obtain GaAs by MOCVD, use is made of organometallic precursors, which are typically TriMethylGallium (TMGa) and Tert-ButylArsine (TBAs), which are gaseous at the working temperature in the process. Alternatively, it may be any other gallium precursor and/or any other arsenic precursor.

(66) The carrier gas is typically hydrogen. Alternatively, it may be nitrogen or helium, or any other inert gas from column VIII of the Periodic Table.

(67) The second nucleation step is generally performed at between 350° C. and 450° C.

(68) The total pressure in the chamber has typical values of between 80 and 600 Torr.

(69) The partial pressure of the gallium precursor is generally between 0.5 and 5 Torr.

(70) The molar flow ratio is generally between 1.5 and 10.

(71) According to a particular embodiment, the conditions of the second nucleation step are: total pressure in the chamber: 200-450 Torr; time: 200-400 seconds; partial pressure of TMGa: about 1.5 Torr; As/Ga molar flow ratio: about 2.5; temperature: 370-390° C.

(72) The second growth step, shown in FIG. 4M or in FIG. 4N, takes place vertically in the trench. The substrate is maintained in the growth chamber.

(73) The temperature is increased to make the GaAs nuclei coalesce and to start the step of rapid growth of the GaAs at high temperature and low pressure, which makes it possible to obtain a localized layer of GaAs of excellent crystalline quality.

(74) The second growth step is generally performed at between 550° C. and 670° C.

(75) The total pressure in the chamber has typical values of between 5 and 80 Torr.

(76) The partial pressure of the gallium precursor is generally between 10 and 50 mTorr.

(77) The molar flow ratio is generally between 2.5 and 15.

(78) According to a particular embodiment, the conditions of the second growth step are: total pressure in the chamber: 20 Torr; time: 300 seconds; partial pressure of TMGa: about 30 mTorr; As/Ga molar flow ratio: about 3.5; temperature: 570-630° C.

(79) A structure is thus obtained comprising: a silicon substrate 1; a plurality of masking patterns 20 located on the silicon substrate 1, two masking patterns being separated by a trench 21; a passivation layer 4 located in each trench; a two-dimensional buffer layer 5 located on the passivation layer 4 in each trench; a layer 61, 62 of a semiconductor material of interest located on the two-dimensional buffer layer 5 and filling at least each trench, said layer of a semiconductor material of interest having a density of threading dislocations of less than 10.sup.6/cm.sup.2.

(80) Preferably, the semiconductor material of interest is a IV-IV, III-V, II-VI semiconductor material and/or a 2D semiconductor material.

(81) Preferably, the masking patterns are made of a dielectric material.

(82) In addition, the layer 61 of semiconductor material of interest may be confined in the trenches, as illustrated in FIG. 4M. Alternatively, the layer 62 of semiconductor material of interest may be widened by lateral growth outside of each trench, for example to form a horizontal nanowire of square cross-section, as illustrated in FIG. 4N.

(83) In addition, the layer of semiconductor material of interest is preferably of [100] orientation.

(84) Since the buffer layer of two-dimensional material does not comprise any side bonds, it may then function as a universal substrate for the localized growth of the semiconductor of interest with a reduced defect content (notably a reduced density of threading dislocations) and thus having optimized physicochemical properties. Specifically, contrary to direct growth on a silicon substrate, growth on the buffer layer of two-dimensional material makes it possible to overcome the problem of the difference in lattice parameters. It is achieved with no (or with very few) covalent bonds at the interface, by promoting van der Waals growth, thus enabling the formation of an unconstrained material, which avoids the process of relaxation by generation of threading dislocations. This thus makes it possible to form a layer of a semiconductor material of interest which is a crystalline material with a density of threading dislocations of less than 10.sup.6/cm.sup.2. The semiconductor material of interest is preferably a monocrystalline material.

(85) In addition, the selective growth, i.e. without the trenches between the masking patterns, of a 3D semiconductor material (GaAs, GaN, etc.) on a 2D material makes it possible to concentrate the nucleation on a very limited number of areas of the substrate: the nucleation density is thereby considerably enhanced and notably allows the growth of a continuous layer of a 3D material on a 2D material.

(86) The present invention is not limited to the embodiments described previously, but extends to any embodiment falling within the scope of the claims.

(87) Among the numerous applications of the invention, mention may be made of microelectronics, photonics, sensors, radiofrequency-related technologies, electromechanical microsystems (MEMS), Internet-of-things components, battery chargers, high-voltage components, microprocessors, static and dynamic memories, photovoltaics, and more broadly anything concerning “more than Moore” technologies or derivative technologies, i.e. technologies which integrate several functions on the same silicon chip.