The present disclosure provides a nitride semiconductor device. The nitride semiconductor device includes: an electron transport layer, made of a nitride semiconductor; an electron supply layer, disposed on the electron transport layer and made of a nitride semiconductor having a band gap greater than a band gap of the nitride semiconductor of the electron transport layer; a first protective layer, disposed on the electron supply layer and made of a nitride semiconductor having a band gap less than the band gap of the nitride semiconductor of the electron supply layer; a second protective layer, disposed on a portion of the first protective layer and made of a nitride semiconductor having a band gap greater than the band gap of the nitride semiconductor of the first protective layer; and a gate layer, disposed on the second protective layer.

A semiconductor device includes: a semiconductor substrate including a front surface, a back surface that is opposite to the front surface, and a drift layer of a first conductive type disposed between the front surface and the back surface; a first diffusion layer of a second conductive type provided between the drift layer and the front surface; a second diffusion layer provided between the drift layer and the back surface; a first buffer layer of the first conductive type provided between the drift layer and the second diffusion layer, having a concentration higher than that of the drift layer, and into which a proton is injected; and a second buffer layer of the first conductive type provided between the first buffer layer and the second diffusion layer and having a concentration higher than that of the drift layer, wherein a peak concentration of the second buffer layer is higher than a peak concentration of the first buffer layer, an impurity concentration of the first buffer layer gradually decreases toward the back surface, a length from a peak position of the first buffer layer to a boundary between the drift layer and the first buffer layer is represented by Xa, a length from the peak position to a boundary between the first buffer layer and the second buffer layer is represented by Xb, and Xb>5 Xa.

A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

Provided is a semiconductor device comprising a semiconductor substrate containing oxygen. An oxygen concentration distribution in a depth direction of the semiconductor substrate has a high oxygen concentration part where an oxygen concentration is higher on a further upper surface-side than a center in the depth direction of the semiconductor substrate than in a lower surface of the semiconductor substrate. The high oxygen concentration part may have a concentration peak in the oxygen concentration distribution. A crystal defect density distribution in the depth direction of the semiconductor substrate has an upper surface-side density peak on the upper surface-side of the semiconductor substrate, and the upper surface-side density peak may be arranged within a depth range in which the oxygen concentration is equal to or greater than 50% of a peak value of the concentration peak.

A cell structure of a silicon carbide MOSFET device, comprising a drift region (3) located on a substrate layer (2), a second conducting type well region (4) and a first JFET region (51) that are located in the drift region (3), an enhancement region located within a surface of the well region (4), a gate insulating layer (8) located on a first conducting type enhancement region (6), the well region (4) and the first JFET region (51) and being in contact therewith at the same time, a gate (9) located on the gate insulating layer, source metal (10) located on the enhancement region, Schottky metal (11) located on a second conducting type enhancement region (7) and the drift region (3), a second JFET region (52) located on a surface of the drift region (3) between the Schottky metals (11), and drain metal (12).

In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

The present disclosure relates to a wafer, a manufacturing method thereof, and a semiconductor device. The wafer manufacturing method includes: providing a wafer having a scribe lane for die cutting. A plurality of through-silicon-vias for cracking stress release and prevention is formed on one side of the scribe lane, and the through-silicon-vias are filled with a protective material. Through the technique of through-silicon vias filled with protective materials on both sides of the scribe lane, the cutting stress can prevent damage to the die area during wafer cutting. The through-silicon-vias can effectively reduce the scribe lane width, which is conducive to miniaturizing the scribe lane and improving the effective utilization of wafers.

The present disclosure relates to semiconductor power devices, and in particular, to a high-electron-mobility transistor (HEMT) with high voltage endurance capability and a preparation method thereof. The high-electron-mobility transistor with high voltage endurance capability includes a gate electrode, a source electrode, a drain electrode, a barrier layer, a P-type nitride semiconductor layer and a substrate, wherein the P-type nitride semiconductor layer is between the barrier layer and the substrate, which is insufficient to significantly deplete a two-dimensional electron gas in a channel except a gate stack, the source electrode is in electrical contact with the P-type nitride semiconductor layer, and the source electrode and the drain electrode are both in electrical contact with the two-dimensional electron gas.

An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.

A transistor device ac includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer, a source contact and a drain contact on the barrier layer, and a gate contact on the barrier layer between source contact and the drain contact. The device further includes a plurality of selective modified access regions at an upper surface of the barrier layer opposite the channel layer. The selective modified access regions include a material having a lower surface barrier height than the barrier layer, and the plurality of selective modified access regions are spaced apart on the barrier layer along a length of the gate contact.