SEMICONDUCTOR WAFER AND METHOD FOR FABRICATING A SEMICONDUCTOR WAFER

Abstract

In an embodiment, a semiconductor wafer includes a front surface, a plurality of active component positions, and at least one composite alignment mark arranged on the front surface and indicating a unique orientation of the semiconductor wafer. The composite alignment mark includes a first portion that has at least one raised section formed of a first material and a second portion that is positioned laterally adjacent the first portion. The second portion has at least one raised section formed of a second material that is different form the first material.

Claims

1. A semiconductor wafer, comprising: a front surface; a plurality of active component positions; and at least one composite alignment mark arranged on the front surface and indicating a unique orientation of the semiconductor wafer; wherein the at least one composite alignment mark comprises a first portion that comprises at least one raised section formed of a first material and a second portion that is positioned laterally adjacent the first portion and that comprises at least one raised section formed of a second material that is different form the first material.

2. The semiconductor wafer of claim 1, wherein the first and second portions have complementary shapes.

3. The semiconductor wafer of claim 1, wherein the at least one composite alignment mark is rotationally asymmetric.

4. The semiconductor wafer of claim 1, wherein a first raised section of the first portion has the form of a closed border that laterally surrounds a second raised section of the first portion that is rotationally asymmetric and indicates the unique orientation of the semiconductor wafer.

5. The semiconductor wafer of claim 1, wherein the second portion is contiguous with the first portion.

6. The semiconductor wafer of claim 1, wherein the second portion overlaps the first portion.

7. The semiconductor wafer of claim 1, wherein the second portion is spaced apart a distance from the first portion.

8. The semiconductor wafer of claim 1, wherein at least one composite alignment mark is positioned in an inactive portion of the semiconductor wafer outside of the plurality of active component positions and/or in a scribe line region that is adjacent one of the active component positions and/or in a dummy component position.

9. The semiconductor wafer of claim 1, wherein the first material comprises a metal or alloy.

10. The semiconductor wafer of claim 1, wherein the first material comprises Al or comprises Cu or is formed of an AlCu alloy or comprises Au, W, a W alloy, Ti or TiN.

11. The semiconductor wafer of claim 1, wherein the second material comprises an electrically insulating material.

12. The semiconductor wafer of claim 11, wherein the electrically insulating material comprises an imide or an epoxy or a nitride or an oxide or a multilayer structure comprising a nitride layer and an oxide layer.

13. The semiconductor wafer of claim 1, wherein the active component positions each comprise a transistor device and the first portion is formed in a same electrically conductive layer as a layer of a source pad and/or a gate pad and the second portion is formed in an electrically insulating layer arranged on the front surface of the active component positions of the semiconductor wafer.

14. A method of fabricating a semiconductor wafer, the method comprising: depositing a first layer of a first material onto a front surface of the semiconductor wafer, wherein the semiconductor wafer comprises a plurality of active component positions; forming a first portion of at least one composite alignment mark in the first layer, the first portion having at least one raised section formed of the first material and indicating a unique orientation of the wafer; depositing a second layer on the first layer, the second layer comprising a second material that differs from the first material; and structuring the second layer to form a second portion of the at least one composite alignment mark, the second portion comprising at least one raised section formed of the second material, and to expose at least at part of the at least one raised section formed of the first material, to form the at least one composite alignment mark which indicates the unique orientation of the semiconductor wafer.

15. The method of claim 14, wherein the forming the first portion of at least one composite alignment mark in the first layer comprises: structuring the first layer by laser ablation to form the at least one raised section formed of the first material.

16. The method of claim 14, wherein the forming the first portion of at least one composite alignment mark in the first layer comprises: structuring the first layer by etching to form the at least one raised section formed of the first material.

17. The method of claim 14, wherein the forming the first portion of at least one composite alignment mark in the first layer comprises: selectively depositing the first material to form the at least one raised section formed of the first material.

18. The method of claim 14, further comprising: structuring the first layer to form a gate pad and/or a source pad in the active component positions; and structuring the second layer to expose the gate pad and/or the source pad.

19. The method of claim 14, further comprising: testing one or more parameters of a device that is positioned in one of the active component positions and/or testing one or more parameters of an auxiliary device that is positioned in a dummy component position or in a scribe line region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Exemplary embodiments are depicted in the drawings and are detailed in the description which follows.

[0055] FIG. 1 illustrates a schematic top view of a front side of a semiconductor wafer according to an embodiment.

[0056] FIG. 2A illustrates a cross-sectional view and FIG. 2B a top view of a composite alignment mark according to an embodiment.

[0057] FIG. 3A illustrates a cross-sectional view and FIG. 3B a top view of a composite alignment mark according to an embodiment.

[0058] FIG. 4 illustrates a cross-sectional view of a composite alignment mark according to an embodiment.

[0059] FIG. 5A illustrates a cross-sectional view and FIG. 5B a top view of a first portion of an alignment mark and FIG. 5C and FIG. 5D illustrates a cross-sectional view and top view, respectively, of the alignment mark after fabrication of the second portion of the composite alignment mark.

[0060] FIG. 6 illustrates a cross-sectional view of a semiconductor wafer according to an embodiment.

[0061] FIG. 7 illustrates a flow diagram of a method of fabricating a composite alignment mark on the front surface of a semiconductor wafer.

[0062] FIG. 8 illustrates a flow diagram of a method for fabricating a semiconductor wafer.

[0063] FIG. 9 illustrates a flow diagram of a method for fabricating a semiconductor component.

DETAILED DESCRIPTION

[0064] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, “leading”, “trailing”, etc., is used with reference to the orientation of the figure(s) being described. Because components of the embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, thereof, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0065] A number of exemplary embodiments will be explained below. In this case, identical structural features are identified by identical or similar reference symbols in the figures. In the context of the present description, “lateral” or “lateral direction” should be understood to mean a direction or extent that runs generally parallel to the lateral extent of a semiconductor material or semiconductor carrier. The lateral direction thus extends generally parallel to these surfaces or sides. In contrast thereto, the term “vertical” or “vertical direction” is understood to mean a direction that runs generally perpendicular to these surfaces or sides and thus to the lateral direction. The vertical direction therefore runs in the thickness direction of the semiconductor material or semiconductor carrier.

[0066] As employed in this specification, when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present.

[0067] As employed in this specification, when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0068] FIG. 1 illustrates a schematic view of a semiconductor wafer 10 according to an embodiment. the semiconductor wafer 10 comprises a front surface 11 and a plurality of active component positions 12 which are arranged in a regular array of rows and columns whereby a scribe line region 13 having a width w.sub.s is arranged laterally adjacent and between neighbouring ones of the active component positions 12. A plurality of the scribe lines 13 extend parallel to one another in the Y direction and a further plurality of the scribe lines 13 parallel to one another in the X direction to form a grid. The semiconductor wafer 10 may be formed of monocrystalline silicon or may comprise an epitaxial silicon layer formed on a monocrystalline substrate.

[0069] The semiconductor wafer 10 further comprises at least one composite alignment mark 14 arranged on the front surface 11 of the semiconductor wafer 10. The active component positions 12 each include a semiconductor device which is indicated schematically in FIG. 1 by the box 15. The active component positions 12 include device structures formed in the semiconductor material of the wafer 10 and may also include a metallisation structure arranged on the front surface 11 of the semiconductor wafer 10 in the active component positions 12, which are not illustrated in the schematically of FIG. 1. For example, the device may be a transistor device or a diode. In some embodiments, each component position includes more than one semiconductor device, for example a transistor and diode, whereby the two or more devices may be electrically coupled to one another to form a desired circuit.

[0070] The semiconductor wafer 10 may also include one or more dummy positions 16 which include an auxiliary or test device 46 which may be used for device testing or process control monitoring purposes. The wafer 10 also includes an inactive area 47 which is positioned outside of the active component positions 12, the dummy component positions 16 and the scribe line regions. The inactive area 47 is typically arranged towards the periphery of the semiconductor wafer 10.

[0071] One or more of the composite alignment marks 14 may be positioned in one or more of the scribe line regions 13, one or more of the dummy component positions 16, one or more of the active component positions 12 and in one or more locations on the inactive portion 47 of the semiconductor wafer 10.

[0072] The composite alignment mark 14 indicates a unique orientation of the semiconductor wafer 10 and may be used for aligning the semiconductor wafer 10 during various manufacturing steps to form the devices within the wafer, to perform process control during manufacture of the wafer as well as testing of the active devices and auxiliary devices in the dummy positions 16, for aligning the wafer prior to the singulation of the wafer along the scribe line regions 13 to separate the individual semiconductor dies from the semiconductor wafer 10 and/or for removing the dies from the singulated wafer during pick and place.

[0073] During the manufacturing of a semiconductor wafer, the wafer is positioned such that it has a desired position within a tool or apparatus. An initial orientation can be performed using a mechanical alignment method, for example a flat edge or notch formed in the wafer 10 may be mechanically aligned with a flat edge or protrusion in an apparatus. Then, the wafer 10 is aligned relative to the tool using the one or more composite alignment marks 14 formed on the front surface.

[0074] Generally, semiconductor devices fabricated by carrying out a sequence of processing steps to form the devices in the wafer and by depositing a stack of layers of differing materials, for example electrically insulating, dielectric, electrically conductive layers and patterning the layers to form a metallisation structure which provides the electrically conductive redistribution structure between the outermost contact surfaces and the semiconductor devices formed within the wafer. Each of these steps and layers is typically aligned to an underlying structure or layer using alignment marks, which may be formed on the wafer itself. The tools used to fabricate the semiconductor devices visually locate the alignment marks, whereby the position of these alignment marks is programmed into the tools. These multiple structures and layers should be aligned correctly in order for the devices to operate properly. Minimising alignment errors is helpful for ensuring that devices meet performance specifications and for achieving high yield and reliability. In the final processing stages, e.g. backend processing, the wafer 10 is aligned using the composite alignment mark 14 or marks so as to allow the tool to perform process control monitoring, align the diced wafer and remove pre-selected dies from the diced wafer using pick and place processes. Typically, the composite alignment marks are located using optical methods, for example an optical microscope.

[0075] FIG. 2A illustrates a cross-sectional view along the line A-A shown in FIG. 2B and FIG. 2B a plan view of a composite alignment mark 14 according to an embodiment. The composite alignment mark 14 is positioned on the front surface 11 of the semiconductor wafer 10. The composite alignment mark 14 comprises a first portion 17 which is formed of a first material and a second portion 18 which is formed of a second material which is different from the first material. The first and second portions 17, 18 are arranged laterally adjacent to one another on the front surface 11 of the wafer 10. In some embodiments, such as that illustrated in FIGS. 2A and 2B, the first portion 17 is formed of electrically conductive material such as a metal or alloy, for example an aluminium copper alloy and the second portion 18 is formed of electrically insulating material, such as polyimide.

[0076] As can be seen in the top view of FIG. 2B, the first portion 17 includes a first raised section 20 which has a shape which can be considered to be a 7 cross. The first raised section 20 includes a first leg 21 extending in a longitudinal or Y direction in the Cartesian coordinate system, a second leg 22 which extends substantially orthogonally to the first section 21 and in the X direction and intermediate the length of the first leg 22 to form a cross. A third leg 23 extends from distal end of the first leg 21 on one side only in the X direction and substantially parallel to the second leg 22 to form a 7 shape. The legs 21, 22, 23 of the first raised section 20 may each have substantially the same width and height. The first portion 17 includes a second raised section 24 which has the form of a closed border or frame which laterally surrounds and is spaced apart from the first raised section 20. The frame may have a square or rectangular form, with sections extending in the longitudinal Y direction that are connected by sections extending in the transverse Y direction. The sections of the frame 24 have substantially the same width and height on all four sides. As can be seen in the cross-sectional view of FIG. 2A, the raised sections 20, 24 have side faces 27 which extend substantially perpendicularly to the front surface 11 of the wafer 10.

[0077] The second portion 18 of the composite alignment mark 14 has a third raised section 25 that fills the regions of the front surface 11 between the first and second sections 20, 24 of the first portion 17. The second portion 18 also includes a fourth section 26 having the form of a frame which laterally surrounds the frame section 24 of the first portion 17. The frame 26 also has the form of a square or rectangular frame having substantially the same width on all sides. As can be seen in the cross-sectional view FIG. 2A, the side faces 27 of the first portion 17 and the side faces 27 of the second portion 18 touch one another and are contiguous. In this embodiment, the second portion 18 has a height which is slightly greater than the height of the first portion 17. The first portion 17 may be formed from a metallic layer of the metallisation structure formed on the devices formed in the component positions 16 and the second portion from an electrically insulating layer of the metallisation structure formed on the devices formed in the component positions 16, such as polyimide. The frame section 26 of the second portion 18 is laterally surrounded and bordered by further regions 32 of this metallic layer.

[0078] In this embodiment, the first raised section 20 of the first portion 17 is rotationally asymmetric about an axis which extends substantially perpendicularly to the front surface 11 of the wafer as indicated by the arrow 29 extending in the Z direction. The first raised section 20 can therefore be used to indicate a unique orientation of the wafer 10. The first raised section 25 of the second portion 18 has the complementary or inverse shape of the first raised section and also has a rotationally asymmetric shape and, therefore, also indicates a unique orientation of the wafer 10. The frames provided by the first raised section 24 of the first portion 17 and the fourth raised section 26 of the second portion 18 are rotationally symmetrical. The frame sections 24, 26 may be used for height adjustment if the dimensions of the fame sections 24, 26 are known.

[0079] The first and second material of the first and second portions 17, 18 of the composite alignment mark 14 are, therefore, selected so as to have a sufficient optical contrast between one another. For example, the optical contrast in the visible wavelength range should be sufficient to allow the location of the alignment mark by eye, or light microscope. If the first portion 17 alone is to be used as an alignment mark at an earlier stage of wafer production, the optical contrast between this material and the underlying surface of the semiconductor wafer, which may be the semiconductor material of the wafer 10 or another layer formed on the semiconductor wafer 10, such as a passivation layer, are selected to have sufficient optical contract.

[0080] FIG. 3A illustrates a cross sectional view of a composite alignment mark 14 according to another embodiment. FIG. 3B illustrates a top view of a portion of the composite alignment mark 14 shown in FIG. 2B, in particular, the region between the intersection of the distal end of the first leg 21 and the third leg 23 and the surrounding fame 24. In this embodiment, the composite alignment mark 14 has the same general form as that illustrated in FIG. 2A. In this embodiment, however, the second portion 18 is spaced apart from the first portion 17 by a gap 28 such that the side faces 27 of the raised sections 20, 24 of the first portion 17 are spaced apart from the side faces 27 of the raised sections 25, 26 of the second portion 18.

[0081] FIG. 4 illustrates a cross-sectional view of a composite alignment mark 14 according to another embodiment which has the same shape general shape in the top view as illustrated in FIG. 2B. In this embodiment, the second portion 18 overlaps the peripheral regions 29 of the top surface 30 of the first portion 17. The central regions 31 of the upper surface 30 of the raised sections 20, 24 of the first portion 17 remain uncovered by the material of the second portion 18. The exposed regions 31 of the first portion 17 and of the second portion 18 have a shape that corresponds to the general shape of the first and second portion 17, 18 shown in FIG. 2B and indicate a unique orientation of the composite alignment mark 14 and of the semiconductor wafer 10.

[0082] FIGS. 5A through 5D illustrate the fabrication of the composite alignment mark 14 of FIGS. 2A and 2B, where FIG. 5A illustrates a cross-sectional view along the line A-A shown in FIG. 5B and FIG. 5B a top view after fabrication of the first portion 17 of the composite alignment mark 14. FIG. 5C and FIG. 5D illustrates a cross-sectional view along the line A-A of FIG. 5D and top view, respectively, of the composite alignment mark 14 after fabrication of the second portion 18 of the composite alignment mark 14.

[0083] The first portion 17 of the composite alignment mark 14 is formed by depositing a first layer, which may be formed of one or more metallic layers, for example a layer of an aluminium copper alloy, and structuring this first layer to form the first raised section 20 and the second raised section 24 by removing portions of the first layer. The first layer may be structured by laser ablation, wet etching or plasma etching, for example. The peripheral edge regions 32 of the first layer that are positioned laterally adjacent the composite alignment mark 14 can also be seen in FIGS. 5A and 5B. The first portion 17 of the composite alignment mark 14 has a shape which indicates a unique orientation of the semiconductor wafer since the first raised section 20 has a shape which is asymmetrical about the axis 19 which extends substantially perpendicularly to the front surface 11 of the wafer 10, for example the 7-cross shape shown in FIG. 2B. The first section 20 of the composite alignment mark 14 may itself be used for alignment purposes before completion of the fabrication of the composite alignment mark 14 by depositing the second portion 18.

[0084] FIGS. 5C and 5D illustrate that, subsequently, a second layer of a different material, for example an electrically insulating material such as polyimide, is deposited which fills the regions between the first and second sections 20, 24 of the first portion and the gap 33 between the second section 24 and the peripheral regions 32 of the surrounding regions of the first layer. This gap 33 may have a substantially uniform width and provide the frame 26 formed of the second material. The second layer may be deposited such that it covers the upper surface of the first and second sections 20, 24 and is subsequently structured by removing the portions of the second layer which are positioned on the upper surface of the first portion 17 to form the laterally separate sections 25, 26 of the second portion 18 of the composite alignment mark 14. The second layer may be structured using photolithographic techniques, for example. In some embodiments, in the composite alignment mark 14, the second layer has a height which is greater than the height of the first layer, as can be seen in the cross-sectional view of FIG. 5C, since it initially covered the upper surface of the first portion 17.

[0085] The composite alignment mark 14 may be formed from layers which form part of the active devices formed in the active component positions 12. FIG. 6 illustrates a cross-sectional view showing an active component position 12 of the semiconductor wafer 10 which is laterally surrounded by scribe line regions 13 along which the wafer 10 will be diced to form a cuboid semiconductor die including an active device 15 from each component active component position 12. The first and second portions 17, 18 of the composite alignment mark 14 are formed from layers of the first metallisation structure 34 which is formed on the front surface 11 of the wafer 10. The frontside metallisation structure 34 typically includes one or more electrically conductive layers formed of a metal or alloy and one or more electrically insulating layers.

[0086] In the embodiment illustrated in FIG. 6, the frontside metallisation comprises a layer 35 formed of an aluminium copper alloy and a copper layer 36 which is positioned on the aluminium copper layer and which provides a source pad 37 and gate pad 38 for a vertical transistor device 39 formed in the active component position 12. A drain pad 40 is arranged on the rear surface 41 of the wafer, the rear surface 41 opposing the front surface 11. The metallisation structure 34 may include further conductive layers, for example, tungsten or a titanium or titanium nitride layers which are arranged between the aluminium copper layer 35 and the transistor device 39.

[0087] A polyimide layer 42 of the frontside metallisation structure 34 is positioned on the front surface 11 of the semiconductor wafer 10 such that it extends over peripheral regions of the portions of the aluminium copper layer 35 providing the source pad 37 and gate pad 38 and extends over the semiconductor material and over the scribe line regions 13. For semiconductor dies which are to be mounted in a source down arrangement, for example, in a can type package, the peripheral regions of the semiconductor dies, formed by the portions of the scribe line regions 13 that are not removed during dicing, are entirely covered by the polyimide layer 42. Consequently, the polyimide layer 42 extends over the entire width w.sub.s of the scribe line regions 13 of the semiconductor wafer 10. In FIG. 6, the composite alignment mark 14 is located in one of the scribe line regions 13 and is formed from the aluminium copper layer 36 and the polyimide layer 42. The outermost surface 43 of the second portion 18 of the composite alignment mark 14 is, therefore, positioned at a distance from the front surface 11 of the semiconductor wafer 10 which is less than the outermost surface 44 of the copper layer of the source pad 37 and gate pad 38. The upper surface of the first portion 17 of the composite alignment mark 14 is positioned at a distance from the front surface 11 that is less than the distance tween the upper surface 43 of the second portion 18 from the front surface 11. The composite alignment mark 14 may be located at other positions on the front surface 11, for example in a dummy component position, in an inactive region 47 or in an active component position 12.

[0088] FIG. 7 illustrates a flow diagram 50 of a method of fabricating a composite alignment mark. In box 51, a first layer of a first material is deposited onto a front surface of the semiconductor wafer that comprises a plurality of active component positions. In box 52, a first portion of at least one composite mask is formed in the first layer. The first portion of the at least one composite alignment mark has at least one raised section formed of the first material and has a shape which indicates a unique orientation of the wafer. The first portion may be formed from the first layer by structuring and removing regions of the first layer by laser ablation or by etching. In other embodiments the first material is selectively deposited to form the at least one raised section formed of the first material. The first and second materials should have an optical contrast that enables them to be discerned optically, for example in the visible wavelength range.

[0089] In box 53, a second layer is deposited on the first layer, whereby the second layer comprises a second material that differs from the first material. For example, the first material may be a metal or an alloy and the second material be electrically insulating material. The first and second layers may each also be formed of sublayers having different compositions, for example the first layer may be formed of two or more metallic sublayers and the second layer be formed or two or more electrically insulating sublayers.

[0090] In box 54, the second layer is structured to form a second portion of the composite alignment mark. The second portion comprises at least one raised section formed of the second material. The second layer is structured so as to expose at least part of the one or more raised sections formed of the first material in order to form the composite alignment mark comprising the first and second portions of differing materials, which are arranged laterally adjacent one another on the front surface of the wafer. This composite alignment mark indicates the unique orientation of the wafer.

[0091] In some embodiments, the first layer may be structured to form one or more contact pads in the active component positions of the semiconductor wafer, for example, a source pad and/or a gate pad for a vertical transistor device formed in the active component positions. The second layer may be further structured to expose at least regions of the gate pad and/or source pad.

[0092] FIG. 8 illustrates a flow diagram 60 of a method for fabricating a semiconductor wafer. In box 61, a first layer of a first material is deposited onto the front surface of the semiconductor wafer and a first portion of at least one composite alignment mark is formed in the first layer. One or more portions of the frontside metallisation structure for a device positioned within the active component positions of the semiconductor wafer are also formed from the first layer, for example contact pads or parts of the redistribution structure for the device. The first layer may be formed of metal or alloy or may include two or more sublayers, each sublayer being formed of metal or alloy. The first portion of each of the composite alignment marks has a shape which is capable of indicating a unique orientation of the semiconductor wafer.

[0093] In box 62, the wafer is aligned using the first portion of the at least one composite alignment mark. After alignment of the semiconductor wafer, one or more parameters of a device formed in the semiconductor wafer is tested. The device may be formed in the one of the active component positions or may be a test structure or auxiliary structure formed in the semiconductor wafer. A test or auxiliary structure may be formed in the scribe line region, an active component position, a dummy component position or an inactive portion of the semiconductor wafer.

[0094] In box 64, the method continues by depositing a second layer of a second material that is different from the first material onto the front surface of the semiconductor wafer and forming a second portion of the at least one composite alignment mark. The second layer may be formed of an electrically insulating material and deposited in the form of a closed layer which is then structured, by removing portions of the closed electrically insulating layer to expose some or all of the first portion of the at least one composite alignment mark. The second layer may also form part of the front side metallization structure formed in the active component portions and also be structured to expose one or more contact pads of the active device devices formed in the active component positions.

[0095] In box 65, the wafer is aligned using the least one composite alignment mark which is formed from the first and second portions of differing material and in box 66, a parameter of a device formed in the semiconductor wafer is tested. The device may be an active device formed in one of the active component positions or a test or auxiliary structure. The device to be tested may be formed in one of the active component positions, the scribe line region, dummy component position or an inactive portion of the semiconductor wafer. The device which is tested after formation of the second layer may be the same or different from the device which is tested after the formation of the first portion of the composite alignment mark. The first and second materials are selected so as to provide sufficient optical contrast between the first material and the semiconductor wafer and between the first and second materials.

[0096] FIG. 9 illustrates a flow diagram 70 of a method for fabricating a semiconductor component. in box 71, the semiconductor wafer with at least one composite alignment mark formed on its front surface is aligned using at least one of the composite alignment marks. The wafer of any one of the embodiments described herein may be used. The wafer may be fabricated using any one of the methods described herein, for example as described with reference to FIGS. 5A-5D, 7 or 8. In box 72, the semiconductor dies are singulated from the semiconductor wafer by cutting through the wafer in the scribe line regions. in box 73, an individual die is removed from the singulated wafer and in box 74 the individual die is mounted on a support structure of a semiconductor package.

[0097] The wafer may be realigned using one or more of the composite alignment marks after singulation and before removal of the dies. Additionally, the wafer may be realigned after some of the dies have been removed from the singulated wafer. In these embodiments, one or more composite alignment marks are located in regions of the wafer that are not removed during singulation. For example, one or more composite alignment marks may be located in one or more dummy component positions that are distributed across the area of the wafer.

[0098] In some embodiments, the support structure may be a metal can and the semiconductor die provide a vertical transistor device, which has a drain contact on its rear side and a source pad and gate pad on its opposing surface front surface. The drain contact is mounted on and electrically coupled to the base of the can and the source pad and the gate pad on the opposing surface front surface are substantially coplanar with the peripheral rim of the can. In other embodiments, the support structure may be a die pad of a metallic leadframe for a leaded or leadless package, or may be a die pad having the form of an electrically conductive layer formed on a redistribution structure such as a circuit board. In other embodiments, the semiconductor die may be packaged using chip embedding techniques.

[0099] Spatially relative terms such as “under”, “below”, “lower”, “over”, “upper” and the like are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first”, “second”, and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

[0100] As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

[0101] The expression “and/or” should be interpreted to include all possible conjunctive and disjunctive combinations, unless expressly noted otherwise. For example, the expression “A and/or B” should be interpreted to mean only A, only B, or both A and B. The expression “at least one of” should be interpreted in the same manner as “and/or”, unless expressly noted otherwise. For example, the expression “at least one of A and B” should be interpreted to mean only A, only B, or both A and B.

[0102] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.