Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the semiconductor device are included. The method of manufacturing the semiconductor device includes forming a hafnium oxide layer on a substrate and crystallizing the hafnium oxide layer by using a hafnium cobalt oxide layer as a seed layer. According to the method of manufacturing the semiconductor device, a thin-film hafnium oxide layer may be easily crystallized.

Claims

1. A semiconductor device in which a field effect transistor and a capacitor are electrically connected, wherein the field effect transistor comprises a semiconductor layer which includes a source and a drain, a dielectric layer on the semiconductor layer, and a gate electrode on the dielectric layer, wherein the capacitor comprises a first electrode, a second electrode disposed to be spaced apart from the first electrode, a hafnium oxide (HfOx) layer crystallized and disposed between the first electrode and the second electrode, and a seed layer on the hafnium oxide layer, wherein the seed layer comprises a hafnium cobalt oxide (HfCoOx) or hafnium silicon oxide (HfSiOx), and wherein the hafnium oxide layer has a permittivity in a range from about 30 to about 70.

2. The semiconductor device of claim 1, wherein the hafnium oxide layer further comprises ZrO2 or Al2O3.

3. The semiconductor device of claim 1, wherein the hafnium oxide layer has a thickness equal to or less than 7 nm.

4. The semiconductor device of claim 1, wherein the seed layer has a thickness equal to or less than 3 nm.

5. The semiconductor device of claim 1, wherein at least one of the first or second electrodes comprises at least one material selected from the group consisting of Al, Si, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, BaHf, Ta, W, Re, Os, Ir, Pt, and Au or a material including the at least one material and a nitride or an oxide.

6. The semiconductor device of claim 1, wherein the hafnium oxide layer is crystallized in an orthorhombic phase or a tetragonal phase.

7. The semiconductor device of claim 1, further comprising: a silicon dioxide layer between the first electrode and the hafnium oxide layer.

8. The semiconductor device of claim 1, wherein the seed layer further includes at least one material selected from the group consisting of Be, B, Na, Mg, Al, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U.

9. The semiconductor device of claim 1, wherein the seed layer has a cobalt content of 10% or less.

10. A dynamic random access memory (DRAM) comprising the semiconductor device of claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) These and/or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings in which:

(2) FIG. 1 is a schematic view illustrating a semiconductor device according to an embodiment;

(3) FIG. 2 illustrates an example in which a silicon dioxide layer is further included in the semiconductor device illustrated in FIG. 1;

(4) FIG. 3 is an atom density graph according to a sputtering time with respect to the semiconductor device illustrated in FIG. 1;

(5) FIG. 4 shows a variation in an intensity of a hafnium oxide layer having a thickness or 6 nm and a hafnium oxide layer having a thickness of 10 nm, according to a diffraction angle in an X-ray diffraction analysis method;

(6) FIG. 5 is a schematic view of a semiconductor device according to another embodiment;

(7) FIG. 6 is a transmission electron microscopic image of a layer structure including a TiN layer, a crystallized HfO.sub.2 layer, a HfCoOx layer, and a top electrode;

(8) FIG. 7 shows a permittivity of HfO.sub.2 according to a thickness of HfO.sub.2 in the layer structure illustrated in FIG. 6;

(9) FIG. 8 illustrates a semiconductor device according to another embodiment;

(10) FIG. 9 is a transmission electron microscopic image of a layer structure including a silicon substrate, a SiO.sub.2 layer, and a HfO.sub.2 layer;

(11) FIG. 10 shows a variation in an intensity of the layer structure illustrated in FIG. 9 according to a diffraction angle in an X-ray diffraction analysis method; and

(12) FIG. 11 illustrates a method of manufacturing a semiconductor device, according to an embodiment.

DETAILED DESCRIPTION

(13) Hereinafter, a semiconductor device and a manufacturing method thereof according to various embodiments will be described more fully with reference to the accompanying drawings. In the drawings, like elements are labeled like reference numerals, and the sizes of elements in the drawings may be exaggerated for clarity and convenience of description. While such terms as “first,” “second,” etc., may be used to describe various elements, such elements must not be limited to the above terms. The above terms are used only to distinguish one element from another.

(14) An expression used in the singular form encompasses the expression in the plural form, unless it has a clearly different meaning in the context. It will also be understood that when a component “includes” an element, unless there is another opposite description thereto, it should be understood that the component does not exclude another element but may further include another element. Also, in the drawings, for clarity of description, sizes or thicknesses of elements may be exaggerated. Also, it will also be understood that when a material layer is referred to as being “on” another substrate or layer, it can be directly on the other substrate or layer, or intervening layers may also be present. In addition, materials constituting each layer in the embodiments below are exemplary, and other materials than the described ones may also be used.

(15) FIG. 1 is a schematic view illustrating a semiconductor device 100 according to an embodiment.

(16) The semiconductor device 100 may include a substrate 110, a hafnium oxide (HfOx) layer 120 that is crystallized and provided on the substrate 110, and/or a hafnium cobalt oxide (HfCoOx) layer 130 provided on the hafnium oxide layer 120. Alternatively, cobalt may be diffused in the hafnium oxide layer 120. The hafnium oxide (HfOx) layer 120 may be another Group IV oxide, for example, TiO.sub.2 or ZrO.sub.2 or may also be a Group III oxide, for example, Sc.sub.2O.sub.3 or Y.sub.2O.sub.3, or combinations thereof.

(17) The substrate 110 may include, for example, at least one material selected from the group consisting of Al, Si, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, BaHf, Ta, W, Re, Os, Ir, Pt, and Au or may further include a nitride or an oxide in addition to the at least one material.

(18) The hafnium oxide layer 120 may include a crystal phase. For example, the hafnium oxide layer 120 may include an orthorhombic phase or a tetragonal phase. The hafnium oxide layer 120 may include, for example, hafnium dioxide (HfO.sub.2).

(19) The hafnium oxide layer 120 may have, for example, a thickness equal to or less than 7 nm. The hafnium oxide layer 120 may have a high permittivity when the hafnium oxide layer 120 has a thickness of 7 nm or less and is crystallized, and may be applied as a high-k layer to a ferroelectric field effect transistor.

(20) The hafnium oxide layer 120 may have a higher permittivity by further including, for example, ZrO.sub.2 or Al.sub.2O.sub.3.

(21) The hafnium cobalt oxide layer 130 may have, for example, a thickness equal to or less than 3 nm. The hafnium cobalt oxide layer 130 may have a cobalt content of 10% or less. The hafnium cobalt oxide layer 130 may include a hafnium cobalt oxide compound. The hafnium cobalt oxide compound may be a compound including HfCoOx and at least one selected from the group consisting of Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U.

(22) FIG. 2 illustrates an example in which a layer is further included in the semiconductor device illustrated in FIG. 1.

(23) A semiconductor device 100A may further include a silicon dioxide (SiO.sub.2) layer 115 between the substrate 110 and the hafnium oxide layer 120. For example, when the substrate 110 is a silicon substrate, the semiconductor device 100A may be applied to a metal oxide semiconductor (MOS) device.

(24) FIG. 3 is an atom density graph according to a sputtering time with respect to the semiconductor device 100 illustrated in FIG. 1, obtained through X-ray photoelectron spectroscopy (XPS). That is, FIG. 3 shows a result of atom density analysis performed on each layer of the semiconductor device 100.

(25) Referring to FIG. 3, a hafnium cobalt oxide layer and a hafnium oxide layer are included, and the hafnium oxide layer has a thickness of about 6 nm.

(26) FIG. 4 shows a variation in an intensity of a hafnium oxide layer having a thickness or 6 nm and a hafnium oxide layer having a thickness of 10 nm, according to a diffraction angle in an X-ray diffraction analysis (XRD) method. The graphs respectively show variations in intensities of HfO.sub.2 10 nm/HfCoOx 1 nm, HfO.sub.2 10 nm/HfCoOx 0 nm, HfO.sub.2 6 nm/HfCoOx 1 nm, and HfO.sub.2 6 nm/HfCoOx 0 nm. In a crystallized hafnium oxide layer, one peak value occurs at an angle of approximately 30 degrees. That is, in HfO.sub.2 6 nm/HfCoOx 1 nm, a peak value occurs at approximately 30 degrees, whereas in HfO.sub.2 10 nm/HfCoOx 1 nm, HfO.sub.2 10 nm/HfCoOx 0 nm, and HfO.sub.2 6 nm/HfCoOx 0 nm, a peak value does not occur at approximately 30 degrees but at an angle deviating from 30 degrees or multiple peak values occur. This indicates that a thin-film hafnium oxide layer having a thickness of 6 nm is orthorhombic-crystallized or tetragonally crystallized due to the hafnium cobalt oxide layer.

(27) Also, when the hafnium oxide layer has a thickness of 10 nm or there is no hafnium cobalt oxide layer, crystallization is not properly performed, but the hafnium oxide layer has monoclinic crystallinity. In the graphs, “m” indicates monoclinic crystallinity, “t” denotes tetragonal crystallinity, and “o” indicates orthorhombic crystallinity.

(28) FIG. 5 is a schematic view of a semiconductor device 200 according to another embodiment.

(29) The semiconductor device 200 may include a substrate 210, a hafnium oxide layer 220, and a hafnium cobalt oxide layer 230, and/or a top electrode 240. The substrate 210 may include, for example, a conductive material, and act as a bottom electrode. The substrate 210 may include, for example, TiN or AlN, but is not limited thereto. The hafnium cobalt oxide layer 230 may include a hafnium cobalt oxide compound. The hafnium cobalt oxide compound may be a compound including HfCoOx and at least one material selected from the group consisting of Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U.

(30) The top electrode 240 may include, for example, at least one material selected from the group consisting of Al, Si, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, BaHf, Ta, W, Re, Os, Ir, Pt, and Au or may further include a nitride or an oxide in addition to the at least one material. However, the top electrode 240 is not limited thereto. As described above, the semiconductor device 200 may include the substrate 210 operating as an electrode and the top electrode 240 and applied to a metal insulator metal (MIM) capacitor.

(31) FIG. 6 is a transmission electron microscopic image of a layer structure including a crystallized HfO.sub.2 layer, a HfCoOx layer, and a top electrode. The crystallized HfO.sub.2 layer has a thickness of approximately 6 nm.

(32) FIG. 7 shows a permittivity of HfO.sub.2 according to a thickness of HfO.sub.2 in the layer structure illustrated in FIG. 6. The white triangles indicate a TiN/HfO.sub.2/TiN layer structure, and the black triangles indicate a TiN/HfO.sub.2/HfCoOx/TiN layer structure. In the TiN/HfO.sub.2/TiN layer structure, a permittivity of HfO.sub.2 having a thickness of 6 nm is relatively low, and in the TiN/HfO.sub.2/HfCoOx/TiN layer structure, a permittivity of HfO.sub.2 having a thickness of 6 nm is relatively high. For example, HfO.sub.2 of the semiconductor device according to the embodiment may have a permittivity in a range from about 30 to about 70.

(33) FIG. 8 illustrates a semiconductor device according to another embodiment.

(34) A semiconductor device 300 may include a substrate 310, a silicon dioxide layer (SiO.sub.2) 315, and a crystallized hafnium oxide layer 320, and/or an electrode 340. The substrate 310 may include, for example, a semiconductor substrate. For example, the substrate 310 may include silicon (Si) or germanium (Ge). The electrode 340 may include at least one material selected from the group consisting of Al, Si, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, BaHf, Ta, W, Re, Os, Ir, Pt, and Au or a material including the at least one material and a nitride or an oxide. However, the semiconductor device 300 is not limited thereto. As described above, the semiconductor device 300 may include the substrate 310 and the electrode 340 and may be applied to a MOS capacitor.

(35) FIG. 9 is a transmission electron microscopic image of a layer structure including a silicon substrate, a SiO.sub.2 layer, and/or an HfO.sub.2 layer. The HfO.sub.2 layer has a thickness of approximately 5 nm.

(36) FIG. 10 shows a variation in an intensity of the layer structure illustrated in FIG. 9 according to a diffraction angle in an X-ray diffraction analysis method. #1 indicates a variation in an intensity of a structure after being heat-treated when HfCoOx is not present; #2 indicates a variation in an intensity of a structure after being heat-treated when HfCoOx is present. In the layer structure of #2, a peak value occurs at around 30 degrees, indicating that HfO.sub.2 is crystallized in the layer structure of #2. In the graph of FIG. 10, “m” indicates monoclinic crystallization and “t” denotes tetragonal crystallization.

(37) The semiconductor device according to the various embodiments including a hafnium oxide layer having a tetragonal phase may be applied to a high-k capacitor for dynamic random access memories (DRAMs). Also, the semiconductor device according to the various embodiments including a hafnium oxide layer having an orthorhombic phase may be applied to a ferroelectric field effect transistor (Fe-FET) via a ferroelectric HfO.sub.2 thin film.

(38) FIG. 11 illustrates a method of manufacturing a semiconductor device, according to an embodiment. The method of manufacturing a semiconductor device will be described with reference to FIGS. 1 and 11.

(39) According to the method of manufacturing a semiconductor device, a hafnium oxide (HfOx) layer 120 is formed on a substrate 110 (S100). The hafnium oxide layer 120 may be formed using, for example, an atomic layer deposition method. The substrate 110 may include at least one material selected from the group consisting of Al, Si, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, BaHf, Ta, W, Re, Os, Ir, Pt, and Au or a material including the at least one material and a nitride or an oxide. The hafnium oxide layer 120 may have, for example, a thickness equal to or less than 7 nm.

(40) A hafnium cobalt oxide (HfCoOx) layer 130 may be formed on the hafnium oxide layer 120 (S200). The hafnium cobalt oxide layer 130 may have a thickness of, for example, 3 nm or less. The hafnium cobalt oxide layer 130 may have a cobalt content of 10% or less.

(41) The hafnium oxide layer 120 may be crystallized using a heat treatment process (S300). In an embodiment, the hafnium cobalt oxide layer 130 may act as a seed layer to crystallize the hafnium oxide layer 120. A hafnium oxide has a stable monoclinic phase and is thus more difficult crystallize orthorhombically or tetragonally. Crystallization of a hafnium oxide layer into orthorhombic crystals or tetragonal crystals has been tried using a doping and thin film process, but it is difficult to obtain a layer having a thickness of 7 nm or less by the doping and thin film process. A heat treatment process may be performed, for example, at a temperature equal to or higher than 400 degrees or equal to or lower than 1000 degrees. A hafnium cobalt oxide layer may also be removed after crystallization. Also, an electrode may be further formed on a hafnium cobalt oxide layer.

(42) According to the method of manufacturing a semiconductor device of the various embodiments, a thin-film hafnium oxide layer may be crystallized by using a hafnium silicon oxide layer as a seed, and a ferroelectric HfO.sub.2 thin film may be manufactured therefrom. A Fe-FET device or a MIM capacitor may be manufactured by using the ferroelectric HfO.sub.2 thin film.

(43) It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments.

(44) While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.