Semiconductor Integrated Circuit

Abstract

A second protective film is formed on and in contact with a first protective film, and is formed to cover the first protective film. The second protective film is also formed so that an end portion extending toward the center of a first opening is interposed between a wiring line and a bonding pad at the edge portion of the bonding pad.

Claims

1. A semiconductor integrated circuit comprising: a substrate that is formed with a semiconductor; a circuit element formation region that is formed on the substrate, and includes an element formed with a semiconductor; a wiring line that is drawn from the circuit element formation region onto the substrate in a pad formation region around the circuit element formation region; a first protective film that covers the circuit element formation region, has a first opening formed in the pad formation region, and is formed with an organic material; a bonding pad that has a smaller area than the first opening in a planar view, is formed on the wiring line on an inner side of the first opening, and is connected to the wiring line; and a second protective film that is in contact with the first protective film to cover the first protective film, has an end portion extending toward a center of the first opening between the wiring line and the bonding pad at an edge portion of the bonding pad, has a second opening that is formed on the inner side of the first opening and has the end portion as an edge, and is formed with an inorganic material.

2. The semiconductor integrated circuit according to claim 1, wherein, in a region of the second opening, the bonding pad is formed in contact with the wiring line.

3. The semiconductor integrated circuit according to claim 1, wherein, in a region in which the end portion extends between the wiring line and the bonding pad, the wiring line, the second protective film, and the bonding pad are stacked in this order from a side of the substrate.

4. The semiconductor integrated circuit according to claim 1, wherein the second protective film includes the end portion, a sidewall portion that is formed on a sidewall of the first opening of the first protective film and continues from the end portion, and an upper layer portion formed on the first protective film.

5. The semiconductor integrated circuit according to claim 1, further comprising a film that is formed between the bonding pad and the wiring line, and the first protective film, the film being provided to enhance adhesion to each.

6. The semiconductor integrated circuit according to claim 1, wherein the wiring line is formed with metal, and the bonding pad is formed with metal.

7. The semiconductor integrated circuit according to claim 2, wherein, in a region in which the end portion extends between the wiring line and the bonding pad, the wiring line, the second protective film, and the bonding pad are stacked in this order from a side of the substrate.

8. The semiconductor integrated circuit according to claim 2, wherein the second protective film includes the end portion, a sidewall portion that is formed on a sidewall of the first opening of the first protective film and continues from the end portion, and an upper layer portion formed on the first protective film.

9. The semiconductor integrated circuit according to claim 3, wherein the second protective film includes the end portion, a sidewall portion that is formed on a sidewall of the first opening of the first protective film and continues from the end portion, and an upper layer portion formed on the first protective film.

10. The semiconductor integrated circuit according to claim 2, further comprising a film that is formed between the bonding pad and the wiring line, and the first protective film, the film being provided to enhance adhesion to each.

11. The semiconductor integrated circuit according to claim 3, further comprising a film that is formed between the bonding pad and the wiring line, and the first protective film, the film being provided to enhance adhesion to each.

12. The semiconductor integrated circuit according to claim 4, further comprising a film that is formed between the bonding pad and the wiring line, and the first protective film, the film being provided to enhance adhesion to each.

13. The semiconductor integrated circuit according to claim 2, wherein the wiring line is formed with metal, and the bonding pad is formed with metal.

14. The semiconductor integrated circuit according to claim 3, wherein the wiring line is formed with metal, and the bonding pad is formed with metal.

15. The semiconductor integrated circuit according to claim 4, wherein the wiring line is formed with metal, and the bonding pad is formed with metal.

16. The semiconductor integrated circuit according to claim 5, wherein the wiring line is formed with metal, and the bonding pad is formed with metal.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0014] FIG. 1A is a cross-sectional view illustrating a partial configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

[0015] FIG. 1B is a plan view illustrating a partial configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

[0016] FIG. 1C is a plan view illustrating the configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

[0017] FIG. 2 is a cross-sectional view illustrating a partial configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

[0018] FIG. 3 is a cross-sectional view illustrating a partial configuration of a semiconductor integrated circuit including bonding pads.

DESCRIPTION OF EMBODIMENTS

[0019] The following is a description of a semiconductor integrated circuit according to an embodiment of the present invention, with reference to FIGS. 1A, 1B, and 1C. FIG. 1A illustrates a cross-section taken along the line aa′ defined in FIG. 1C.

[0020] First, this semiconductor integrated circuit includes a substrate 101 formed with a semiconductor, and a circuit element formation region 121 including an element formed with a semiconductor is formed on the substrate 101. The circuit element formation region 121 includes a transistor formed with a semiconductor, a thin-film resistor, an MIM capacitor, a metal wiring line, an interlayer insulating film, and the like, for example. The semiconductor can be a group III-V compound semiconductor, for example. On the substrate 101, pad formation regions 122 are also formed around the circuit element formation region 121.

[0021] Further, wiring lines 102, a first protective film 103, bonding pads 104, and a second protective film 105 are formed on the substrate 101.

[0022] The wiring lines 102 are drawn from the circuit element formation region 121 onto the substrate 101 in the pad formation regions around the circuit element formation region 121. The wiring lines 102 are formed with a metal such as Au, for example. Also, the wiring lines 102 can be a metal multilayer structure in which the line on the side of the substrate 101 is formed with Au, and the uppermost layer is formed with Ti.

[0023] The first protective film 103 is formed with an organic material such as polyimide or benzocyclobutene (BCB), for example, and is formed to cover the circuit element formation region 121. The first protective film 103 also has first openings 103a in the pad formation regions 122.

[0024] The bonding pads 104 are formed on the wiring lines 102 inside the first openings 103a with an area smaller than that of the first openings 103a in a planar view. The bonding pads 104 are also connected to the wiring lines 102.

[0025] The second protective film 105 is formed on and in contact with the first protective film 103, and is formed to cover the first protective film 103. The second protective film 105 is also formed so that end portions 106 extending toward the centers of the first openings 103a are interposed between the wiring lines 102 and the bonding pads 104 at the edge portions of the bonding pads 104. Further, the second protective film 105 has second openings 105a that are formed on the inner sides of the first openings 103a and have the end portions 106 as the edges. The second protective film 105 also includes the end portions 106, sidewall portions 107 that are formed on the sidewalls of the first openings 103a of the first protective film 103 and continue from the end portions 106, and an upper layer portion 108 formed on the first protective film 103. Further, the second protective film 105 is formed with an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride, for example.

[0026] Also, in this semiconductor integrated circuit, the bonding pads 104 are formed on and in contact with the wiring lines 102 in the regions of the second openings 105a. Further, in the regions where the end portions 106 are interposed between the wiring lines 102 and the bonding pads 104, the wiring lines 102, the second protective film 105, and the bonding pads 104 are stacked in this order from the side of the substrate 101. As described above, since the bonding pads 104 are formed on the end portions 106 of the second protective film 105, peeling of the second protective film 105 can be prevented.

[0027] Manufacturing of the semiconductor integrated circuit according to the above-described embodiment is now briefly described. First, the wiring lines 102 are formed on the substrate 101 on which an element formed with a semiconductor is formed. For example, the wiring lines 102 can be formed by an electrode material deposition technique, a photolithography technique, and an etching technique that are well known.

[0028] Next, the first protective film 103 is formed on the substrate 101 so as to cover the wiring lines 102. In the first protective film 103, the first openings 103a are formed in the regions including the bonding regions. For example, a photosensitive organic material formed with polyimide, BCB, or the like is applied onto the substrate 101 by a coating method such as spin coating, to form a coating film. Next, patterning is performed on the formed coating film. After that, the coating film subjected to the patterning is cured by heating or the like, and thus, the first protective film 103 can be formed.

[0029] Next, the second protective film 105 is formed to cover the first protective film 103. For example, an inorganic insulating material such as silicon nitride or silicon oxynitride is deposited on the entire region of the substrate 101 by a known deposition method such as a plasma CVD method, to form an inorganic insulating film. Patterning is then performed on the inorganic insulating film by a photolithography technique and an etching technique, to form the second openings 105a. Thus, the second protective film 105 can be obtained.

[0030] Next, the bonding pads 104 are formed. For example, the bonding pads 104 can be formed by a known electrolytic plating technique or the like.

[0031] In the semiconductor integrated circuit according to the above-described embodiment, a path between a bonding pad 104 and a sidewall portion 107, a path between the bonding pad 104 and an end portion 106, and a path between the end portion 106 and a wiring line 102 serve as the penetration path of moisture reaching the first protective film 103, as indicated by a bold line in FIG. 2. As described above, according to the embodiment, the area of contact (close contact) between the second protective film 105 formed with an inorganic insulating material and the bonding pad 104 formed with a metal is larger. Further, according to the embodiment, the penetration path of moisture also includes the path between the second protective film 105 and the wiring line 102. In view of these, penetration of moisture reaching the first protective film 103 can be prevented more effectively than in conventional cases.

[0032] Also, if a sufficiently large contact area is secured between the lower surface of the bonding pad 104 and the upper surface of the wiring line 102, the opening area of the second opening 105a can be made smaller, the end portion 106 can be made closer to the center of the first opening 103a, and the above-described contact area can be made even larger. Meanwhile, the area of the upper surface of the bonding pad 104 does not change, regardless of the opening area of the second opening 105a. Thus, according to the embodiment described above, penetration of moisture in the bonding pad 104 can be prevented, without a reduction of the bonding region.

[0033] Also, in the semiconductor integrated circuit according to the embodiment, a film (a layer) for enhancing the adhesion between the respective components can be formed between the bonding pad 104 and the sidewall portion 107, between the bonding pad 104 and the end portion 106, and between the end portion 106 and the wiring line 102. The film for enhancing adhesion can be formed with Ti or a metal containing Ti, for example. In this manner, the adhesion between the bonding pad 104/the wiring line 102 and the first protective film 103 formed with an organic material can be further enhanced. Thus, penetration of moisture into the bonding pad 104 can be further prevented.

[0034] As described above, according to the present invention, end portions of the second protective film formed to cover the first protective film are inserted between the wiring lines and the bonding pads. Thus, it becomes possible to prevent penetration of moisture into the bonding pads by preventing a reduction of the bonding regions. According to the present invention, it is possible to prevent moisture from reaching the circuit element formation region and hindering circuit operations. Also, according to the present invention, there is no need to make the areas of the bonding pads larger, even though sufficiently large bonding region are secured. Thus, it becomes possible to miniaturize and highly densely integrate the semiconductor integrated circuit. As a result, it becomes possible to reduce the cost and size by adopting plastic packaging.

[0035] Note that the present invention is not limited to the embodiment described above, and it is obvious that many modifications and combinations can be implemented by a person having ordinary knowledge in the art within the technical idea of the present invention.

REFERENCE SIGNS LIST

[0036] 101 substrate [0037] 102 wiring line [0038] 103 first protective film [0039] 103a first opening [0040] 104 bonding pad [0041] 105 second protective film [0042] 105a second opening [0043] 106 end portion [0044] 107 sidewall portion [0045] 108 upper layer portion [0046] 121 circuit element formation region [0047] 122 pad formation region