Architectures for storing and retrieving system data in a non-volatile memory system

Abstract

Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system. Using these embodiments, system data is much less likely to become corrupted due to charge loss, charge redistribution, disturb effects, and other phenomena that have caused corruption in prior art non-volatile memory systems.

Claims

1. A system, comprising: an array of non-volatile memory cells arranged into rows and columns; a sense amplifier to receive current during a read operation from a first non-volatile memory cell in a first column of the array and to indicate a first value stored in the first non-volatile memory cell and to receive current during the read operation from a second non-volatile memory cell in a second column of the array and to indicate a second value stored in the second non-volatile memory cell; and a logic circuit to receive from the sense amplifier the indicated first value and the indicated second value and to perform an AND operation on the first indicated value and the second indicated value to generate a data bit output based on the indicated first value and the indicated second value.

2. The system of claim 1, wherein the first non-volatile memory cell and the second non-volatile memory cell are in the same row in the array.

3. The system of claim 1, wherein the first non-volatile memory cell and the second non-volatile memory cell are in different rows in the array.

4. A system, comprising: an array of non-volatile memory cells arranged into rows and columns; a sense amplifier to receive current during a read operation from a first non-volatile memory cell in a first column of the array and to indicate a first value stored in the first non-volatile memory cell and to receive current during the read operation from a second non-volatile memory cell in a second column of the array and to indicate a second value stored in the second non-volatile memory cell; and a logic circuit to receive from the sense amplifier the indicated first value and the indicated second value and to perform an OR operation on the first indicated value and the second indicated value to generate a data bit output.

5. The system of claim 4, wherein the first non-volatile memory cell and the second non-volatile memory cell are in the same row in the array.

6. The system of claim 4, wherein the first non-volatile memory cell and the second non-volatile memory cell are in different rows in the array.

7. A system, comprising: an array of non-volatile memory cells arranged into rows and columns; and a sense amplifier to receive combined current during a read operation from a first non-volatile memory cell and a second non-volatile memory cell in a selected column of the array and to generate a data bit output indicating a value based on a comparison of the combined current to a reference current.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 depicts a prior art non-volatile memory system.

(2) FIG. 2 depicts a prior art split gate flash memory cell.

(3) FIG. 3 depicts another prior art split gate flash memory cell.

(4) FIG. 4 depicts another prior art split gate flash memory cell.

(5) FIG. 5 depicts a prior art non-volatile memory system with a protected area.

(6) FIG. 6 depicts another embodiment of a system data architecture.

(7) FIG. 7 depicts another embodiment of a system data architecture.

(8) FIG. 8 depicts another embodiment of a system data architecture.

(9) FIG. 9 depicts another embodiment of a system data architecture.

(10) FIG. 10 depicts another embodiment of a system data architecture.

(11) FIG. 11 depicts another embodiment of a system data architecture.

DETAILED DESCRIPTION OF THE INVENTION

(12) FIGS. 6-8 depict embodiments that are particularly suitable for non-volatile memory (NVM) cell designs where a charge loss, charge redistribution, disturb, or other physical or electrical changes in the NVM cell will cause a cell to gravitate towards a “1” state, which might flip a stored “0” to a “1” but will not affect a stored “1”.

(13) FIG. 6 depicts system data architecture 600. Each bit of system data is written into two redundant NVM cells, such as cells 601 and 602, located in the same row accessible by the same word line, such as wordline 601, and in different columns accessible by different bit lines, such as bit lines 604 and 605.

(14) During a read operation, current from NVM cells 601 and 602 are simultaneously but independently sensed by sense amplifier 104 against a reference current to determine their respective logic states. Data read from the two cells as output by sense amplifier 104 (which indicates a first value stored one of the two NVM cells 601, 602 and a second value stored in the other of the two NVM cells 601, 602) are routed through AND device 603 (a logic device performing an AND function, which can be implemented using hardware logic or by firmware executed on a controller or processor) to generate the final system data (indicated by “Output”).

(15) If NVM cells 601 and 602 originally stored a “0” and neither cell has flipped, then the output will be a “0”. If NVM cells 601 and 602 originally stored a “0” and one of the two NVM cells 601, 602 has flipped from a “0” to a “1,” the output will still be a “0” because the output of AND device 603 will be “0”. The probability of both NVM cells flipping from a “0” to a “1” is extremely low.

(16) If NVM cells 601 and 602 originally stored a 1, then it is expected that both NVM cells 601 and 602 will still store a “1” because the underlying NVM cell architecture is assumed to be of the type where a leakage or disturb will cause a “0” to flip to a “1” but will not cause a “1” to flip to a “0”. Bitline 606 and wordline 603 are shown for completeness.

(17) FIG. 7 depicts system data architecture 700. Each bit of system data is written into two redundant NVM cells. The redundant NVM cells each can be located in any row and in any column. That is, there is no restriction on where the redundant NVM cells can be placed, and they need not be located in the same row or column or adjacent rows or columns. In this example, a pair of redundant bits are stored in NVM cell 701 accessible by wordline 601 and bit line 604 and in NVM cell 702 accessible by wordline 603 and bitline 606. Bitline 602 and wordline 605 are shown for completeness.

(18) During a read operation, current from NVM cells 701 and 702 are independently sensed by sense amplifier 104 against a reference current to determine their respective logic states. Read data from the two NVM cells output by sense amplifier 104 (which indicates a first value stored one of the two NVM cells 701, 702 and a second value stored in the other of the two NVM cells 701, 702) are processed with AND device 603 (a logic device performing an AND function, which can be implemented using hardware logic or by firmware executed on a controller or processor) to generate the final system data (indicated by “Output”).

(19) If NVM cells 701 and 702 originally stored a “0” and neither cell has flipped, then the output will be a “0”. If NVM cells 701 and 702 originally stored a “0” and one of the two NVM cells 701, 702 has flipped from a “0” to a “1,” the final data will still be a “0” because the output of the AND operation will be “0”. The probability of both NVM cells 701 and 702 flipping from a “0” to a “1” is extremely low.

(20) If NVM cells 701 and 702 originally stored a “1”, then it is expected that both will still store a “1” because the underlying NVM cell architecture is assumed to be of the type where a leakage, disturb, or other changes will cause a “0” to flip to a “1” but will not cause a “1” to flip to a “0”.

(21) FIG. 8 depicts system data architecture 800. Each bit of system data is written into two redundant NVM cells, such as NVM cells 801 and 802, located in the same column accessible by the same bit line, such as bitline 604, but located in different rows accessible by different wordlines, such as wordlines 601 and 603. Bitlines 605, 606 and wordline 602 are shown for completeness.

(22) During a read operation, both wordlines 601 and 603 are selected. Read current from NVM cells 801 and 802 are combined in the common bitline 604. The summed current is sensed by sense amplifier 104 against a reference current to determine its logic state. The reference current is set to a level within a range which is: higher than the sum of a typical 0-state read current for the NVM cells and the upper limit of a neutral floating gate (FG) read current (for NVM cells which use charge storage in a polysilicon FG, where the upper limit refers to the upper limit of the range of neutral FG read current for NVM cells in the array); or higher than the sum of typical 0-state read current plus the saturation point of 0-state read current movement (for NVM cells which use other storage mechanisms). The reference level is also lower than two times the lower limit of read current of 1-state cells which are read immediately after being set to 1-state.

(23) During production test screen of a device following system data architecture 800, a read with the reference current within the above mentioned range is performed on the protected area 501, to guarantee that the two NVM cells 801 and 802 can be erased sufficiently to ensure the combined read current exceeds the reference level, under worst-case erase and read conditions, where the “worst case” is the weakest erase and read conditions across specified process/temperature/voltage ranges, which can vary from technology to technology. These conditions typically are captured during testing.

(24) If the stored data in selected NVM cells 801 and 802 is a “0” and neither NVM cell flips, then the final data output by sense amplifier 104, (indicated by “Output”) is still a “0”. If the stored data in selected NVM calls 801 and 802 is “0”, and one of the two NVM cells 801, 802 has flipped from a “0” to a “1,” the combined read current of the two NVM cells will saturate before it exceeds the reference current, and the final data will still be deemed by sense amplifier 104 to be a “0”. The probability of both NVM cells 801, 802 flipping from a “0” to a “1” is extremely low.

(25) If NVM cells 801 and 802 originally stored a “1”, then it is expected that both NVM cells 801, 802 will still store a “1” because the underlying NVM cell architecture is assumed to be of the type where a leakage, disturb, or other changes will cause a “0” to flip to a “1” but will not cause a “1” to flip to a “0”.

(26) FIGS. 9-10 depict embodiments that are particularly suitable for NVM cell designs where a charge loss, charge redistribution, or disturb will cause a cell to gravitate towards a “0” state, which might flip a stored “1” to a “0” but will not affect a stored “0”.

(27) FIG. 9 depicts system data architecture 900. Each bit of system data is written into two redundant NVM cells, such as cells 901 and 902, located in the same row accessible by the same wordline, such as wordline 601, but located in different columns accessible by different bitlines, such as bitlines 604 and 605. Bitline 606 and wordlines 602, 603 are shown for completeness.

(28) During a read operation, current from NVM cells 901 and 902 are simultaneously but independently sensed against a reference current by sense amplifier 104 to determine a first value stored in NVM cell 901 and a second value stored in NVM 902. Read data from the two NVM cells output by sense amplifier 104 are processed with OR device 903 (a logic device performing an OR function, which can be implemented using hardware logic or by firmware executed on a controller or processor) to generate the final system data (indicated by “Output”).

(29) If NVM cells 901 and 902 originally stored a “1” and neither cell has flipped, then the output will be a “1”. If NVM cells 901 and 902 originally stored a “1” and one of the two NVM cells has flipped from a “1” to a “0,” the final data will still be a “1” because the output of OR device 903 will be “1”. The probability of both NVM cells 901, 902 flipping from a “1” to a “0” is extremely low.

(30) If NVM cells 901 and 902 originally stored a “0”, then it is expected that both NVM cells 901, 902 will still store a “0” because this scheme will only be used in NVM cell architecture where leakage, disturb, or other changes will cause a “1” to flip to a “0” but will not cause a “0” to flip.

(31) FIG. 10 depicts system data architecture 1000. Each bit of system data is written into two redundant NVM cells. The redundant NVM cells each can be located in any row and column. That is, there is no restriction on where the NVM cells can be placed, and they need not be located in the same row or column or adjacent rows or columns.

(32) In this example, a pair of redundant bits are stored in NVM cell 1001 accessible by wordline 601 and bit line 604 and in NVM cell 1002 accessible by wordline 603 and bitline 606. Bitline 605 and wordline 602 are shown for completeness.

(33) During a read operation, current from NVM cells 1001 and 1002 are independently sensed against a reference current by sense amplifier 104 to determine a first value stored in NVM cell 1001 and a second value stored in NVM cell 1002. Read data from the two NVM cells output by sense amplifier 104 are processed with OR device 903 (a logic device performing an OR function, which can be implemented using hardware logic or by firmware executed on a controller or processor) to generate the final system data (indicated by “Output”).

(34) If NVM cells 1001 and 1002 originally stored a “1” and neither NVM cell has flipped, then the output will be a “1”. If NVM cells 1001 and 1002 originally stored a “1” and one of the two NVM cells has flipped from a “1” to a “0,” the final data will still be a “1” because the output of OR device 903 will be “1”. The probability of both NVM cells 1001, 1002 flipping from a “1” to a “0” is extremely low.

(35) If NVM cells 1001 and 1002 originally stored a “0”, then it is expected that both NVM cells 1001, 1002 will still store a “0” because this scheme will only be used in NVM cell architecture where leakage, disturb, or other changes will cause a “1” to flip to a “0” but will not cause a “0” to flip.

(36) FIG. 11 depicts an embodiment that is suitable for: (1) NVM cell designs where a charge loss, charge redistribution, disturb, or other physical changes to the cell will cause a cell to gravitate towards a “0” state, which might flip a stored “1” to a “0” but will not affect a stored “0”; (2) NVM cell designs where aforementioned changes will cause a cell to gravitate towards a “1” state, which might flip a stored “0” to a “1” but will not affect a stored “1”; and (3) NVM cell designs where aforementioned changes will cause an NVM cell to gravitate towards either state, which might flip some stored “0”s to “1”s but also might flip some stored “1”s to “0” s.

(37) FIG. 11 depicts system data architecture 1100. Here, each word of system data, such as word 1101, is stored with associated error correction code data, such as error correction code (ECC) data 1102 in a row. Each system bit is stored in a word and is stored without redundancy. Multiple words may be stored in a row, each with there associated error correction code data, without exceeding the scope.

(38) Here, ECC data 1102 is generated for word 1101 using an ECC, such as the Hamming code, or a code generated by the majority voter algorithm (where data is stored in N redundant physical cells and the value of the stored data is deemed to be the value indicated by a majority of the N cells), to perform error detection and error correction such as 2-bit error detection and 1-bit error correction scheme. In place of ECC data 1102, a parity bit scheme may be utilized to indicate error detection without correction. When bit 1101 is read, the entire word 1101 and ECC data 1102 are read by sense amplifier 104 and sent to ECC engine 1103. That is, sense amplifier 104 receives current from the array and outputs a word and error correction code data for the word to ECC engine 1103. If any single bit in word 1101 has flipped in either direction, the error will be detected and/or corrected successfully by ECC engine 1103. The probability of more than one bit flipping is extremely low.

(39) In one embodiment, system data architecture 1100 is additionally implemented with redundancy such as using multiple cells for each system bit to further enhance the reliability such as for functional safety for automotive applications. For example, each system bit can be stored in two cells in two rows or two columns, as described in previous embodiments.

(40) In one embodiment, ECC engine 1103 is implemented using an external controller or firmware.

(41) It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.