MOSFET in sic with self-aligned lateral MOS channel

Abstract

There is disclosed a method for manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising simultaneously formed n type regions (7) comprising an access region (7a) and a JFET region (7b) defining the length of the MOS channel (17), and wherein the access region (7a) and the JFET region (7b) are formed by ion implantation by using one masking step. The design is self-aligning so that the length of the MOS channel (17) is defined by simultaneous creating n-type regions on both sides of the channel (17) using one masking step. Any misalignment in the mask is moved to other less critical positions in the device. The risk of punch-through is decreased compared to the prior art. The current distribution becomes more homogenous. The short-circuit capability increases. There is lower Drain-Source specific on-resistance due to a reduced MOS channel resistance. There is a lower JFET resistance due to the possibility to increase the JFET region doping concentration.

Claims

1. A method of manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising: an n+substrate (1), an n drift layer (3) in contact with the n+substrate (1), the method comprising: forming a p type buried grid (4) in contact with the n drift layer (3), forming a p-well (6) above the p type buried grid (4), forming simultaneously formed n type regions (7) comprising an access region (7a) and a JFET region (7b) that are laterally self-aligned and have an intermediate part of the p-well (6) between the access region (7a) and the JFET region (7b); forming an n+source (8) in contact with the p-well (6) and the access region (7a), forming a p body (9) for a body diode circuit in contact with the p-well (6) and the p type buried grid (4), forming an insulating gate oxide (10) on a portion of the n+source (8), the access region (7a), the intermediate part of the p-well (6), and the JFET region (7b), forming a gate contact (11) on the insulating gate oxide (10), forming an isolation layer (12) on the gate contact (11), forming a source contact (13) for a MOSFET circuit in contact with the n+source (8), forming a body diode contact (14) for the body diode circuit in contact with the p body (9), and forming a drain contact (15) in contact with the n+substrate (1), wherein the simultaneously formed access region (7a) and JFET region (7b), which are laterally self-aligned, have the intermediate part of the p-well (6) between the access region (7a) and the JFET region (7b), and are in contact with the gate oxide (10), define a MOS channel (17), wherein the access region (7a) is in contact with the n+source (8), wherein the JFET region (7b) is in contact with the n drift layer (3) or with an optional n layer (5) between the n drift layer (3) and the JFET region (7b), and wherein the access region (7a) and the JFET region (7b) in the simultaneously formed n type regions (7) are formed by ion implantation into the p-well (6) by using one masking step, wherein one of the following steps is carried out: i. forming the p-well (6) by a process involving ion implantation and the simultaneously formed n type regions (7) being implanted to such a depth that a part of the p-well (6) under the access region (7a) remains, or ii. forming the p-well (6) by epitaxial growth not involving ion implantation, wherein at least one selected from a p-well implant (6b) and the p type buried grid (4) is disposed between the n drift layer (3) and a region consisting of the p-well (6) as well as the access region (7a).

2. The method according to claim 1, wherein the MOSFET comprises an n+buffer layer (2) between the n+substrate (1) and the n drift layer (3).

3. The method according to claim 1, wherein the isolation layer (12) also is between the source contact (13) and the body diode contact (14).

4. The method according to claim 1, wherein the source contact (13) and the body diode contact (14) are connected.

5. The method according to claim 1, wherein the source contact (13) and the body diode contact (14) are connected by a thick metallization (16).

6. The method according to claim 1, wherein the source contact (13) and the body diode contact (14) are not connected.

7. The method according to claim 1, wherein the part of the p-well (6) which is not the MOS channel (17) has a doping concentration which is different from the intermediate part of the p-well (6) which is the MOS channel (17).

8. The method according to claim 1, wherein the p-well (6) has a higher doping concentration towards the lower part of the p-well (6).

9. The method according to claim 1, wherein the access region (7a) has a doping concentration less than 1e17/cm3.

10. A MOSFET with lateral channel in SiC, said MOSFET comprising: an n+substrate (1), an n drift layer (3) in contact with the n+substrate (1), a p type buried grid (4) in contact with the n drift layer (3), a p-well (6) above the p type buried grid (4), simultaneously formed n type regions (7) comprising an access region (7a) and a JFET region (7b) that are laterally self-aligned and have an intermediate part of the p-well (6) disposed between the access region (7a) and the JFET region (7b), an n+source (8) in contact with the p-well (6) and the access region (7a), a p body (9) for a body diode circuit in contact with the p-well (6) and the p type buried grid (4), an insulating gate oxide (10) on a portion of the n+source (8), the access region (7a), the intermediate part of the p-well (6), and the JFET region (7b), a gate contact (11) on the insulating gate oxide (10), an isolation layer (12) on the gate contact (11), a source contact (13) for a MOSFET circuit in contact with the n+source (8), a body diode contact (14) for the body diode circuit in contact with the p body (9), and a drain contact (15) in contact with the n+substrate (1), wherein the simultaneously formed access region (7a) and JFET region (7b), which are laterally aligned and have the intermediate part of the p-well (6) between the access region (7a) and the JFET region (7b), define a MOS channel (17), wherein the access region (7a) is in contact with the n+source (8), wherein the JFET region (7b) is in contact with the n drift layer (3) or with an optional n layer (5) between the n drift layer (3) and the JFET region (7b), wherein the access region (7a) and the JFET region (7b) in the simultaneously formed n type regions (7) have the same doping concentration and define the length of the MOS channel (17) with a tolerance of ±50 nm or less, and wherein the MOSFET satisfies one of: iii. the p-well (6) is made by a process involving ion implantation and the simultaneously formed n type regions (7) are implanted to such a depth that a part of the p-well (6) under the access region (7a) remains, or iv. the p-well (6) is made by epitaxial growth not involving ion implantation, wherein at least one selected from a p-well implant (6b) and the p type buried grid (4) is disposed between the n drift layer (3) and a region consisting of the p-well (6) as well as the access region (7a).

11. The MOSFET according to claim 10, wherein the length of the MOS channel (17) is defined with a tolerance of ±30 nm or less.

12. The MOSFET according to claim 10, wherein the MOSFET comprises an n+buffer layer (2) between the n+substrate (1) and the n drift layer (3).

13. The MOSFET according to claim 10, wherein the isolation layer (12) also is between the source contact (13) and the body diode contact (14).

14. The MOSFET according to claim 10, wherein the source contact (13) and the body diode contact (14) are connected.

15. The MOSFET according to claim 10, wherein the source contact (13) and the body diode contact (14) are connected by a thick metallization (16).

16. The MOSFET according to claim 10, wherein the source contact (13) and the body diode contact (14) are not connected.

17. The MOSFET according to claim 10, wherein the part of the p well (6) which is not the MOS channel (17) has a doping concentration which is different from the intermediate part of the p-well (6) which is the MOS channel (17).

18. The MOSFET according to claim 10, wherein the p-well (6) has a higher doping concentration towards the lower part of the p-well (6).

19. The MOSFET according to claim 10, wherein the access region (7a) has a doping concentration less than 1e17/cm3.

20. A MOSFET arrangement according to claim 10, wherein body diode parts comprising the body diode contact (14), the p body (9) are not repeated in every unit cell so that there are more than one MOSFET between two adjacent body diodes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention is described with reference to the following drawings in which:

(2) FIG. 1 shows the manufacturing process for a device according to the invention. In the top panel the p-well is formed by selective doping such as ion implantation. In the middle panel the p-well (6) is formed. In the bottom panel the simultaneously formed n type regions (7, 7a, 7b) are formed, i.e. the self aligned channel is formed.

(3) FIG. 2 shows the continuation of the manufacturing process from FIG. 1, where the source region (8), the gate oxide (10) and the gate (11) are formed.

(4) FIG. 3 shows the manufacturing process for a device according to the invention where no other layer is between the p-well (6) and the p type buried grid (4), i.e. the p-well (6) is in contact with the p type buried grid (4). In the top panel the p-well is formed by selective doping such as ion implantation. In the middle panel the p-well (6) is formed. In the bottom panel the simultaneously formed n type regions (7, 7a, 7b) are formed, i.e. the self aligned channel is formed.

(5) FIG. 4 shows the continuation of the manufacturing process from FIG. 3, where the source region, the gate oxide and the gate are formed.

(6) FIG. 5 shows the manufacturing process for two devices according to the invention where the p-well is made by epitaxy and not involve ion implantation. The access region (7a) and the JFET region (7b) has to be implanted deeper than the p-well layer thickness. Hence, the access region (7a) does not have a part of the p-well (6) under it. The p type buried grid (4) covers the entire p-well (6) as well as the access region (7a), so that there is no direct contact between the p-well (6) and the access region (7a) with the n drift layer (3) and hence there is no need for an additional p-well implant (6b) to avoid punch-through. The p-well (6) is formed by non-selective doping such as epitaxial growth. In one embodiment (right panels) the relative doping level in the different regions is: 9>4>7>6. In the left panels the doping level in the lower part of the access region (7a) and in lower part of the JFET region (7b) is higher than in the buried grid (4). In the upper panels the p-well (6) is formed. The p-well (6) is in contact with the p type grid (4). In the middle panel the self aligned channel is formed, i.e. the part of the p-well (6) between the access region (7a) and the JFET region (7b). In the lower panel the source region (8) is formed.

(7) FIG. 6 shows the continuation of the manufacturing process from FIG. 5, where the gate oxide (10) and the gate (11) are formed.

(8) FIG. 7 shows a cross section of a unit cell of a DMOSFET according to the state of the art. There is no p type buried grid. 1—n+ substrate, 2—n+ buffer layer, 3—n drift layer, 6—p-well, 7—n type JFET area, 8—n+ source, 9—p+ contact area, 10—gate oxide, 11—gate contact, 12—passivation layer, 13—source contact, 14—body diode contact, 15—drain contact+thick metallization, 16—thick metallization

(9) FIG. 8 shows the DMOSFET from FIG. 7 according to the state of the art with indicated areas for the body diode and the MOSFET. An electrical model is shown as well.

(10) FIG. 9 shows a resistance model of the DMOSFET from FIG. 7 according to the state of the art. The MOSFET and the PN body diode share the same drift to drain area. For the MOSFET: R.sub.total, MOS=R1+R2+R3+R4+R6+R7+R8. R1—Source contact resistance, R2—Source to MOS channel resistance, R3—MOS channel resistance, R4—JFET resistance, R6—Drift resistance, R7—Substrate+buffer layer resistance, R8—Drain contact resistance. For the PN-Body Diode: R.sub.total, pnd=R9+R10+R6+R7+R8. R9—P-Body contact resistance, R10—P-well resistance, R6—Drift resistance, R7—Substrate+buffer layer resistance, R8—Drain contact resistance.

(11) FIG. 10 shows a cross section of a unit cell. A MOSFET and a body diode is shown In this configuration the p-well region (6) is in direct contact with the buried p+ buried grid (4). 1—n+ substrate, 2—n+ buffer layer, 3—n drift layer, 4—p type buried grid, 5—n regrown layer, 6—p-well, 7 simultaneously formed n type regions. The simultaneously formed n type regions 7 are made of 7a access region and 7b JFET region. 8—n+ source, 9—p body, 10—gate oxide, 11—gate contact, 12—isolation layer, 13—source contact, 14—body diode contact, 15—drain contact+thick metallization, 16—thick metallization, In this case, the depth of the access region (7a) is the same as the depth of the JFET region (7b).

(12) FIG. 11 shows an electrical model of the body diode and MOSFET according to FIG. 10. The source (S), gate (G) and drain (D) are indicated. The shaded areas show the body diode and the MOSFET. An electrical model is shown as well.

(13) FIG. 12 shows the cross section of a MOSFET unit cell with a resistance model. R.sub.total MOS=R1+R2+R3+R4+R5+R6+R7+R8, R1—Source contact resistance, R2—Source to MOS channel access resistance, R3—MOS channel resistance, R4—JFET resistance, R5—Buried grid channel resistance, R6—Drift resistance, R7—Substrate+buffer layer resistance, R8—Drain contact resistance. Also the resistance of the PN body diode is shown: R.sub.total pnd=R9+R10+R11+R12+R13+R14. R9—P-Body contact resistance, R11—P-body+p-grid resistance, R12—Drift Resistance, R13—Substrate+buffer layer resistance, R14—Drain contact resistance, As can be seen the MOSFET and the PN body diode do not share the same drift to drain area and hence the drift to drain resistances are generally different.

(14) FIG. 13 shows the cross section of a unit cell similar to FIG. 10, but the p-type buried grid (4) is not in direct contact with the p-well (6), the p-type buried grid (4) is in contact with the p-body (9) forming a connection of the p-well (6) and the p-type buried grid (4).

(15) FIG. 14 shows the cross section of a unit cell for the embodiment of FIG. 13, where the areas of the body diode and the MOSFET respectively are shown together with the source (S), gate (G) and drain (D). An electrical model is also shown.

(16) FIG. 15 shows a resistance model of the embodiment in FIG. 13. R.sub.total MOS=R1+R2+R3+R4+R5+R6+R7+R8, R1—Source contact resistance, R2—Source to MOS channel access resistance, R3—MOS channel resistance, R4—JFET resistance, R5—Buried grid channel resistance, R6—Drift resistance, R7—Substrate+buffer layer resistance, R8—Drain contact resistance. Also the resistance of the PN body diode is shown: R.sub.total pnd=R9+R10+R11+R12+R13+R14. R9—P-Body contact resistance, R11—P-body+p-grid resistance, R12—Drift resistance, R13—Substrate+buffer layer resistance, R14—Drain contact resistance. As can be seen the MOSFET and the PN body diode do not share the same drift to drain area and hence the drift to drain resistances are generally different.

(17) FIG. 16 shows a comparative embodiment where the p-well (6) is manufactured with epitaxy, but the regions 7a and 7b are manufactured involving ion implantation. This embodiment is not according to the invention. It shows the critical point indicated by an arrow and a circle. If the concentration in the bottom part of the p-well (6) is too low, the depletion region of the pn-junction can in blocking extend to the source (8) through the access region (7a) or the channel underneath the gate (10+11). This punch through needs to be avoided.

(18) FIG. 17 shows an embodiment according to the invention, where the p-well (6) is manufactured involving epitaxy and ion implantation. Between the n drift layer (3) on one side and a region consisting of the p-well (6), as well as the access region (7a) on the other side, there is at least one from a p type buried grid (4) and a p-well implant (6b). As can be seen, between the access region (7a) and the n drift layer (3) there is both a p type buried grid (4) and a p-well implant (6b). The p-well implant (6b) is manufactured involving ion implantation. Between the p-well (6) and the n-type drift layer (3), there is partly both a p type buried grid (4) and a p-well implant (6b) and partly only a p-well implant (6b).

(19) FIG. 18 shows an alternative embodiment according to the invention, where the depth of the p-well (6) is thinner than the depth of the simultaneous formed n-type regions (7). The embodiment of FIG. 18 is manufactured in the same way as the embodiment in FIG. 17. The p type buried grid (4) is not covering the entire area between the p-well (6) and the n drift layer (3). One part of the area is covered by the p-well implant (6b) in contact with the JFET region (7b), the p-grid (4) and the p-well (6). Also in this case there is at least one selected from a p-type buried grid (4) and a p-well implant (6b) between the p-well (6) and the n-type drift layer (3).

(20) FIG. 19 shows the cross section of a unit cell for the embodiment of FIG. 17, where the areas of the body diode and the MOSFET respectively are shown together with the source (S), gate (G) and drain (D). An electrical model is also shown.

(21) FIG. 20 shows a resistance model of the embodiment in FIG. 17. R.sub.total MOS=R1+R2+R3+R4+R5+R6+R7+R8, R1—Source contact resistance, R2—Source to MOS channel access resistance, R3—MOS channel resistance, R4—JFET resistance, R5—Buried grid channel resistance, R6—Drift resistance, R7—Substrate+buffer layer resistance, R8—Drain contact resistance. Also the resistance of the PN body diode is shown: R.sub.total pnd=R9+R10+R11+R12+R13+R14. R9—P-Body contact resistance, R11—P-body+p-grid resistance, R12—Drift Resistance, R13—Substrate+buffer layer resistance, R14—Drain contact resistance, As can be seen the MOSFET and the PN body diode do not share the same drift to drain area and hence the drift to drain resistances are generally different.

(22) FIG. 21 shows different ways of arranging MOSFET cells and PN body diode cells according to the invention. In the upper panel an embodiment where there is one MOSFET cell between adjacent PN body diodes. In the middle panel, there are more than one MOSFET cells between adjacent PN body diodes. In the bottom panel an embodiment according to the prior art is shown where each MOSFET cell has a PN body diode contact.

DETAILED DESCRIPTION

(23) Before the invention is disclosed and described in detail, it is to be understood that this invention is not limited to particular compounds, configurations, method steps, substrates, and materials disclosed herein as such compounds, configurations, method steps, substrates, and materials may vary somewhat. It is also to be understood that the terminology employed herein is used for the purpose of describing particular embodiments only and is not intended to be limiting since the scope of the present invention is limited only by the appended claims and equivalents thereof.

(24) It must be noted that, as used in this specification and the appended claims, the singular forms “a”, “an” and “the” include plural referents unless the context clearly dictates otherwise.

(25) If nothing else is defined, any terms and scientific terminology used herein are intended to have the meanings commonly understood by those of skill in the art to which this invention pertains.

(26) To be in contact as used herein in connection with regions and objects means that they are in physical contact with each other. If the regions are conductive this implies that there is an electrical contact as well.

(27) MOSFET is used to denote a metal oxide semiconductor field effect transistor. The PN body diode part is included in the term MOSFET unless where the MOSFET is indicated separate next to the PN body diode such as in FIGS. 8, 11, 14, and 19.

(28) In a first aspect there is provided a method of manufacturing a MOSFET with lateral channel in SiC, said DMOSFET comprising: an n-F substrate (1), an n drift layer (3) in contact with the n+ substrate (1), a p type buried grid (4) in contact with the n drift layer (3), a p-well (6), simultaneously formed n type regions (7), an n+ source (8), a p body (9) in contact with the p-well (6) and the p type buried grid (4), an insulating gate oxide (10), a gate contact (11) on the insulating gate oxide (10), an isolation layer (12) on the gate contact (11), a source contact (13) in contact with the n+ source (8), a body diode contact (14) in contact with the p body (9), a drain contact (15) in contact with the n+ substrate (1), wherein the simultaneously formed n type regions (7) comprises an access region (7a) and a JFET region (7b) with a part of the p-well (6) between the access region (7a) and the JFET region (7b) defining a MOS channel (17),

(29) wherein the access region (7a) is in contact with the n-F source (8),

(30) wherein the JFET region (7b) is in contact with the n drift layer (3), or an optional n layer (5) between the n drift layer (3) and the JFET region (7b),

(31) wherein the access region (7a) and the JFET region (7b) in the simultaneously formed n type regions (7) are formed by ion implantation by using one masking step,

(32) wherein one of the following steps is carried out:

(33) i. the p-well (6) is made by a process involving ion implantation and the simultaneously formed n type regions (7) are implanted to such a depth that a part of the p-well (6) under the access region (7a) remains, or ii. the p-well (6) is made by epitaxial growth not involving ion implantation, wherein at least one selected from a p-well implant (6b) and p type buried grid (4) is between the n drift layer (3) and a region consisting of the p-well (6) as well as the access region (7a).

(34) The MOSFET is manufactured in silicon carbide (SiC). Other materials such as metals and oxides are also used as known in the art to make specific details such as oxide layers and metal layers and metal contacts.

(35) When the p-well (6) is made by ion implantation, i.e. the manufacturing of the p-well (6) includes ion implantation, then a part of the p-well (6) has to remain at least under the access region (7a). “under” in this context means that a part of the p-well (6) is between the access region (7a) and the n drift layer (3) or the optional layer (5).

(36) When the p-well (6) is made by epitaxial growth and the manufacturing of the p-well (6) is not involving ion-implantation, then an additional p-well implant (6b) is necessary, if there otherwise would have been a direct contact of the p-well (6) and the n drift layer (3). The p-well implant (6b) protects from punch through, which may happen if there was a direct contact between the p-well (6) and the n drift layer (3). Thus the p-well implant (6b) should be between the p-well (6) and the n drift layer (3) so that there is no direct contact between the p-well (6) and the n drift layer (3). If a p type buried grid (4) is between the p-well (6) and the n drift layer (3), then the p-well implant (6b) might be not needed. The p-well implant (6b) is in contact with the JFET region (7b), the p-grid (4) and the p-well (6). In one embodiment, the p-well implant (6b) has a doping concentration in the interval 5e17-5e18/cm.sup.3. The doping concentration of the p-well implant (6b) is preferably adapted so that it overcompensates the access region (7a) and the JFET region (7b). The doping concentration of the p-well implant (6b) is thus preferably higher than in the access region (7a) and the JFET region (7b).

(37) When it is stated that the JFET region (7b) is in contact with the n drift layer (3), it is intended that there may be an optional layer (5) between and in contact with the n drift layer (3) and the JFET region (7b).

(38) The letters p and n denote the conductivity type for the doping, i.e. positive and negative conductivity type respectively. The letter n and p refer to the conductivity type of the layers, areas, or regions, examples include p-well, p-type, n-type etc where the letter p and n denote the conductivity type. Although the most common configuration of conductivity type is shown in the different aspects, a skilled person realizes that it is possible to change conductivity type so that p becomes n and n becomes p. Thus also all embodiments where p and n are exchanged are encompassed. It is possible to change all p to n and all n to p in the invention.

(39) The part of the P-well volume between the access (7a) and JFET (7b) regions and closest to the gate oxide (10) is called the MOS channel (17). The length of the MOS channel (17) is defined by the simultaneously formed n-type regions (7) which are added by ion implantation. In the cross section shown in FIG. 10 the length can be seen as the distance across the area (17). In the FIGS. 11-20 the MOS channel (17) is not indicated, but is the part of the p-well (6) which is between the access region (7a) and the JFET region (7b) and close to the gate oxide (10). It can be seen that the simultaneous formed n type regions (7) comprises an access region (7a) and a JFET region (7b). Thus 7 denotes both 7a and 7b.

(40) In one embodiment the MOSFET comprises an n-F buffer layer (2).

(41) In one embodiment the MOSFET comprises an n layer (5) between the buried grid (4) and the p-well (6) and in contact with the n drift layer (3) and the JFET region (7b).

(42) In one embodiment the isolation layer (12) also is between the source contact (13) and the body diode contact (14).

(43) In one embodiment the source contact (13) and the body diode contact (14) are connected.

(44) In one embodiment the source contact (13) and the body diode contact (14) are connected by a thick metallization (16).

(45) In one embodiment the source contact (13) and the body diode contact (14) are not connected.

(46) In one embodiment the p-well (6) is made by epitaxial growth.

(47) Under a part of the JFET region (7b), there may or may not be a part of the p-well (6).

(48) In one embodiment the part of the p-well (6) which is not the MOS channel (17) has a doping concentration which is different from the part of the p-well (6) which is the MOS channel (17). The MOS channel (17) is between the access region (7a) and the JFET region (7b). The MOS channel (17) is not explicitly indicated in all drawings. It is indicated in FIG. 10, but exists also in the other embodiments according to the invention such as the ones shown in FIGS. 11-20.

(49) In one embodiment, the p-well (6) has a higher doping concentration towards the lower part of the p-well (6). This has the advantage that the protection against punch-through becomes even better. This embodiment is suitably made with selective doping of the p-well (6). It can be made by ion implantation of the p-well (6) or by an epitaxial grown p-well (6) combined with ion-implantation of the JFET region (7b).

(50) In one embodiment, the access region (7a) has a doping concentration less than 1e17/cm.sup.3. This has the advantage of improving the short-circuit capability of the MOSFET.

(51) In one embodiment the relative doping concentrations of some of the regions are as follows: 6<7a, 7b<6b<4.

(52) It is said that a part is made with ion implantation when ion implantation has been involved in the manufacturing process. If for instance a part is made with epitaxial growth followed by ion implantation, then the part exposed to the ion implantation is said to be made by ion implantation. It is said that a part is made by epitaxy if that part is made by epitaxy but not subjected to ion implantation.

(53) In a second aspect there is provided a MOSFET with lateral channel in SiC, said MOSFET comprising: an n-F substrate (1), an n drift layer (3) in contact with the n+ substrate (1), a p type buried grid (4) in contact with the n drift layer (3), a p-well (6), simultaneously formed n type regions (7), an n+ source (8), a p body (9) in contact with the p-well (6) and the p type buried grid (4), an insulating gate oxide (10), a gate contact (11) on the insulating gate oxide (10), an isolation layer (12) on the gate contact (11), a source contact (13) in contact with the n+ source (8), a body diode contact (14) in contact with the p body (9), a drain contact (15) in contact with the n+ substrate (1),

(54) wherein the simultaneously formed n type regions (7) comprise an access region (7a) and a JFET region (7b) with a part of the p-well (6) between the access region (7a) and the JFET region (7b) defining a MOS channel (17),

(55) wherein the access region (7a) is in contact with the n+ source (8),

(56) wherein the JFET region (7b) is in contact with the n drift layer (3), or an optional n layer (5) between the n drift layer (3) and the JFET region (7b),

(57) wherein the access region (7a) and the JFET region (7b) in the simultaneously formed n type regions (7) have the same doping concentration and define the length of the MOS channel (17) with a tolerance of ±50 nm or better,

(58) wherein the MOSFET satisfies one of:

(59) i. the p-well (6) is made by a process involving ion implantation and the simultaneously formed n type regions (7) are implanted to such a depth that a part of the p-well (6) under the access region (7a) remains, or ii. the p-well (6) is made by epitaxial growth not involving ion implantation, wherein at least one selected from a p-well implant (6b) and the p type buried grid (4) is between the n drift layer (3) and a region consisting of the p-well (6) as well as the access region (7a).

(60) In one embodiment the length of the MOS channel (17) is defined with a tolerance of ±30 nm or better. The length is the distance between the access region (7a) and the JFET region (7b). The masking step for (7) comprises several process steps affecting the channel length distribution (tolerance) over the wafer, but not so much locally. Within one MOSFET chip, the channel length distribution can be even below 30 nm. In one embodiment the tolerance is ±30 nm or better. In one embodiment the typical length of the MOS channel (17) is in the interval 0.5-1 μm with a tolerance of ±50 nm or better, preferably ±30 nm or better. In one embodiment the tolerance is ±20 nm or better. In one embodiment the tolerance is ±25 nm or better. In one embodiment the tolerance is ±35 nm or better. In one embodiment the tolerance is ±40 nm or better. In one embodiment the tolerance is ±45 nm or better.

(61) The simultaneous formation of access (7a) and JFET (7b) regions shifts the wider resistance distribution from the MOS channel (17) to the access region (7a). The MOSFET performance is less sensitive on access resistance variations. Without it, the resistance distribution is mainly in the MOS channel.

(62) The embodiments of the first aspect are also applicable to the second aspect.

(63) In one embodiment, the access region (7a) between the n-F source (8) and the MOS channel (17) forms together with the MOS channel the dominant part of the MOSFET resistance. The carrier mobility drop with temperature is higher for the moderately doped access region (7a) than for the high doped source (8). Therefore, in comparison with conventional MOSFET structures without access region, the resistance in the access region will increase and the stress of the MOS channel (17) on the gate oxide (10) will be reduced giving an improved short circuit capability (time before breakdown).

(64) The formation process of the self-aligned channel has in one embodiment a p-well with lower doping concentration than in conventional MOSFET designs as the simultaneously formed n type regions (7) on both sides of the channel are limited in doping concentration (JFET-region doping concentration <5e17/cm.sup.3) and the p-well doping concentration is in one embodiment overcompensated (p-well doping concentration <JFET-region doping concentration). In addition, low p-well doping concentration in the MOS channel region is preferred due to increased channel mobility. Towards the bottom of the p-well region, the doping concentration increases in one embodiment as high electric field at the edges of the p-well can lead to punch-through, which results in reduced blocking capability and early breakdown of the device. Hence, the embodiment with the proposed MOSFET architecture combines a low-doped p-well with a high doped buried p+-grid, which can be implemented either in contact or separated from the p-well (FIGS. 1 & 2). The buried grid is shielding the sensitive parts of the MOSFET structure such as the gate oxide and the JFET region from high electric field and has high enough doping concentration to avoid punch-through. The combination of low-doped p-well and high-doped buried grid enables a reduction of the on-state resistance of the MOSFET by increasing channel mobility, hence reducing the channel resistance (R3), as well as a reduction of the JFET resistance (R4) and a controllable source to MOS channel access resistance (R2).

(65) The proposed structure benefits from a buried grid, which forms an effective pn body diode for the third quadrant operation of the MOSFET. Therefore, the lower-doped p-well will not participate in the third-quadrant current drive, leading to improved reliability of the device.

(66) In one embodiment there is provided a MOSFET arrangement wherein body diode parts comprising the body diode contact (14), the p body (9) are not repeated in every unit cell so that there are more than one MOSFET between two adjacent body diodes. Such an embodiment is depicted in FIG. 21, middle panel.