Semiconductor device for increasing capacitance effective area and effective capacitance value

Abstract

A semiconductor device is disclosed. The semiconductor device includes a substrate, a well, an oxidation layer, a gate electrode and a shared source/drain electrode. The substrate has a first surface and a second surface opposite to each other. The well is formed in the substrate. The substrate and the well have a first conductivity type and a second conductivity type respectively. The oxidation layer is formed in the well. The gate electrode is formed above the first surface and has a first opening. The shared source/drain electrode is formed near the first surface in the oxidation layer and exposed from the first opening. The shared source/drain electrode has the first conductivity type.

Claims

1. A semiconductor device for increasing capacitance effective area and effective capacitance value, comprising: a substrate having a first surface and a second surface, wherein the first surface and the second surface are opposite to each other; a well formed in the substrate, wherein the substrate and the well have a first conductivity type and a second conductivity type respectively; an oxidation layer formed in the well; a gate electrode formed above the first surface and having a first opening; a poly-silicon layer formed above the first surface and under the gate electrode, wherein an area of the poly-silicon layer is larger than an area of the gate electrode; and a shared source/drain electrode formed near the first surface in the oxidation layer and exposed from the first opening, wherein the shared source/drain electrode has the first conductivity type; wherein a capacitance of a capacitor between the gate electrode and the oxidation layer is proportional to an effective length of the gate electrode which is proportional to a mask length, so the capacitance of the capacitor formed by the gate electrode, the oxidation layer and the substrate is increased by increasing the mask length and extending the poly-silicon layer to both sides to make an area of the poly-silicon layer larger than that of the gate electrode to increase the capacitance effective area and the effective capacitance value without changing manufacturing processes of the semiconductor device.

2. The semiconductor device of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

3. The semiconductor device of claim 2, wherein a guard ring surrounding the well is formed in the substrate.

4. The semiconductor device of claim 1, further comprising: a first contact electrically connected to the gate electrode; and a second contact electrically connected to the shared source/drain electrode.

5. The semiconductor device of claim 1, wherein the substrate having the first conductivity type and the shared source/drain electrode both comprise dopants of the first conductivity type.

6. The semiconductor device of claim 5, wherein a concentration of the dopants of the first conductivity type in the shared source/drain electrode is higher than that in the substrate.

7. The semiconductor device of claim 1, wherein the well having the second conductivity type comprises dopants of the second conductivity type.

Description

BRIEF DESCRIPTION OF THE APPENDED DRAWINGS

(1) FIG. 1 illustrates a timing diagram of the display data signal and the polarity control signal in the prior art.

(2) FIG. 1 illustrates a schematic diagram showing a conventional operational amplifier including an input stage and an output stage coupled in series with each other.

(3) FIG. 2 illustrates a schematic diagram showing the output stage of a conventional operational amplifier with a gold-oxygen half-capacitance as a compensation capacitor.

(4) FIG. 3A and FIG. 3B respectively illustrate a top view showing a layout of a conventional MOS capacitor and a cross-sectional view showing its luminated structure.

(5) FIG. 4A and FIG. 4B illustrate schematic diagrams showing respective internal distributed capacitances in a general MOS capacitor.

(6) FIG. 5 illustrates a schematic diagram showing the definition of parameters such as an effective width and an effective length in a general MOS capacitor.

(7) FIG. 6A and FIG. 6B illustrate schematic diagrams showing changes in the capacitance values of the MOS capacitor at different gate-source voltages respectively.

(8) FIG. 7 illustrate a schematic diagram showing that the poly-silicon layer in the MOS capacitor of the invention extends to both sides and the source electrode and the drain electrode are shared with each other.

(9) FIG. 8A and FIG. 8B illustrate a top view of the layout of the MOS capacitor and a schematic cross-sectional view of the laminated structure thereof in the invention respectively.

DETAILED DESCRIPTION OF THE INVENTION

(10) An embodiment of the invention is a semiconductor device.

(11) In this embodiment, the semiconductor device according to the invention can be a MOS capacitor applied to an operational amplifier. Its main function is to provide higher compensation capacitance value to improve the stability of the system, thereby improving the disadvantage of the system which is not stable due to the low actual compensation capacitance value in the prior art.

(12) At first, please refer to FIG. 4A and FIG. 4B. FIG. 4A and FIG. 4B illustrate schematic diagrams showing respective internal distributed capacitances in a general MOS capacitor.

(13) As shown in FIG. 4A and FIG. 4B, the MOS capacitor MOS formed on the substrate B includes a gate electrode G, a source electrode S, and a drain electrode D. The internal distributed capacitors in the MOS capacitor MOS can include a first capacitor C1 between the gate electrode G and the source electrode S, a second capacitor C2 between the gate electrode G and the oxide layer OX, a third capacitor C3 between the gate electrode G and the drain electrode D, a fourth capacitor C4 between the oxide layer OX and the substrate B, a fifth capacitor C5 between the gate electrode G and the substrate B located in an overlap region OL that the gate electrode G at a side and a field oxide layer FOX overlap, a capacitor CBS between the source electrode S and the substrate B and a capacitor CBD between the drain electrode D and the substrate B.

(14) Then, please refer to FIG. 5. FIG. 5 illustrates a schematic diagram showing the definition of parameters such as an effective width and an effective length in a general MOS capacitor.

(15) As shown in FIG. 5, in the MOS capacitor MOS, the actual effective length LEFF of the gate electrode G is the distance between the source electrode S and the drain electrode D. Since both the source electrode S and the drain electrode D extend to below the gate electrode G, there is a small overlap length LD with the gate G. Therefore, the effective length LEFF of the gate electrode G is slightly smaller than the mask length LMK and the effective length LEFF is approximately equal to the mask length LMK minus twice the overlap length LD, but not limited to this.

(16) Similarly, the mask width WMK of the source electrode S and the drain electrode D is also slightly reduced to the effective width WEFF due to the disposition of the field oxide layer; that is to say, the effective width WEFF of the source electrode S and the drain electrode D is slightly smaller than the mask width WMK. And, the effective width WEFF will be approximately equal to the mask width WMK minus twice the width OE, but not limited to this.

(17) Next, please refer to FIG. 6A and FIG. 6B. FIG. 6A and FIG. 6B illustrate schematic diagrams showing changes in the capacitance values of the MOS capacitor at different gate-source voltages respectively.

(18) As shown in FIG. 6A, when the gate-source voltage VGS of the MOS capacitor is between 0 and the threshold voltage VT, it is defined as “a cut-off region”; when the gate-source voltage VGS of the MOS capacitor is between the threshold voltage VT and (the drain-source voltage VDS plus the threshold voltage VT), it is defined as “a saturation region”; when the gate-source voltage VGS of the MOS capacitor is higher than (the drain-source voltage VDS plus the threshold voltage VT), it is defined as “a linear region”. FIG. 6B illustrates a schematic diagram showing the capacitance of the MOS capacitor is at “an aggregation stage SA”, “a depletion stage SB”, “a moderate inversion stage SC” and “a strong inversion stage SD” under different gate-source voltages VGS.

(19) In summary, the first capacitor C1 to the fifth capacitor C5 can be respectively calculated as follows:

(20) (1) The capacitance of the first capacitor C1 between the gate electrode G and the source electrode S

(21) =the capacitance of the third capacitor C3 between the gate electrode G and the drain electrode D

(22) =(the overlap length LD)*(the effective width WEFF)*(the oxide layer capacitance COX)

(23) (2) The capacitance of the second capacitor C2 between the gate electrode G and the oxide layer OX

(24) =(the effective width WEFF)*(the effective length LEFF)*(the oxide layer capacitance COX)

(25) =(the effective width WEFF)*(the mask length LMK−2*the overlap length LD)*(the oxide layer capacitance COX)

(26) (3) The capacitance of the fourth capacitor C4 between the oxide layer OX and the substrate B=0

(27) (4) The capacitance of the fifth capacitor C5 between the gate electrode G and the substrate B

(28) =(the capacitance CGB between the gate electrode G and the substrate B)*(the effective length LEFF)

(29) =(the capacitance CGB between the gate electrode G and the substrate B)*(the mask length LMK−2* the overlap length LD)

(30) Next, assuming that the capacitance values of the MOS capacitors in “the cut-off region”, “the saturation region” and “the linear region” are COFF, CSAT, and CLINE respectively. And then, COFF, CSAT, and CLINE can be calculated as follows:

(31) (1) COFF

(32) =(the capacitance CGB between the gate electrode G and the substrate B)+(the capacitance CGS between the gate electrode G and the source electrode S)+(the capacitance CGD between the gate electrode G and the drain electrode D)
=(C2+2*C5)+(C1)+(C3)  Formula 1

(33) (2) CSAT

(34) =(the capacitance CGB between the gate electrode G and the substrate B)+(the capacitance CGS between the gate electrode G and the source electrode S)+(the capacitance CGD between the gate electrode G and the drain electrode D)
=(2*C5)+(C1+2C⅔)+(C3)  Formula 2

(35) (3) CLINE

(36) =(the capacitance CGB between the gate electrode G and the substrate B)+(the capacitance CGS between the gate electrode G and the source electrode S)+(the capacitance CGD between the gate electrode G and the drain electrode D)
=(2*C5)+(C1+C2/2)+(C3+C2/2)  Formula 3

(37) It can be known from the above formula 1 to formula 3 that if the capacitance of the second capacitor C2 between the gate electrode G and the oxide layer OX can be effectively increased, the MOS capacitor can provide higher capacitance value no matter in “the cut-off region”, “the saturation region” and “the linear region”. Therefore, when the MOS capacitor is applied to an operational amplifier, the MOS capacitor can provide higher compensation capacitance value to improve the overall stability of the system.

(38) In the above, in order to increase the capacitance of the second capacitor C2 between the gate electrode G and the oxide layer OX, for example, as shown in FIG. 7, the poly-silicon layer POLY in the MOS capacitor MOS can extend to both sides, so that the area of the poly-silicon layer POLY is larger than the area of the gate electrode G above it, and the source electrode S and the drain electrode D of the MOS capacitor MOS can be shared with each other, so that the MOS capacitor MOS can provide higher capacitance value, but not limited to this.

(39) Please refer to FIG. 8A and FIG. 8B. FIG. 8A and FIG. 8B illustrate a top view of the layout of the MOS capacitor and a schematic cross-sectional view of the laminated structure thereof in the invention respectively.

(40) As shown in FIG. 8A, a guard ring GR surrounding the well NW is formed in the substrate PS, and the shared source electrode/drain electrode S/D is disposed at the center.

(41) After comparing FIG. 3A of the prior art with FIG. 8A of the invention, it is known that assuming that the capacitance effective area in FIG. 3A of the prior art is AEFF1 and the capacitance effective area in FIG. 8A of the invention is AEFF2, then AEFF1 and AEFF2 can be calculated as follows:

(42) $\begin{array}{cc}\left(1\right)& \\ \mathrm{AEFF}1=L{1}^{*}W1& \mathrm{Formula}4\\ \left(2\right)& \\ \begin{array}{c}\mathrm{AEFF}2=\left(L*W\right)-\left[{\left(2W1/3\right)}^{*}L2\right]\\ =\left[{\left(L1+2L2+2L3\right)}^{*}\left(W1+2W2\right)\right]-\\ \left[{\left(2W1/3\right)}^{*}L2\right]\end{array}& \mathrm{Formula}5\end{array}$

(43) Assuming L1=20, W1=6, L2=1, L3=W2=0.5, it can be known according to Formula 4 and Formula 5 that:

(44) (1) The capacitance effective area AEFF1 in FIG. 3A of the prior art

(45) =20*6=120

(46) (2) The capacitance effective area AEFF2 in FIG. 8A of the invention

(47) =[(20+2*1+2*0.5)*(6+2*0.5)]−(4*1)=157

(48) That is to say, the capacitance effective area AEFF2 in FIG. 8A of the invention can be significantly increased from the capacitance effective area AEFF1 in FIG. 3A of the prior art, and the percentage increase thereof is approximately [(157-120)/120]*100%=30.83%, but not limited to this.

(49) In addition, according to the cross-sectional view of the luminated structure of the MOS capacitor MOS shown in FIG. 8B, the MOS capacitor MOS of the invention can include the substrate PS, the well region NW, the oxide layer OX, the gate electrode G and the shared source electrode/drain electrode S/D.

(50) The substrate PS has a first surface SF1 and a second surface SF2, and the first surface SF1 and the second surface SF2 are opposed to each other. The well NW is formed in the substrate PS. The oxide layer OX is formed in the well NW. The gate electrode G is formed above the first surface SF1 and has a first opening OP1. The shared source electrode/drain electrode S/D is formed in the oxide layer OX near the first surface SF1, and is exposed to the first opening OP1. The gate electrode G is electrically connected to the first contact VGP. The shared source electrode/drain electrode S/D is electrically connected to the second contact OUT.

(51) It should be noted that the substrate PS having the first conductivity type and the shared source electrode/drain electrode S/D both include dopants of the first conductivity type (for example, the P-type dopants). However, since the shared source electrode/drain electrode S/D is a first conductive type heavily-doped region (for example, the P-type heavily-doped region) p+, it is believed that the concentration of the dopants of the first conductivity type in the shared source electrode/drain electrode S/D is higher than that in the substrate PS. As for the well NW having the second conductivity type, it includes dopants of the second conductivity type (for example, the N-type dopants).

(52) In practical applications, as shown in FIG. 8B, the semiconductor device MOS can further include a poly-silicon layer POLY formed above the first surface SF1 and under the gate electrode G, and the poly-silicon layer POLY can extend to both sides to make the area of the poly-silicon layer POLY larger than the area of the gate electrode G. The poly-silicon layer POLY has a second opening OP2, and the second opening OP2 is located below the first opening OP1, and the second opening OP2 is larger than the first opening OP1.

(53) It should be noted that the MOS capacitor MOS shown in FIG. 8B can increase the capacitance effective area and the effective capacitance value by increasing the area of the poly-silicon layer POLY and using the shared source/drain S/D, but not limited to this.

(54) Compared to the prior art, the semiconductor device according to the invention can be a MOS capacitor applied to an operational amplifier, which can increase capacitance effective area and effective capacitance value by increasing the area of the poly-silicon layer and using the shared source/drain electrode under the condition of the same overall area. Therefore, higher compensation capacitance value can be provided to improve the stability of the system, thereby improving the disadvantage of the system which is not stable due to the low actual compensation capacitance value in the prior art.

(55) With the example and explanations above, the features and spirits of the invention will be hopefully well described. Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teaching of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.