A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers. The electrically conductive layers include an intermetallic alloy of aluminum and at least one metal other than aluminum. Memory openings vertically extend through the alternating stack. Memory opening fill structures are located in a respective one of the memory openings and include a respective vertical semiconductor channel and a respective vertical stack of memory elements.

A method includes forming a first conductive feature in a first dielectric layer, forming a first metal cap over and contacting the first conductive feature, forming an etch stop layer over the first dielectric layer and the first metal cap, forming a second dielectric layer over the etch stop layer; and etching the second dielectric layer and the etch stop layer to form an opening. The first conductive feature is exposed to the opening. The method further includes selectively depositing a second metal cap at a bottom of the opening, forming an inhibitor film at the bottom of the opening and on the second metal cap, selectively depositing a conductive barrier in the opening, removing the inhibitor film, and filling remaining portions of the opening with a conductive material to form a second conductive feature.

A semiconductor structure includes a first dielectric layer on a substrate, a conductive structure disposed in the first dielectric layer and including a terminal portion and an extending portion connecting the terminal portion and extending away from the terminal portion, a second dielectric layer disposed on the first dielectric layer, a conductive via through the second dielectric layer and directly contacting the extending portion, and a dummy via through the second dielectric layer and directly contacting the terminal portion. In a cross-sectional view, a width of the dummy via is smaller than 50% of a width of the conductive via.

A semiconductor memory device includes a first insulating layer, a first conductive layer, a first pillar, a second pillar, and a second insulating layer. The first conductive layer contains tungsten. The first conductive layer includes a first sub conductive layer and a second sub conductive layer. The first pillar and the second pillar pass through the first insulating layer and the first conductive layer. The second insulating layer divides the first insulating layer and the first conductive layer. The first sub conductive layer is in contact with the second sub conductive layer and is provided between the second sub conductive layer and the first insulating layer. A fluorine concentration in the first sub conductive layer is lower than that in the second sub conductive layer.

A method of forming a semiconductor device can comprise providing a first shift region in which to determine a first displacement. A second shift region may be provided in which to determine a second displacement. A unique electrically conductive structure may be formed comprising traces to account for the first displacement and the second displacement. The electrically conductive structure may comprise traces comprising a first portion within the first shift region and a second portion of traces in the second shift region laterally offset from the first portion of traces. A third portion of the traces may be provided in the routing area between the first shift region and the second shift region. A unique variable metal fill may be formed within the fill area. The variable metal fill may be electrically isolated from the unique electrically conductive structure.

A method of forming a metal superlattice structure includes depositing, on a substrate, a layer of a first metal with face-centered-cubic (fcc) crystal structure. The method further includes depositing a layer of ruthenium (Ru) metal with fcc crystal structure on the layer of the first metal. The layer of the first metal may cause the layer of ruthenium metal to have fcc crystal structure.

A variety of applications can include apparatus having a memory device with an array of vertical strings of memory cells for the memory device with data lines coupled to the vertical strings, where the data lines have been formed by a metal liner deposition process. In the metal liner deposition, a metal can be formed on a patterned dielectric region. The metal liner deposition process allows for construction of the height of the data lines to be well controlled with selection of a thickness for the dielectric region used in forming the metal liner. Use of a metal liner deposition provides a controlled mechanism to reduce data line capacitance by being able to select liner thickness in forming the data lines. The use of the dielectric region with the metal liner deposition can allow the fabrication of the data lines to avoid pitch double or pitch quad processes.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process are disclosed. The methods may include: providing a substrate comprising a dielectric surface into a reaction chamber; depositing a nucleation film directly on the dielectric surface; and depositing a molybdenum metal film directly on the nucleation film, wherein depositing the molybdenum metal film includes: contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor; and contacting the substrate with a second vapor phase reactant comprising a reducing agent precursor. Semiconductor device structures including a molybdenum metal film disposed over a surface of a dielectric material with an intermediate nucleation film are also disclosed.

Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.