Neural-signal amplifier and multi-channel neural-signal amplifying system

Abstract

A neural-signal amplifier includes an amplifier, a switched-capacitor circuit-input unit, a switched-capacitor feedback-circuit unit, and a switched-capacitor circuit-output unit. Each of the switched-capacitor circuit-input unit, the switched-capacitor feedback-circuit unit, and the switched-capacitor circuit-output unit includes a plurality of differential switches, a plurality of common mode switches, and a plurality of capacitors. By controlling the switches to turn on or performing the switched-capacitor operation, the neural-signal amplifier is controlled to suppress the DC drift and reconstruct the DC input of the common-mode power supply.

Claims

1. A neural-signal amplifier, comprising: an amplifier comprising a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a common-mode feedback-input terminal, wherein the first input terminal is configured to receive a first input signal, the second input terminal is configured to receive a second input signal, and the common-mode feedback-input terminal is configured to receive a common-mode feedback-input signal to generate and respectively output a first amplified output signal and a second amplified output signal from the first output terminal and the second output terminal; and a switched-capacitor circuit-input unit receiving a first bio-potential signal and a second bio-potential signal to generate the first input signal and the second input signal; and two switched-capacitor feedback-circuit units, wherein one of the two switched-capacitor feedback-circuit units is electrically connected between the first input terminal and the first output terminal of the amplifier, and other one of the two switched-capacitor feedback-circuit units is electrically connected between the second input terminal and the second output terminal; and a switched-capacitor circuit-output unit receiving the first amplified output signal and the second amplified output signal to generate the common-mode feedback-input signal; wherein the switched-capacitor circuit-input unit, the two switched-capacitor feedback-circuit unit, and the switched-capacitor circuit-output unit are further provided with a plurality of differential switches and a plurality of common-mode switches, wherein when the plurality of differential switches are turned on and the plurality of common-mode switches are turned off, the neural-signal amplifier is in a differential amplifying state; when the plurality of differential switches are turned off and the plurality of common-mode switches are turned on, the neural-signal amplifier is in a common-mode reconstructing state, wherein the neural-signal amplifier is controlled to switch between the differential amplifying state and the common-mode reconstructing state by operations the plurality of differential switches and the plurality of common-mode switches, so as to reconstruct a common-mode current to suppress DC current drift; wherein the neural-signal amplifier further comprises a switch-control unit electrically connected to the switched-capacitor circuit-input unit, the two switched-capacitor feedback-circuit units, and the switched-capacitor circuit-output unit, wherein the switch-control unit outputs a switch-control signal to control each of the differential switches and each of the common-mode switches, wherein when the switch-control signal is higher than a standard value, the plurality of differential switches are turned on and the plurality of common-mode switches are turned off; when the switch-control signal is lower than the standard value, the plurality of differential switches are turned off and the plurality of common-mode switches are turned on.

2. The neural-signal amplifier according to claim 1, wherein the switched-capacitor circuit-input unit comprises: a first differential switch connected to a first bio-potential signal source which generates the first bio-potential signal; a first common-mode switch connected between the first differential switch and a first capacitor, and the first capacitor connected to the first input terminal; a second differential switch connected to a second bio-potential signal source which generates the second bio-potential signal; a second common-mode switch connected between the second differential switch and a second capacitor, and the second capacitor connected to the second input terminal; and a first reference voltage connected between the first common-mode switch and the second common-mode switch.

3. The neural-signal amplifier according to claim 2, wherein the switched-capacitor feedback-circuit unit comprises: a third common-mode switch; a fourth common-mode switch connected to a fifth bias source which supplies a fifth bias, and the fifth bias source further connected to the third common-mode switch; a third differential switch connected to the fourth common-mode switch; a third capacitor connected between the third common-mode switch and the fourth common-mode switch; and a low-pass capacitor connected between the third common-mode switch and the third differential switch; wherein the third capacitor, the low-pass capacitor, and the third common-mode switch are connected to the first input terminal or the second input terminal, and the low-pass capacitor and the fourth common-mode switch are respectively connected to the first output terminal and the second output terminal.

4. The neural-signal amplifier according to claim 3, wherein the switched-capacitor circuit-output unit comprises: a sixth common-mode switch connected to the first output terminal; a seventh common-mode switch connected to the common-mode feedback-input terminal; an eighth common-mode switch connected to the second output terminal; a sixth differential switch having a terminal connected to the sixth common-mode switch, and another terminal connected to a fifth bias source which supplies a fifth bias; a seventh differential switch having a terminal connected to the seventh common-mode switch, and another terminal connected to a first bias source which supplies a first bias; an eighth differential switch having a terminal connected to the eighth common-mode switch, and another terminal connected to the fifth bias source which supplies the fifth bias; a fifth capacitor having a terminal connected between the first output terminal and the seventh common-mode switch, and another terminal connected between the common-mode feedback-input terminal and the seventh differential switch; a sixth capacitor having a terminal connected between the common-mode feedback-input terminal and the seventh common-mode switch, and another terminal connected between the second output terminal and the eighth common-mode switch; a seventh capacitor having a terminal connected between the sixth common-mode switch and the eighth differential switch, and another terminal connected between the seventh common-mode switch and the seventh differential switch; and an eighth capacitor having a terminal connected between the seventh common-mode switch and the seventh differential switch, and another terminal connected between the eighth common-mode switch and the eighth differential switch.

5. The neural-signal amplifier according to claim 4, further comprising a bias-voltage generating unit, wherein the bias-voltage generating unit is electrically connected to the two switched-capacitor feedback-circuit units and the switched-capacitor circuit-output unit, and configured to generate the fifth bias and supply the fifth bias to the two switched-capacitor feedback-circuit units, and generates the fifth bias and the first bias and supplies the fifth bias and the first bias to the switched-capacitor circuit-output unit; wherein the bias-voltage generating unit is connected to a plurality of different bias sources.

6. The neural-signal amplifier according to claim 5, wherein the bias-voltage generating unit comprises a power-supply circuit formed by a Sooch Cascode current mirror.

7. The neural-signal amplifier according to claim 1, wherein the amplifier includes an amplifying circuit formed by a fully-differential folded common-source gate amplifier (FDFC Amp).

8. A multi-channel neural-signal amplifying system, comprising: a plurality of neural-signal amplifier coupling units, wherein each of the neural-signal amplifier coupling units comprises a plurality of neural-signal amplifiers according to claim 1; a plurality of analog-signal microprocessors, wherein each of the analog-signal microprocessors is coupled to one of the neural-signal amplifier coupling units; and a plurality of neural-signal sensing channels, and each of the neural-signal sensing channels connected to each of the neural-signal amplifiers.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 depicts a circuit diagram of a conventional neural-signal detecting circuit.

(2) FIG. 2 depicts an architecture diagram of a brain neural electrophysiological signal-sensing system.

(3) FIG. 3 depicts an architecture diagram of a multi-channel system according to an embodiment of the present invention.

(4) FIG. 4 depicts an block diagram of a neural-signal amplifier according to an embodiment of the present invention.

(5) FIG. 5 depicts a circuit diagram of a neural-signal amplifier according to an embodiment of the present invention.

(6) FIG. 6 depicts a circuit diagram of a common-mode feedback-input architecture according to an embodiment of the present invention.

(7) FIG. 7 depicts a half-circuit diagram of the common-mode feedback-input architecture according to an embodiment of the present invention.

(8) FIG. 8 depicts a half-circuit architecture diagram of a reconstructed common-mode DC power input according to an embodiment of the present invention.

(9) FIG. 9 depicts a circuit diagram of a switched-capacitor circuit-output unit according to an embodiment of the present invention.

(10) FIG. 10 depicts a circuit diagram of a bias-voltage generating unit according to an embodiment of the present invention.

(11) FIG. 11 depicts a circuit diagram of a two-stage amplification unit according to an embodiment of the present invention.

(12) FIG. 12 depicts an open-loop frequency response diagram according to an embodiment of the present invention.

(13) FIG. 13 depicts a time-domain transient response diagram according to an embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(14) The embodiment of the present invention is to be illustrated together with related drawings. In the drawings, the same symbols refer to the same or similar elements or method procedures.

(15) Please refer to FIG. 2, which depicts an architecture diagram of a brain neural electrophysiological signal-sensing system. As shown in FIG. 2, in the brain neural electrophysiological signal-sensing system, a neural-signal detector NM for sensing physiological signals, such as a neural-signal probe, may be used to transmit EEG/ECoG signals to an analog-biological signal-acquisition device ABA. An analog-digital converter ADC and a successive approximation register SAR may be used to convert analog signals into digital signals and then transmit the converted signals to a packet device WP and further to the bus BUS. A microcontroller MCU is connected to bus BUS, and includes a digital-to-analog signal converter DAC. The sensed physiological signals may be analyzed based on the converted amplified signals transmitted by an antenna RF.

(16) Please refer to FIG. 3, which depicts an architecture diagram of the multi-channel system of the neural-signal amplifier according to an embodiment of the present invention. As shown in FIG. 3, a first neural-signal amplifier coupling unit NAA.sub.1 includes a plurality of neural-signal amplifiers, such as the first neural-signal amplifier NA.sub.1, the second neural-signal amplifier NA.sub.2 to the fourth neural-signal amplifier NA.sub.4. The first neural-signal amplifier NA.sub.1 is connected to the first channel Ch.sub.1, and the second neural-signal amplifier NA.sub.2 is connected to the second channel Ch.sub.2. In other words, in the first neural-signal amplifier coupling unit NAA.sub.1, every neural-signal amplifier is independently connected to a channel, and each amplified signal in each neural-signal amplifier is further transmitted to a first analog-signal microprocessor Analog MUX1.

(17) Furthermore, as shown in the embodiment of FIG. 3, the second neural-signal amplifier coupling unit NAA.sub.2 includes a plurality of neural signal-sensing channels, and each neural signal-sensing channel is connected to one of the neural-signal amplifiers. The fifth neural-signal amplifier NA.sub.5, and the sixth neural-signal amplifier NA.sub.6 to the eighth neural-signal amplifier NA.sub.8 are respectively and independently connected to the fifth channel Ch.sub.5, and the sixth channel Ch.sub.6 to the eighth channel Ch.sub.8, and each amplified signal is further transmitted to a second analog-signal microprocessor Analog MUX2. However, the present invention is not limited to the examples described herein. Every neural-signal amplifier coupling unit may be further provided with more than four neural-signal amplifiers, and each neural-signal amplifier is independently connected to a physiological signal channel, and every neural-signal amplifier coupling unit is connected to an analog-signal microprocessor.

(18) Please refer to FIG. 4, which depicts a block diagram of a neural-signal amplifier according to an embodiment of the present invention. As shown in FIG. 4, the neural-signal amplifier includes an amplifier 20, a switched-capacitor feedback-circuit unit 30, a switched-capacitor circuit-output unit 40, and a switched-capacitor circuit-input unit 10. The amplifier 20 includes a first input terminal V.sub.i1, a second input terminal V.sub.i2, a first output terminal V.sub.o1, a second output terminal V.sub.o2, and a common-mode feedback-input terminal V.sub.cmc.

(19) The switched-capacitor circuit-input unit 10 is connected to the first input terminal V.sub.i1 and the second input terminal V.sub.i2 of the amplifier 20. The switched-capacitor circuit-output unit 40 is connected to the common-mode feedback-input terminal V.sub.cmc, the first output terminal V.sub.o1, and the second output terminal V.sub.o2 of the amplifier 20. One switched-capacitor feedback-circuit unit 30 has a terminal connected between the first output terminal V.sub.o1 and the switched-capacitor circuit-output unit 40, and the other terminal connected between the first input terminal V.sub.i1 and the switched-capacitor circuit-input unit 10. The other switched-capacitor feedback-circuit unit 30 has a terminal connected to the second output terminal V.sub.o2 and the switched-capacitor circuit-output unit 40, and the other terminal connected between the second input terminal V.sub.i2 and the switched-capacitor circuit-input unit 10.

(20) In some embodiments of the present invention, the amplifier includes an amplification circuit formed by a fully-differential folded common-source gate amplifier (FDFC Amp).

(21) As shown in FIG. 4, the amplifier 20 includes a first input terminal V.sub.i1, a second input terminal V.sub.i2, a first output terminal V.sub.o1, a second output terminal V.sub.o2, and a common-mode feedback-input terminal V.sub.cmc. The first input terminal V.sub.i1 receives the first input signal, the second input terminal V.sub.i2 receives the second input signal, and the common-mode feedback-input terminal V.sub.cmc receives the common-mode feedback-input signal. The first amplified output signal and the second amplified output signal are respectively outputted from the first output terminal V.sub.o1 and the second output terminal V.sub.o2.

(22) The switched-capacitor circuit-input unit 10 receives a first bio-potential signal and a second bio-potential signal to generate the first input signal and the second input signal. The two switched-capacitor feedback-circuit units 30 are electrically connected between the first input terminal V.sub.i1 and the first output terminal V.sub.o1, and between the second input terminal V.sub.i2 and the second output terminal V.sub.o2 of the amplifier 20. The switched-capacitor circuit-output unit 40 receives the first amplified output signal and the second amplified output signal to generate the common-mode feedback-input signal.

(23) Please further refer to FIG. 5, which depicts a circuit diagram of the neural-signal amplifier according to an embodiment of the present invention. The configuration of the switched-capacitor circuit-input unit 10 according to an embodiment of the present invention is to be described as follows. As shown in FIG. 5, the switched-capacitor circuit-input unit 10 includes a first differential switch Ds.sub.1, a first common-mode switch Cs.sub.2, a second differential switch Ds.sub.2, a second common-mode switch Cs.sub.2, a first capacitor 151, and a second capacitor 152, and the switched-capacitor circuit-input unit 10 is connected to a first reference voltage source that supplies a first reference voltage BIASA. The first differential switch Ds.sub.1 is connected to the first bio-potential signal terminal V.sub.S1 that receives a first bio-potential signal. The first common-mode switch Cs.sub.1 is connected between the first differential switch Ds.sub.1 and the first capacitor 151. The first capacitor 151 is connected to the first input terminal V.sub.i1. The second differential switch Ds.sub.2 is connected to a second bio-potential signal terminal V.sub.S2 that receives a second bio-potential signal. The second common-mode switch Cs.sub.2 is connected between the second differential switch Ds.sub.2 and the second capacitor 152. The second capacitor 152 is connected to the second input terminal V.sub.i2. The first reference voltage BIASA is supplied between the first common-mode switch Cs.sub.1 and the second common-mode switch Cs.sub.2.

(24) In some embodiments of the present invention, the first differential switch Ds.sub.1, the first common-mode switch Cs.sub.2, the second differential switch Ds.sub.2, the second common-mode switch Cs.sub.2, the first capacitor 151, and the second capacitor 152 can be formed by transistors. This further minimizes the size of the neural-signal amplifier of the present invention in the chip architecture.

(25) The configuration of the switched-capacitor feedback-circuit unit 30 according to an embodiment of the present invention is to be described as follows. The switched-capacitor feedback-circuit unit 30 includes a third common-mode switch Cs.sub.3, a fourth common-mode switch Cs.sub.4, a third differential switch Ds.sub.3, a third capacitor 153, a low-pass capacitor CLP, and the switched-capacitor feedback-circuit unit 30 is connected to a fifth bias source which supplies a fifth bias BIASE. The fourth common-mode switch Cs.sub.4 is connected to the fifth bias source that supplies the fifth bias BIASE, the fifth bias source is also connected to the third common-mode switch Cs.sub.3, and the third differential switch Ds.sub.3 is connected to the fourth common-mode switch Cs.sub.4. The third capacitor 153 is connected between the third common-mode switch Cs.sub.3 and the fourth common-mode switch Cs.sub.4. The low-pass capacitor CLP is connected between the third common-mode switch Cs.sub.3 and the third differential switch Ds.sub.3.

(26) Specifically, in an embodiment of the present invention, the neural-signal amplifier 1 includes two switched-capacitor feedback-circuit units; the third capacitor 153, the low-pass capacitor CLP, and the third common-mode switch Cs.sub.3 of one switched-capacitor feedback-circuit unit 30 are connected to the first input terminal V.sub.i1, and the low-pass capacitor CLP and the fourth common-mode switch Cs.sub.4 of this one switched-capacitor feedback-circuit unit 30 are connected to the first output terminal V.sub.o1.

(27) The third capacitor 153, the low-pass capacitor CLP, and the third common-mode switch Cs.sub.3 of the other switched-capacitor feedback-circuit unit 30 are connected to the second input terminal V.sub.i2. The low-pass capacitor CLP and the fourth common-mode switch Cs.sub.4 of the other switched-capacitor feedback-circuit unit 30 are connected to the second output terminal V.sub.o2.

(28) Thus, the feedback circuits having the first input terminal V.sub.i1, the first output terminal V.sub.o1, the second input terminal V.sub.i2, and the second output terminal V.sub.o2 are respectively configured to suppress DC current drift.

(29) In some embodiments of the present invention, the low-pass capacitor CLP, the third common-mode switch Cs.sub.3, and the fourth common-mode switch Cs.sub.4 are configured to be formed by transistors, so as to minimize the size of the neural-signal amplifier of the present invention in the chip architecture.

(30) The configuration of the switched-capacitor circuit-output unit 40 is to be further described below. The switched-capacitor circuit-output unit 40 includes a plurality of capacitors and switches and is connected to at least one voltage source. In an embodiment of the present invention, the switched-capacitor circuit-output unit 40 includes a sixth common-mode switch Cs.sub.6, a seventh common-mode switch Cs.sub.7, an eighth common-mode switch Cs.sub.8, a sixth differential switch Ds.sub.6, a seventh differential switch Ds.sub.7, an eighth differential switch Ds.sub.8, a fifth capacitor 155, a sixth capacitor 156, a seventh capacitor 157, and an eighth capacitor 158. In addition, the switched-capacitor circuit-output unit 40 is also connected to the fifth bias source that supplies the fifth bias BIASE, and the first bias source that supplies the first bias BIASA.

(31) Further, the sixth common-mode switch Cs.sub.6 is connected to the first output terminal V.sub.o1; the seventh common-mode switch Cs.sub.7 is connected to the common-mode feedback-input terminal V.sub.cmc; the eighth common-mode switch Cs.sub.8 is connected to the second output terminal V.sub.o2; one terminal of the sixth differential switch Ds.sub.6 is connected to the sixth common-mode switch Cs.sub.6, and the other terminal thereof is connected to the fifth bias source which supplies the fifth bias BIASE; one terminal of the seventh differential switch Ds.sub.7 is connected to the seventh common-mode switch Cs.sub.7, and the other terminal thereof is connected to the first bias source which supplies the first bias BIASA; one terminal of the eighth differential switch Ds.sub.8 is connected to the eighth common-mode switch Cs.sub.8, and the other terminal thereof is connected to the fifth bias source which supplies the fifth bias BIASE.

(32) Please refer to FIG. 6, the connection configuration of the plurality of capacitors in the switched-capacitor circuit-output unit 40 is that one terminal of the fifth capacitor 155 is connected between the first output terminal V.sub.o1 and the seventh common-mode switch Cs.sub.7, and the other terminal of the fifth capacitor 155 is connected between the common-mode feedback-input terminal V.sub.cmc and the seventh differential switch Ds.sub.7; one terminal of the sixth capacitor 156 is connected between the common-mode feedback-input terminal V.sub.cmc and the seventh common-mode switch Cs.sub.7, and the other terminal of the sixth capacitor 156 is connected between the second output terminal V.sub.o2 and the eighth common-mode switch Cs.sub.8; the seventh capacitor 157 is connected between the sixth common-mode switch Cs.sub.6 and the eighth differential switch Ds.sub.8, and the other terminal of the seventh capacitor 157 is connected between the seventh common-mode switch Cs.sub.7 and the seventh differential switch Ds.sub.7; one terminal of the eighth capacitor 158 is connected between the seventh common-mode switch Cs.sub.7 and the seventh differential switch Ds.sub.7, and the other terminal of the eighth capacitor 158 is connected between the eighth common-mode switch Cs.sub.8 and the eighth differential switch Ds.sub.8. When the differential switches Ds.sub.1 to Ds.sub.8 are turned on and the common-mode switches Cs.sub.1 to Cs.sub.8 are turned off, the neural-signal amplifier of the present invention is in a differential amplifying state; when the differential switches Ds.sub.1 to Ds.sub.8 are turned off and the common-mode switches Cs.sub.1 to Cs.sub.8 are turned on, the neural-signal amplifier of the present invention is in a common-mode reconstructing state.

(33) The method of generating the common-mode feedback-input signal outputted by the switched-capacitor circuit-output unit 40 is to be further described as follows. Please refer to FIG. 6 and FIG. 7 which depict a circuit diagram of the common-mode feedback-input architecture, and a half-circuit diagram of the common-mode feedback-input architecture in FIG. 6 according to an embodiment of the present invention, respectively. In the common-mode feedback-input architecture illustrated in FIG. 6, the elements are symmetrically disposed along the direction of the common-mode feedback input, thus preventing the common-mode feedback input from being interfered by differential signals. In other words, in the circuit architecture illustrated in FIG. 6, the circuit architecture may be a fine common-mode feedback circuit by making the direction of the common-mode feedback input (V.sub.cmc) the same as the direction to which the symmetrical axis of the whole circuit extends.

(34) Furthermore, the output voltage of the common-mode feedback circuit is designed to be (V.sub.oc-V.sub.cm). In an embodiment of the present invention, the common-mode feedback-input circuit is designed by the configuration of the switchable switches and capacitors to construct the common-mode feedback input, which has smaller limitation on amplifier output signal amplitudes compared to a conventional 2-differential-pairs common-mode feedback circuit and a triode-region transistor common-mode feedback circuit. In addition, the switched-capacitor common-mode feedback circuit of the present invention does not need to withstand higher resistance loading unlike a conventional resistive-divider common-mode feedback circuit does.

(35) Furthermore, the switched-capacitor common-mode feedback circuit of the present invention may be further applied to a capacitor-filter circuit or other amplifier circuits.

(36) FIG. 6 shows a common-mode feedback circuit diagram. The plurality of switches can be controlled to change the path of the switches for receiving the fifth bias. Preferably, the first bias BIASA is a DC bias; the fifth capacitor 155, the sixth capacitor 156, the seventh capacitor 157, and the eighth capacitor 158 receive the fifth bias BIASE with the deduction of the first bias BIASA.

(37) The first bias BIASA is the DC bias voltage. The sixth common-mode switch Cs.sub.6, the seventh common-mode switch Cs.sub.7, the eighth common-mode switch Cs.sub.8, the sixth differential switch Ds.sub.6, the seventh differential switch Ds.sub.7, and the eighth differential switch Ds.sub.8 can be formed by transistors, and controlled by two non-overlapping clock signals, so as to minimize the size of the neural-signal amplifier of the present invention in the chip architecture.

(38) FIG. 7 discloses a simplified OP amplifier model of the common-mode feedback-input architecture of FIG. 6. The common-mode feedback-input circuit constituted by the switched capacitors is a linear and balanced discrete-time circuit. The second capacitor C2 is connected between the common-mode feedback voltage terminal V.sub.cmc and the output voltage V.sub.oc, and the voltage gain is denoted as A.sub.cmc. When the switches are switched such that all switches corresponding to the first phase f1 are turned on and those corresponding to the second phase f2 are turned off, the supplied voltage received by the first capacitor C1 is V.sub.CM-V.sub.CSBIAS. When the switches are switched such that all switches corresponding to the first phase f1 are turned off and those corresponding to the second phase f2 are turned on, the first capacitor C1 is connected between the output voltage V.sub.oc and the common-mode bias voltage V.sub.cmc. In a stable state, V.sub.oc is a constant value because the common-mode bias voltage V.sub.CM and the reference voltage V.sub.CSBIAS applied during the operation are both DC voltages, and the switched-capacitor circuit operates under a negative feedback loop.

(39) When the output voltage V.sub.oc is constant, the charge transfer halt in the clock phase may be presented as follows:
Q(ϕ.sub.1)=C.sub.1(V.sub.CM−V.sub.CSBIAS)=Q(ϕ.sub.2)=C.sub.1(V.sub.oc−V.sub.cmc) .Math.V.sub.CM−V.sub.CSBIAS=V.sub.oc−V.sub.cmc

(40) When the base-bias voltage V.sub.CSBIAS is equal to the common-mode bias voltage V.sub.CM and the voltage gain A.sub.cmc is much greater than 1, the common-mode bias voltage V.sub.CM approaches the base-bias voltage V.sub.CSBIAS and the output voltage V.sub.oc approaches the common-mode bias voltage V.sub.CM. In other words, since the switched-capacitor circuit is only formed by passive elements such as capacitors and switches, the common-mode circuit is not limited by the output voltage amplitude of the op amplifier.

(41) Please refer to FIG. 8, which depicts a half-circuit architecture diagram of the reconstructed common-mode DC power input according to an embodiment of the present invention. As shown, in the ideal fully-differential operational model, the gain of the common-mode half circuit is A.sub.cmc=0, and thus the overall closed-loop common-mode gain is zero. Therefore, the output voltage V.sub.oc of the common-mode circuit is independent from the input voltage V.sub.ic and the common-mode source voltage V.sub.sc of the common-mode operational amplifier. In actual application, the gain A.sub.cmc of the OP amplifier in the common-mode half-circuit is not zero but is small enough. By using the input differential pair and the tail current source, a common-mode feedback amplification loop may be added to the circuit, so as to reconstruct the input common-mode voltage, thus preventing the input common-mode voltage from possibly drifting.

(42) Please refer to FIG. 9, which depicts a circuit diagram of the switched-capacitor circuit-output unit according to an embodiment of the present invention. As shown in FIG. 9, this switched-capacitor circuit-output unit includes a first transistor Mos.sub.1, a second transistor Mos.sub.2, a third transistor Mos.sub.3, a fourth transistor Mos.sub.4, a fifth transistor Mos.sub.5, a sixth transistor Mos.sub.6, a seventh transistor Mos.sub.7, an eighth transistor Mos.sub.8, a ninth transistor Mos.sub.9, a tenth transistor Mos.sub.10, an eleventh transistor Mos.sub.11, and a twelfth transistor Mos.sub.12.

(43) Specifically, in an embodiment of the present invention, the gate of the first transistor Mos.sub.1 is connected to the first input voltage V.sub.i1; the gate of the second transistor Mos.sub.2 is connected to the second input voltage V.sub.i2; the gate of the third transistor Mos.sub.3 is connected to the common-mode feedback-input terminal V.sub.cmc; the gate of the fourth transistor Mos.sub.4 is connected to the first bias BIASA; the gates of the fifth transistor Mos.sub.5 and the sixth transistor Mos.sub.6 are connected to the second bias BIASB; the gates of the seventh transistor Mos.sub.7 and the eighth transistor Mos.sub.8 are connected to the third bias BIASC; the gates of the ninth transistor Mos.sub.9 and the tenth transistor Mos.sub.10 are connected to the fourth bias BIASD; the gates of the eleventh transistor Mos.sub.11 and the twelfth transistor Mos.sub.12 are connected to the fifth bias BIASE.

(44) Furthermore, as shown in FIG. 9, the fully-differential folded-cascode amplifier with a Sooch Cascode current mirror is used in a biasing operation. The switched-capacitor common-mode feedback circuit is configured to have a common-mode voltage. The gain A.sub.dm0 of the low-frequency differential mode of the fully-differential folded-cascode amplifier may be denoted as follows:

(45) A.sub.dm0=−gm1×R.sub.odh, wherein gm1 refers to the transconductance of the input transistors, and R.sub.odh refers to the output resistance of low-frequency differential half-circuit.

(46) Furthermore, in the circuit architecture illustrated in FIG. 9, the output resistance R.sub.odh of the low-frequency differential half-circuit may also be denoted as R.sub.odh≈[r.sub.o7g.sub.m7(r.sub.o5//r.sub.o1)]//(r.sub.o9g.sub.m9r.sub.o11), wherein r.sub.o refers to the output resistance of the transistor, and the numbers refer to the corresponding transistors, for instance, r.sub.o7 is the output resistance of the seventh transistor, r.sub.o5 is the output resistance of the fifth transistor, r.sub.o1 is the output resistance of the first transistor, r.sub.o9 is the output resistance of the ninth transistor, and r.sub.o11 is the output resistance of the eleventh transistor. gm refers to the transconductance of the transistor, and the numbers refer to the corresponding transistors, for instance, gm.sub.7 is the transconductance of the seventh transistor, and gm.sub.9 is the transconductance of the ninth transistor.

(47) The gain of the low-frequency differential mode of the fully-differential folded-cascode amplifier may be denoted as follows:

(48) A.sub.cm0=−g.sub.m1/(1+g.sub.m1R.sub.t)×R.sub.och≈−R.sub.och/R.sub.t, wherein gm.sub.1 is the transconductance of the input transistor, R.sub.och is the output resistance of the low-frequency common-mode half-circuit, and R.sub.t is the degenerated resistance of the input transistor.

(49) Specifically, in the circuit architecture illustrated in FIG. 9, the output resistance of the low-frequency common-mode half-circuit is R.sub.och≈[r.sub.o7g.sub.m7(r.sub.o5//R.sub.o(M1))]//(r.sub.o9g.sub.m9r.sub.o11), wherein R.sub.o(M1)≈r.sub.o1g.sub.m1(2r.sub.o4//2r.sub.o3). The degenerated resistance of the transistor as stated above is R.sub.t≈(2r.sub.o4//2r.sub.o3).

(50) In an embodiment of the present invention, this circuit further includes a bias-voltage generating unit. The bias-voltage generating unit is electrically connected to the two switched-capacitor feedback-circuit units 30 and the switched-capacitor circuit-output unit 40, generates the fifth bias BIASE and supplies the fifth bias BIASE to the two switched-capacitor feedback-circuit units, and generates the fifth bias BIASE and the first bias BIASA and supplies the fifth bias BIASE and the first bias BIASA to the switched-capacitor circuit-output unit 40. The bias-voltage generating unit is connected to a plurality of different bias sources.

(51) In some embodiments of the present invention, the bias-voltage generating unit includes a power-supply circuit constituted by a Sooch Cascode current mirror.

(52) Please refer to FIG. 10, which depicts a circuit diagram of the bias-voltage generating unit according to an embodiment of the present invention. As shown in FIG. 10, this bias-voltage generating unit includes a thirteenth transistor Mos.sub.13, a fourteenth transistor Mos.sub.14, a fifteenth transistor Mos.sub.15, a sixteenth transistor Mos.sub.16, a seventeenth transistor Mos.sub.17, an eighteenth transistor Mos.sub.18, a nineteenth transistor Mos.sub.19, a twentieth transistor Mos.sub.20, a twenty-first transistor Mos.sub.21, a twenty-second transistor Mos.sub.22, a twenty-third transistor Mos.sub.23, a twenty-fourth transistor Mos.sub.24, a twenty-fifth transistor Mos.sub.25, and a twenty-sixth transistor Mos.sub.26.

(53) Specifically, as shown in FIG. 10, the gate of the thirteenth transistor Mos.sub.13 and the gate of the seventeenth transistor Mos.sub.17 are connected to the second bias BIASB; the gate of the fourteenth transistor Mos.sub.14 and the gate of the eighteenth transistor Mos.sub.18 are connected to the third bias BIASC; the gate of the fifteenth transistor Mos.sub.15 is connected to the gate of the sixteenth transistor Mos.sub.16; the gate of the nineteenth transistor Mos.sub.19 is connected to the gate of the twentieth transistor Mos.sub.20; the gate of the twenty-first transistor Mos.sub.21 is connected to the fourth bias BIASD; the gate of the twenty-second transistor Mos.sub.22 is connected to the first bias BIASA; the gate of the twenty-third transistor Mos.sub.23 is connected between the twenty-fourth transistor Mos.sub.24 and the twenty-fifth transistor Mos.sub.25; the gate of the twenty-fourth transistor Mos.sub.24 is connected to the fifth bias BIASE; the gate of the twenty-fifth transistor Mos.sub.25 is connected to the gate electrode of the twenty-sixth transistor Mos.sub.26.

(54) Furthermore, as shown in the circuit architecture disclosed in FIG. 10, this circuit not only provides extremely high output resistance, but also combines the input current branch, thus eliminating mismatch between each current branch and reducing the consumed power.

(55) Please refer to FIG. 11, which depicts a circuit diagram of the two-stage amplification unit according to an embodiment of the present invention. As shown in FIG. 11, this two-stage amplification unit includes a twenty-seventh transistor Mos.sub.27, a twenty-eighth transistor Mos.sub.28, a twenty-ninth transistor Mos.sub.29, a thirtieth transistor Mos.sub.30, a thirty-first transistor Mos.sub.31, a thirty-second transistor Mos.sub.32, and a thirty-third transistor MOS.sub.33.

(56) The gate of the twenty-seventh transistor Mos.sub.27 and the gate of the twenty-ninth transistor Mos.sub.29 are connected to the second bias BIASB; the gate of the twenty-eighth transistor Mos.sub.28 is connected to the first output terminal V.sub.o1; the gate of the thirtieth transistor Mos.sub.30 is connected to the second output terminal V.sub.o2; the gate of the thirty-first transistor Mos.sub.31 is connected to the first bias BIASA; the gate of the thirty-third transistor Mos.sub.33 is connected to the first bias BIASA; the gate of the thirty-second transistor Mos.sub.32 is connected between the twenty-ninth transistor Mos.sub.29 and the thirtieth transistor Mos.sub.30.

(57) Specifically, with configuration of the two-stage amplification unit circuit as shown in FIG. 11, the input signal is differentially amplified by single-end amplification and two-stage amplification, so as to enhance the gain and benefit the external signal analysis.

(58) Please refer to FIG. 12, which depicts an open-loop frequency response diagram according to an embodiment of the present invention. As shown in FIG. 12, in an embodiment of the present invention, the open-loop frequency response of the neural-signal amplifier has a phase margin of 130 degrees at a bandwidth of BW=1.689 MHz. Furthermore, as shown in FIG. 12, the amplifying system may be stable at a phase margin of 60 degrees; the amplifying system may have a risk of oscillation at a phase margin lower than 60 degrees.

(59) Please refer to FIG. 13, which depicts a time-domain transient response diagram according to an embodiment of the present invention. As shown in FIG. 13, this diagram shows a time-domain transient response of the output signal of the single neural-signal amplifier when the input signal is [0.9+100 □V □ sin (1 KHz)].

(60) In summary, in the present invention, the switched capacitors are used to replace the external DC shielding capacitors; in some embodiments, the switched capacitors and switches may be implemented by transistors, thus minimizing the area of the overall integrated circuit. In addition, with the operations of the switched capacitors, the leakage currents of the switched capacitors are lower than that of the DC shielding capacitors, so that neural signal distortion of the neural-signal amplifier of the present invention can be reduced.

(61) Furthermore, the neural signal received by the multi-channel neural-signal acquisition architecture designed according to the neural-signal amplifier of the present invention may be more accurate, and the sensing signal of the analog front-end circuit may be more easily detected by the physiological signal-detecting terminal by the physiological signal-receiving channel architecture of the neural-signal amplifier independently disposed for each sensing channel.

(62) In addition, the detecting range of the stable measurement of the neural-signal amplifier circuit and the gain range of the designed multi-channel neural-signal acquisition architecture of the present invention may be adjusted by adjusting the circuit disposition of the switched capacitors, so that the neural-signal amplifier of the present invention may be applied to measure other physiological signal sources.

(63) The multi-channel neural-signal amplifying system of the present invention may further eliminate mismatch between different current circuits in the neural-signal amplifier by respectively using the bias-voltage generating unit, which generates the plurality of biases for the switched-capacitor circuit-input unit, and the switched capacitor feedback-circuit unit. Moreover, the accuracy of the signal amplification gain may be further enhanced and the power consumption of the overall circuit architecture can be reduced by sharing a plurality of voltage sources.

(64) The present invention may be realized in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the provided embodiments may make the present invention more easily understood and convey the scope of the present invention more thoroughly and completely for a person of ordinary skills in the art; the present invention may be defined by the scope of the appended claims.