Solid state switch driver circuit for a battery system

Abstract

In a solid state switch (SSS) driver circuit for controlling a solid state switch operated as high side switch between a battery cell stack and a load, the SSS driver circuit includes: a voltage generation circuit; a switch off circuit; and a switch controller connected to a first output node and to a second output node, wherein the switch controller is configured to: receive a ground voltage via a third ground node, and a fourth control signal; and connect the first output node and a gate node of the solid state switch according to the fourth control signal.

Claims

1. A solid state switch (SSS) driver circuit for controlling a solid state switch operated as high side switch between a battery cell stack and a load, the SSS driver circuit comprising: a voltage generation circuit configured to receive: a supply voltage via a first input node; an output voltage of the battery cell stack via a second input node; a ground voltage via a first ground node; and a first control signal, wherein the voltage generation circuit is configured to: generate a drive voltage higher than the supply voltage and the output voltage of the battery cell stack according to the first control signal; and output the drive voltage to a first output node; a switch off circuit configured to receive: the output voltage of the battery cell stack via a third input node; a ground voltage via a second ground node; a second control signal; and a third control signal, wherein the switch off circuit is further configured to output the output voltage of the battery cell stack to a second output node according to the second and third control signals; and a switch controller connected to the first output node and to the second output node, wherein the switch controller is configured to: receive a ground voltage via a third ground node, and a fourth control signal; and connect the first output node and a gate node of the solid state switch according to the fourth control signal.

2. The SSS driver circuit of claim 1, wherein the voltage generation circuit comprises a first capacitor with a first capacitor node connected to the first input node via a first diode and with a second capacitor node connected to either the first ground node or to the second input node according to the first control signal.

3. The SSS driver circuit of claim 2, wherein the voltage generation circuit comprises a first switch configured to connect the second capacitor node to the first ground node in response to the first control signal having a first value and a second switch configured to connect the second capacitor node to the second input node in response to the first control signal having a second value.

4. The SSS driver circuit of claim 2, wherein the voltage generation circuit comprises a Zener diode interconnected between a first output node and a second input node and/or comprises a second capacitor interconnected between the first output node and the second input node.

5. The SSS driver circuit of claim 1, wherein the switch controller comprises a third switch configured to connect the first output node to the gate node in response to the fourth control signal having a first value, and to disconnect the first output node from the gate node in response to the fourth control signal having a second value, wherein the second output node is directly connected to the gate node.

6. The SSS driver circuit of claim 5, wherein the third switch is a third MOSFET with a source node connected to the first output node and a drain node connected to the second output node and wherein the switch controller further comprises a fourth switch that is configured to connect a gate node of the third MOSFET to the third ground node in response to the fourth control signal having a first value and to disconnect the gate node of the third MOSFET from the third ground node in response to the fourth control signal having a second value.

7. The SSS driver circuit of claim 1, wherein the switch off circuit comprises a fifth switch configured to: connect the third input node to the second output node in response to the second control signal having a first value; and disconnect the third input node from the second output node in response to the second control signal having a second value, and wherein the switch off circuit comprises a seventh switch configured to: connect the third input node to the second output node in response to the third control signal having a first value; and disconnect the third input node from the second output node in response to the third control signal having a second value.

8. The SSS driver circuit of claim 7, wherein the fifth switch is a fifth MOSFET with a source node connected to the second output node and a drain node connected to the third input node and wherein the switch off circuit further comprises a sixth switch configured to: connect a gate node of the fifth MOSFET to the second ground node in response to the second control signal having a first value; and disconnect the gate node of the fifth MOSFET from the second ground node in response to the second control signal having a second value.

9. The SSS driver circuit of claim 7, wherein the seventh switch is a seventh MOSFET with a source node connected to the second output node and a drain node connected to the third input node and wherein the switch off circuit further comprises an eighth switch configured to: connect a gate node of the seventh MOSFET to the second ground node in response to the third control signal having a first value; and disconnect the gate node of the seventh MOSFET from the second ground node in response to the third control signal having a second value.

10. The SSS driver circuit of claim 1, further comprising a first diagnostic circuit configured to: output a first diagnostic signal indicating a potential at the second input node; and output a second diagnostic signal indicating a potential at the first output node.

11. The SSS driver circuit of claim 1, further comprising a second diagnostic circuit configured to output a third diagnostic signal indicating a potential at the second output node.

12. A battery system, comprising a battery cell stack comprising a plurality of battery cells, wherein the battery cell stack is configured to supply an output voltage to a stack node; a solid state switch interconnected between the stack node and a supply node, the solid state switch comprising at least one set of anti-serially interconnected FETs, each set comprising at least one first FET and at least one second FET, wherein gate contacts of the at least one first FET and the at least one second FET are electrically interconnected, and source contacts of the at least one first FET and the at least one second FET are electrically interconnected, at least one first drain contact of the at least one first FET is electrically connected to the stack node, and at least one second drain contact of the at least one second FET is electrically connected to the supply node; and the SSS driver circuit according to claim 1, wherein interconnected gate contacts of the at least one first FET and the at least one second FET are connected to the gate node.

13. The battery system of claim 12, wherein the supply voltage is supplied by the battery cell stack by a system basis chip of the battery system that is power supplied by the battery cell stack.

14. The battery system of claim 12, further comprising a microcontroller configured to receive at least one signal indicative of an operation state of the battery system and further configured to output the first control signal, the second control signal, and the third control signal according to the operation state of the battery system.

15. The battery system of claim 14, wherein the microcontroller is further configured to receive a first diagnostic signal, a second diagnostic signal, and a third diagnostic signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Further characteristics and features of some example embodiments will become more apparent to those of ordinary skill in the art by describing in more detail aspects of some example embodiments with reference to the attached drawings in which:

(2) FIG. 1 schematically illustrates a solid state switch driver circuit according to some example embodiments;

(3) FIG. 2 schematically illustrates a solid state switch driver circuit according to some example embodiments;

(4) FIG. 3 schematically illustrates a solid state switch driver circuit according to some example embodiments;

(5) FIG. 4 schematically illustrates a solid state switch driver circuit according to some example embodiments; and

(6) FIG. 5 schematically illustrates a solid state switch driver circuit according to some example embodiments.

DETAILED DESCRIPTION

(7) Reference will now be made in more detail to embodiments, examples of which are illustrated in the accompanying drawings. Effects and features of the example embodiments, and implementation methods thereof will be described with reference to the accompanying drawings. In the drawings, like reference numerals denote like elements, and redundant descriptions may be omitted. Embodiments according to the present invention, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated example embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be more thorough and more complete, and will more fully convey the aspects and features of the example embodiments of the present invention to those skilled in the art.

(8) Accordingly, processes, elements, and techniques that are not considered necessary to those having ordinary skill in the art for a complete understanding of the aspects and features of the present invention may not be described. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity.

(9) As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Further, the use of “may” when describing embodiments of the present invention refers to “one or more embodiments of the present invention.” In the following description of example embodiments of the present invention, the terms of a singular form may include plural forms unless the context clearly indicates otherwise.

(10) It will be understood that although the terms “first” and “second” are used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be named a second element and, similarly, a second element may be named a first element, without departing from the scope of the present invention. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

(11) As used herein, the term “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. Further, if the term “substantially” is used in combination with a feature that could be expressed using a numeric value, the term “substantially” denotes a range of +/−5% of the value centered on the value.

(12) Electric-vehicle batteries, which are used as a power source for an electric motor, differ from starting, lighting, and ignition batteries utilized as part of combustion engine systems because they are designed to give power over sustained periods of time. A rechargeable or secondary battery differs from a primary battery in that a rechargeable battery can be repeatedly charged and discharged, while a secondary battery provides only an irreversible conversion of chemical to electrical energy (i.e., cannot generally be repeatedly charged and discharged). Low-capacity rechargeable batteries may be used as a power supply for small electronic devices, such as cellular phones, notebook computers and camcorders, while high-capacity rechargeable batteries may be used as the power supply for hybrid vehicles and the like.

(13) In general, rechargeable batteries may include an electrode assembly including a positive electrode, a negative electrode, and a separator interposed between the positive and negative electrodes, a case receiving or enclosing the electrode assembly, and an electrode terminal electrically connected to the electrode assembly. An electrolyte solution may be injected into the case in order to enable charging and discharging of the battery via an electrochemical reaction of the positive electrode, the negative electrode, and the electrolyte solution. The shape of the case (e.g., cylindrical or rectangular), depends on the design of the battery and the corresponding use of the battery. Lithium-ion (and similar lithium polymer) batteries, which may be used, for example, in laptops and other consumer electronics, may also be utilized in electric.

(14) Rechargeable batteries may be used as a battery module formed of a plurality of unit battery cells coupled in series and/or in parallel so as to provide relatively high energy density, for example, for motor driving of a hybrid vehicle. That is, the battery module may be formed by interconnecting the electrode terminals of the plurality of unit battery cells depending on a required amount of power and in order to realize a relatively high-power rechargeable battery.

(15) A battery pack is a set of any number of (e.g., identical) battery modules. They may be configured in a series, parallel or a mixture of both to deliver the desired voltage, capacity, or power density. Components of battery packs include the individual battery modules, and the interconnects, which provide electrical conductivity between them.

(16) For meeting the dynamic power demands of various electrical consumers connected to the battery system a static control of battery power output and charging may not be sufficient. Thus, there may be a steady or intermittent exchange of information between the battery system and the controllers of the electricity-consuming components. This information includes the battery system's actual state of charge (SoC), potential electrical performance, charging ability and internal resistance as well as actual or predicted power demands or surpluses of the consumers.

(17) For monitoring, controlling and/or setting of the aforementioned parameters a battery system may include a battery management unit (BMU), a battery management system (BMS), and/or a battery system manager (BSM). Each of these control units may be realized as an integrated circuit (IC), a microcontroller (μC), an application specific integrated circuit (ASIC), or the like. Control units may be an integral part of the battery system and may be located within a common housing or may be part of a remote control module communicating with the battery system via a suitable communication bus. In both cases, the control unit may communicate with the electrical consumers via a suitable communication bus (e.g., a CAN or SPI interface).

(18) Further, a battery system may include a battery disconnect unit (BDU), configured for disconnecting the battery stack from a downstream load in an abnormal operation condition such as, for example, over temperature, over current, over voltage, crash of an electric vehicle, or the like. The BDU may include at least one relay between a node of the battery stack, for example, the high voltage node thereof, and a downstream load. However, due to construction space requirements, increased demands with respect to switching speed and energy conversation, semiconductor-based solutions for BDUs may be utilized. However, such semiconductor-based switches, for example, MOSFET switches, may utilize specific driver circuits.

(19) The driver circuit for such a MOSFET switch may be located on a separate circuit carrier or may share a circuit carrier with another control unit of the battery system, for example, the BMS. In order to be integrable in an electric vehicle, the driver switch may fulfill the safety standards that apply to electric vehicles such as, for example, ASIL A, ASIL, B, ASIL, C, etc. However, driver stages for solid state power switches may not fulfill these safety standards and/or the realization of the known driver stages for solid state power switches may be cost intensive.

(20) Thus, some example embodiments of the present invention may provide a solid state switch (SSS), and a driver circuit for a battery system that can fulfill the safety standards that apply to electric vehicles and that can be realized in a cost-effective manner.

(21) FIG. 1 schematically illustrates a solid state switch (SSS) driver circuit 100 according to some example embodiments of the present invention. The SSS driver circuit 100 is configured for controlling a solid state switch (SSS) 150, interconnected between a stack node 201 and a supply node 202. Therein, the stack node 201 is connected to a battery cell stack that provides an output voltage of the battery cell stack, for example, 48 V, to the stack node 201. The supply node 202 is configured to be connected to one or more loads or a load circuit for supplying power to the one or more loads. The SSS 150 is configured to selectively connect or disconnect the stack node 201 and the supply node 202. For example, the SSS 150 shall enable disconnecting the battery cell stack from any load in an abnormal operation condition. The SSS 150 is operated as a high side switch between the stack and the supply node 202.

(22) The SSS driver circuit 100 as illustrated in FIG. 1 is configured to output a control signal to the SSS 150, for example, to a gate node 151 of the SSS 150. The control signal is output to the gate node via an output node of the SSS driver circuit 100 that corresponds to the gate node 151. However, in the following it is solely referred to the gate node 151. The control signal output by the SSS driver circuit 100 to the SSS 150 is for selectively setting the SSS 150 conductive or non-conductive and is generated as explained in more detail below.

(23) The SSS driver circuit 100 as shown in FIG. 1 comprises a voltage generation circuit 10, a shut off circuit 30 and a switch controller 50. These sub-circuits of the SSS driver circuit 100 realize different functionalities in the SSS driver circuit and are characterized by their respective inputs and outputs as follows. The voltage generation circuit (VGC) 10 comprises a first input node that receives a supply voltage, V.sub.SUP, which is supplied indirectly by the battery cell stack, for example, by a system basis chip of a battery system comprising the battery cells. The VGC 10 further comprises a second input node 12 that receives an output voltage of the battery cell stack, in the following referred to as GND.sub.DRIVER. The VGC 10 further comprises a first ground node 13 for receiving a ground voltage, GND. The ground voltage GND may be a common ground of the SSS driver circuit 100, the stack and the battery system.

(24) The VGC 10 is level shift circuit for outputting a voltage shifted up from an input voltage through a charge pump circuit. The VGC 10 may include a first input node 11 that receives the supply voltage V.sub.SUP, which is an input voltage, and the V.sub.SUP may be a voltage supplied by the battery system 200 itself. For example, the V.sub.SUP is supplied from a battery cell stack (not shown) of the battery system, or indirectly supplied by a system basis chip (not shown) of the battery system. The VGC 10 is configured for generating a drive voltage VCC.sub.DRIVER using the supply voltage V.sub.SUP and the output voltage GND.sub.DRIVER. Therein the drive voltage is higher than V.sub.SUP as well as higher than GND.sub.DRIVER. Further, GND.sub.DRIVER is higher than V.sub.SUP, for example, V.sub.SUP may be about 20 V and GND.sub.DRIVER may be about 48 V. The drive voltage VCC.sub.DRIVER is suitable for setting the SSS 150 conductive when it is applied to the gate node 151 of the SSS 150. In the VGC 10, the drive voltage VCC.sub.DRIVER is generated according to a first control signal. The first control signal is applied to the VGC 10 via a first control node 14 and may be a pulse-width-modulating (PWM) signal. The duty cycle of the PWM signal received via the first control node 14 may control the amplitude of the drive voltage VCC.sub.DRIVER. In other words, the VGC 10 operates as a DCDC converter the conversion ratio of which is controlled via the first control signal. The drive voltage VCC.sub.DRIVER is output to a first output node 15 of the VGC 10. According to some example embodiments, the drive voltage VCC.sub.DRIVER is output continuously to the first output node 15. Thus, according to some example embodiments, the VGC 10 may generate a voltage that is high enough to set to be conductive at a high side SSS 150 interconnected between a battery stack and a load from a voltage provided by that battery stack. That is, the VGC 10 may performs a voltage up-conversion operation.

(25) The SSS driver circuit 100 of the invention further comprises a switch off circuit (SOC) 30 that comprises a third input node that also receives the output voltage GND.sub.DRIVER. The SOC 30 further comprises a second ground node that also receives the ground voltage (GND). Further, the SOC 30 comprises a second control node 32 that receives a second control signal OFF1 and further comprises a third control node 34 that receives a third control signal, OFF2. Therein, the second control signal and the third control signal may be binary signals. That is, the second control signal and the third control signal may take one of two values, for example, of a high value “1” and a low value “0”. Therein, these values can be represented by specific voltages or specific currents. The SOC 30 is configured for outputting the output voltage GND.sub.DRIVER to a second output node 35 according to (or based on) the second and third control signals. In other words, the SOC 30 is configured to output a voltage for setting the high side SSS 150 to be non-conductive according to two signals, i.e., OFF1 and OFF2. For example, the SOC 30 may be configured to output the GND.sub.DRIVER if at least one of the two control signals OFF1 or OFF2 takes a specific value, e.g., a high value “1”. Otherwise, the SOC 30 does not output the GND.sub.DRIVER to the second output node 35 and hence the second output node 35 is floating. Therein, the output's dependency of the second control signal OFF1 and the third control signal OFF2 provides redundancy in setting the SSS 150 to be non-conductive and thus increases the operational safety of the SSS 150.

(26) The SSS driver circuit 100 further comprises a switch controller 50, which is another sub-circuit of the SSS driver circuit 100. The switch controller 50 is connected to the first output node 15 of the VGC 10 from which it receives the drive voltage VCC.sub.DRIVER generated according to the first control signal. The switch controller 50 is further connected to the second output node 35 of the shut off circuit 30 from which it receives the output voltage GND.sub.DRIVER according to the second and third control signal. The switch controller 50 further comprises a third ground node 53 that also receives the ground voltage GND. The switch controller 50 further comprises a fourth control node 54 that receives a fourth control signal ON1. According to some example embodiments, the fourth control signal is a binary signal, i.e., takes one of two values, e.g., either a high value “1” or a low value “0”. Therein, these values can be represented by specific voltages or specific currents. The switch controller 50 is configured to forward one of the received voltages, VCC.sub.DRIVER, and GND.sub.DRIVER, to a gate node 151 of the solid state switch 150 via an output node of the switch controller 50 and in according to the fourth control signal, ON1. In other words, if the fourth control signal takes a first value the switch controller 50 outputs VCC.sub.DRIVER and when the fourth control signal takes a second value the switch controller 50 outputs GND.sub.DRIVER or a floating voltage to the gate node 151.

(27) The SSS driver circuit 100 of the invention allows the operation of an SSS 150 using solely voltages supplied within the battery system as well as a minimal set of control signals, while maintaining high functional safety during operation. For example, only if ON1 is applied with a first value to switch controller 50, the VCC.sub.DRIVER voltage is output to the gate node 151 and the SSS 150 is set to be conductive. Otherwise, the voltage present at the second output node 35 is directly forwarded to the gate node 151. Further, if at least one of OFF1 or OFF2 is applied with a certain value to SOC 30, the GND.sub.DRIVER voltage is applied to the second output node 35 and, if ON1 takes a second value, to the gate node 151 and SSS 150 is set to be non-conductive. Hence, the SSS driver circuit 100 provides a cost-effective solution for controlling the SSS 150 without the need for, for example, a transformer for generating VCC.sub.DRIVER, and with improved redundancy in setting the SSS 150 to be non-conductive based on the two signals OFF1, OFF2.

(28) FIG. 2 schematically illustrates a solid state switch driver circuit 100 according to some example embodiments. The basic configuration of the embodiment as illustrated in FIG. 2 is identical to (or similar to) the embodiment as shown in FIG. 1. Accordingly, some repeated description may be omitted and the same reference signs are used for the same components. However, the embodiment of FIG. 2 is distinguished by the use of specific components as described in the following.

(29) For example, VGC 10 of the SSS driver circuit 100 of FIG. 2 comprises a first capacitor C1 16 with a first capacitor node 161 and a second capacitor node 162. The first capacitor node 161 is connected to the first input node 11 via a first diode 17. For example, the first capacitor node 161 is connected to the cathode of the first diode 17 and the cathode of the first diode 17 is connected to the first input node 11. The first capacitor node 161 is also connected to the first output node 15, i.e., is interconnected between the first output node 15 and the cathode of the first diode 17. The second capacitor node 162 is connected to ground node 13 via a first switch 18 and is connected to the second input node 12 via a second switch 19.

(30) For example, the first switch 18 is a first MOSFET T.sub.1 (n-channel) with a source node connected to the first ground node 13 and a drain node connected to the second capacitor node 162. The gate of the first MOSFET T.sub.1 is connected to the first control node 14, i.e., receives the first control signal, PWM. Hence, if PWM takes a high value, e.g., “1” or VDD, the ground voltage GND is applied to the second capacitor node 162 via the first switch 18. Then, the first capacitor 16 is charged via the first diode 17 with V.sub.SUP provided by the first input node 11 and hence a voltage drop between GND and V.sub.SUP may occur over C1.

(31) Further, the second switch 19 is a second MOSFET T.sub.2 (p-channel) with a source node connected to the second input node 12 and a drain node connected to second capacitor node 162. A gate node of second MOSFET T.sub.2 is connected to first ground node 13 via another n-channel MOSFET T.sub.10, a source node of which is connected to first ground node 13, a drain node of which is connected to the gate node of the second MOSFET T.sub.2 and a gate node of which is connected to the first control node 14 via an inverter 23. Hence, if the PWM takes a low value, e.g., “0” or VSS, the MOSFET T.sub.10 is set to be conductive and connects the first ground node 13 with the gate node of second MOSFET T.sub.2 and thus sets second MOSFET T.sub.2 to be conductive. Then, the second input node 12 is connected to the second capacitor node 162 which is thus set to the potential GND.sub.DRIVER. Due to the voltage drop over the charged first capacitor 16 C1 thus a voltage equal to the sum of V.sub.SUP and GND.sub.DRIVER applies to the first capacitor node 161. In other words, the VGC 10 operates as a DCDC converter with flying cap capacitor C1. Alternatively, also an n-channel MOSFET could be used for second switch T.sub.2, the gate of MOSFET T.sub.2 being then connected to the first control node 14 via the first converter 23.

(32) FIG. 3 schematically illustrates a solid state switch driver circuit 100 according some example embodiments. The basic configuration of the embodiment as illustrated in FIG. 3 is identical (or similar) to the embodiment as shown in FIGS. 1 and 2. Accordingly, some repeated description may be omitted and the same reference signs may be used for the same components. However, the embodiment of FIG. 3 is distinguished by the use of specific components as described in the following.

(33) For example, in the embodiment of FIG. 3, the VGC 10 further comprises a Zener diode 20 that is interconnected between the first output node 15 and the second input node 12. For example, the cathode of the Zener diode 20 is connected to a node that is interconnected between the first output node 15 and the first capacitor node 161 of the first capacitor 16. Further, the anode of the Zener diode 20 is connected to a node that is interconnected between the second switch 19 and the second input node 12. The Zener diode 20 functions as a protection diode that is configured for ensuring that the drive voltage VCC.sub.DRIVER is limited to a certain value. Accordingly, the third switch T.sub.3 may be protected.

(34) The VGC 10 of the third embodiment further comprises a second capacitor 21 that is interconnected in parallel to the first capacitor 16 in between the first output node 15 and the second input node 12. For example, a first capacitor node of the second capacitor 21 is interconnected between the first output node 15 and the node connected to the cathode of the Zener diode 20. Further, a second capacitor node of the second capacitor 21 is interconnected between the second input node 12 and the node connected to the anode of the Zener diode 20. During the operation of the VGC 10, the second capacitor 21 is charged with the voltage that applies to the first capacitor node 161 of the first capacitor 16 over the second diode 22. Hence, when the second switch is set to be conductive, the second capacitor 21 is charged with the drive voltage VCC.sub.DRIVER, i.e., the first capacitor node of the second capacitor 21 is charged to the drive voltage VCC.sub.DRIVER. Accordingly, the second capacitor 21 stores energy for setting the first output node 15 to VCC.sub.DRIVER even if the voltage V.sub.SUP or the first control signals PWM is not longer supplied to the VGC 10. Accordingly, the charged second capacitor 21 is configured to provide energy for setting SSS 150 conductive for a time period (e.g., a set or predetermined time period), for example, for a time period that allows fulfilling ASIL B requirements with respect to availability of the SSS 150, e.g., for a time of 35 seconds to 1 minute.

(35) FIG. 4 schematically illustrates a solid state switch driver circuit 100 according to some example embodiments. The basic configuration of the embodiment as illustrated in FIG. 4 is identical (or similar) to the embodiments as shown in FIGS. 1 to 3. Accordingly, some repeated description may be omitted and the same reference signs are used for the same components. However, the embodiment of FIG. 4 is distinguished by the use of specific components as described in the following.

(36) According to some example embodiments, as illustrated in FIG. 4, the solid state switch (SSS) 150 is specified to comprise at least one set of anti-serially interconnected FETs, wherein each set comprising at least one first FET, TA, 203 and at least one second FET, TB, 204. Therein, the gate contacts of the FETs 203, 204 are electrically interconnected and the source contacts of the FETs 203 and 204 are electrically interconnected. Further, the drain contact(s) of the at least one first FET 203 is/are electrically connected to the stack node 201 and the drain contact(s) of the at least one second FET 204 is/are electrically connected to the supply node 202. In this configuration, both FETs 203, 204 can be controlled at once by applying a gate voltage to the gates of the FETs 203, 204 via the gate node 151. Further, the SSS 150 comprises a first flyback (free wheeling) diode 205 connected in parallel with the first FET 203 and a second flyback diode 206 connected in parallel with the second FET 204, these diodes protecting the FETs 203, 204.

(37) Further, in FIG. 5 it is illustrated that the SOC 30 comprises a fifth switch 36 that is a fifth p-channel MOSFET T.sub.5 with a drain node connected to the third input node 31, for example, receiving GND.sub.DRIVER, and a drain node connected to the second output node 35. A gate node of MOSFET T.sub.5 is connected to the second ground node 33 via a sixth switch 38 that is a sixth n-channel MOSFET T.sub.6. For example, the source node of MOSFET T.sub.6 is connected to the second ground node 33, the drain node of MOSFET T.sub.6 is connected to the gate node of MOSFET T.sub.5 and a gate node of MOSFET T.sub.6 is connected to the second control node 32. That is, if the second control signal OFF1 takes a high value, e.g., “1” or VDD, MOSFET T.sub.6 is set to be conductive and applies ground voltage GND to the gate node of MOSFET T.sub.5. Hence, the gate channel of MOSFET T.sub.5 is set to be conductive and the cell stack's output voltage GND.sub.DRIVER is applied to the second output node and to the gate node 151 of the SSS 150, thus setting the FETs 203 and 204 to be non-conductive, hence disconnecting stack node 201 from supply node 202.

(38) Further, in FIG. 5 it is illustrated that the SOC 30 comprises a seventh switch 37 that is a seventh p-channel MOSFET T.sub.7 with a drain node connected to the third input node 31, i.e., receiving GND.sub.DRIVER, and a drain node connected to the second output node 35. A gate node of MOSFET T.sub.7 is connected to the second ground node 33 via an eighth switch 39 that is a eighth n-channel MOSFET T.sub.8. For example, the source node of MOSFET T.sub.8 is connected to the second ground node 33, the drain node of MOSFET T.sub.8 is connected to the gate node of MOSFET T.sub.7 and a gate node of MOSFET T.sub.8 is connected to the third control node 34. That is, if the third control signal OFF2 takes a high value, e.g., “1” or VDD, MOSFET T.sub.8 is set to be conductive and applies ground voltage GND to the gate node of MOSFET T.sub.7. Hence, the gate channel of MOSFET T.sub.7 is set to be conductive and the cell stack's output voltage GND.sub.DRIVER is applied to the second output node and to the gate node 151 of the SSS 150, thus setting the FETs 203 and 204 to be non-conductive, hence disconnecting stack node 201 from supply node 202.

(39) Further, in FIG. 5 it is specified that the switch controller 50 comprises a third switch 51 that is a third p-channel MOSFET T.sub.3 a source node of which is connected to the first output node 15 and a drain node of which is connected to the gate node 151, e.g., to a node interconnected between the gate node 151 and the second output node 35. That is, a voltage applied to the drain node of MOSFET T.sub.3 is applied to gate node 151 insofar it is higher than the voltage that applies to the second output node 35. The gate node of the MOSFET T.sub.3 is connected to the third ground node 53 via a fourth switch 52 that is a fourth n-channel MOSFET T.sub.4. The source node of MOSFET T.sub.4 is connected to the third ground node 53, the drain node of the MOSFET T.sub.4 is connected to the gate node of MOSFET T.sub.3 and the gate node of MOSFET T.sub.4 is connected to the fourth control node 54, i.e., receives fourth control signal ON1. That is, if the fourth control signal ON1 takes a high value, e.g., “1” or VDD, MOSFET T.sub.4 is set to be conductive and applies ground voltage GND to the gate node of MOSFET T.sub.3. Hence, the gate channel of MOSFET T.sub.3 is set to be conductive and the voltage at the first output node 15 is applied to the gate node 151 of SSS 150 setting FETs 203 and 204 to be conductive.

(40) FIG. 5 schematically illustrates a solid state switch driver circuit 100 according to some example. The basic configuration of the embodiment as illustrated in FIG. 5 is identical (or similar) to the embodiments as shown in FIGS. 1 to 4. Accordingly, some repeated description may be omitted and the same reference signs are used for the same components. However, the embodiment of FIG. 5 is distinguished by the use of specific components as described in the following.

(41) In the fifth embodiment as illustrated in FIG. 5, the SSS driver circuit 100 further comprises a first diagnostic circuit 60 that is configured to output a first diagnostic signal (DIAG.sub.1) indicating a potential at the second input node 12 and to output a second diagnostic signal (DIAG2) indicating a potential at the first output node 15. For example, the first diagnostic circuit 60 comprises a first voltage divider 61 with a first divider node connected to the second input node 12 and a second divider node connected to the first ground node 13. An output node of the first voltage divider 61 then provides the first diagnostic signal DIAG1. Further, the first diagnostic circuit 60 comprises a second voltage divider 62 with a first divider node connected to the first output node 15 and a second divider node also connected to first ground node 13. An output node of the second voltage divider 62 then provides the second diagnostic signal DIAG2. The first diagnostic circuit 60 thus provides diagnostic signals that are indicative of the voltage drop over the second capacitor 21 as described above.

(42) Hence, the first diagnostic circuit 60 allows detecting malfunctions in the battery system 200, as the first diagnostic circuit 60 receives the same voltage, GND.sub.DRIVER, as applied to the input of the SSS. The first diagnostic circuit further allows testing of the fifth switch T.sub.5 and the seventh switch T.sub.7. For example, if T.sub.3 is switched on, the switching off functionality of T.sub.7 and T.sub.9 can be diagnosed: Therefore, the drive voltage VCC.sub.DRIVER is generated with a voltage that is lower than V.sub.TH of the power MOSFETs 203, 204. Then, the functionality of T.sub.5 and T.sub.7 is tested individually by setting OFF1 and OFF2 to high signal individually and detecting the voltage with the first voltage divider 61, while third switch T.sub.3 is set to be conductive via ON1. Therein, as VCC.sub.DRIVER is controlled to be less than V.sub.TH of FETs 203, 204 the SSS 150 is not closed. By the same approach, also the functionality of third switch T.sub.3 can be tested by detecting DIAG 1 and comparing it to the signal DIAG2 representative of the voltage at first output node 15.

(43) In the fifth embodiment as illustrated in FIG. 5, the SSS driver circuit 100 further comprises a second diagnostic circuit 70 that is configured to output a third diagnostic signal (DIAG.sub.3) which is indicating a potential at the second output node 35. For example, the second diagnostic circuit 70 is configured to output a third diagnostic signal, DIAG.sub.3, indicating a potential at the drain node of the third switch MOSFET T.sub.3 or more precisely the voltage at a node interconnected between the drain node of MOSFET T.sub.3 and the second output node 35. The second diagnostic circuit 70 comprises a third voltage divider 71 with a first divider node connected in between the second output node 35 and the drain node of the third switch MOSFET T.sub.3 and a second divider node connected to ground, GND. The second diagnostic circuit 70 allows for testing the functionality of the switches T.sub.3 also while operating the voltage generation circuit 10 with a PWM signal that leads to an output voltage at the first output node that is less than the V.sub.TH of the power FETs 203, 204. The second diagnostic circuit may be further used for testing the switching off capability of the fifth and seventh switches T.sub.5, T.sub.7.

LISTING OF SOME REFERENCE NUMERALS AND SYMBOLS

(44) 100 solid state switch driver circuit 10 voltage generation circuit 11 first input node 12 second input node 13 first ground node 14 first control node 15 first output node 16 first capacitor 161 first capacitor node 162 second capacitor node 17 first diode 18 first switch 19 second switch 20 Zener diode 21 second capacitor 22 second diode 23 inverter 30 switch off circuit 31 third input node 32 second control node 33 second ground node 34 third control node 35 second output node 36 fifth switch 37 seventh switch 38 sixth switch 39 eighth switch 50 switch controller 51 third switch 52 fourth switch 53 third ground node 54 fourth control node 150 solid state switch (SSS) 151 gate node of SSS 200 battery system 201 stack node 202 supply node 203 first FET(s) 204 second FET(s) 205 first flyback diode 206 second flyback diode