Package structure

Abstract

A semiconductor package is provided and includes: an insulative layer having opposing first and second surfaces; a wiring layer embedded in the insulative layer and having a first side that is exposed from the first surface of the insulative layer and a second side opposing the first side and attached to the second surface of the insulative layer; at least one electronic component mounted on the second side of the wiring layer and electrically connected to the wiring layer; and an encapsulating layer formed on the second side of the wiring layer and the second surface of the insulative layer and encapsulating the electronic component. Therefore, the single wiring layer is allowed to be connected to the electronic component on one side and connected to solder balls on the other side thereof to shorten the signal transmission path.

Claims

1. A package structure, comprising: a single insulative layer having opposing first and second surfaces; a wiring layer embedded in the single insulative layer and having a first side that is exposed from the first surface of the single insulative layer and a second side opposing the first side and attached to the second surface of the single insulative layer, wherein the second side of the wiring layer comprises a plurality of conductive traces, the conductive traces are protruded from the second surface of the single insulative layer, the first side of the wiring layer is defined to have a plurality of conductive pads thereon, and the conductive pads are integrally formed with the conductive traces and exposed from the first surface of the single insulative layer, the first side of the wiring layer is recessed on the first surface of the single insulative layer and is bonded with a plurality of conductive elements, the wiring layer is formed by integrally etching a metal plate and has a T shape, and a horizontal side of the T-shaped wiring layer is a chip-placement side, and a vertical side of the T-shaped wiring layer is a ball-placement side; at least one electronic component mounted on the conductive traces of the second side of the wiring layer and electrically connected to the conductive traces; and an encapsulating layer formed on the second side of the wiring layer and the second surface of the single insulative layer and encapsulating the electronic component, wherein the wiring layer is covered by the encapsulating layer and supported by the single insulative layer.

2. The package structure of claim 1, wherein the second side of the wiring layer is electrically connected to the electronic component.

3. The package structure of claim 1, wherein the electronic component is an active component, a passive component, or a combination thereof.

4. The package structure of claim 1, wherein the electronic component is electrically connected to the wiring layer in a flip-chip manner.

5. The package structure of claim 1, wherein the plurality of conductive elements are formed on the conductive pads and electrically connected to the first side of the wiring layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a cross-sectional schematic view of a conventional QFP package structure;

(2) FIG. 1B is a cross-sectional schematic view of a conventional BGA package structure; and

(3) FIGS. 2A-2H are cross-sectional schematic views showing a method of fabricating a package structure according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(4) The present invention is described in the following with specific embodiments, so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention from the disclosure of the present invention.

(5) It should be noted that all the drawings are not intended to limit the present invention. Various modification and variations can be made without departing from the spirit of the present invention. Further, terms, such as “first”, “second”, “one” and etc., are merely for illustrative purpose and should not be construed to limit the scope of the present invention.

(6) FIGS. 2A-2G are cross-sectional schematic views showing a method of fabricating a package structure 2 according to the present invention.

(7) As shown in FIG. 2A, a conductive layer 20 having a first side 20a and an opposing second side 20b is provided.

(8) In an embodiment, the conductive layer 20 is formed of a metal material such as copper, but is not limited thereto.

(9) As shown in FIG. 2B, a patterning process is performed to etch away a portion of the first side 20a of the conductive layer 20, for forming a plurality of openings 200 via the first side 20a of the conductive layer 20.

(10) As shown in FIG. 2C, an insulative material is formed on the first side 20a of the conductive layer 20 and in the openings 200, allowing the insulative material to serve as an insulative layer 25 that completely covers the first side 20a of the conductive layer 20.

(11) In an embodiment, the insulative layer 25 is made of a primer or a dielectric material.

(12) As shown in FIG. 2D, a portion of the insulative material of the first side 20a of the conductive layer 20 is removed, with a portion of the insulative material corresponding to the openings 200 remained, such that the insulative layer 25 has a first surface 25a and an opposing second surface 25b, and the first side 20a of the conductive layer 20 is exposed from first surface 25a of the insulative layer 25.

(13) As shown in FIG. 2E, a patterning process is performed to remove a portion of the second side 20b of the conductive layer 20, allowing the conductive layer 20 to serve as a wiring layer 21, and the second surface 25b of the insulative layer 25 to be exposed from the second side 21b of the wiring layer 21.

(14) In an embodiment, the first side 21a of the wiring layer 21 is defined as having a plurality of conductive pads 210a.

(15) The wiring layer 21 further comprises a plurality of conductive traces 211 to extendingly and electrically connect with the conductive pads 210a.

(16) In another embodiment, a flattening process (such as grinding the insulative layer 25) is performed, to allow the first side of the wiring layer to be flush with the first surface of the insulative layer.

(17) As shown in FIG. 2F, at least one electronic component 22 is mounted on the second side 21b of the wiring layer 21, and the electronic component 22 is electrically connected with the wiring layer 21.

(18) In an embodiment, the electronic component 22 is an active component such as a semiconductor element (a chip), a passive component, such as a resistor, a capacitor and an inductor, or a combination thereof.

(19) Further, the electronic component 22 is electrically connected to the conductive pads 210a via a plurality of conductive bumps 220 and conductive traces 211.

(20) As shown in FIG. 2G, an encapsulating layer 23 is formed on the second side 21b of the wiring layer 21 and the second surface 25b of the insulative layer 25, and encapsulates the electronic components 22 and the conductive bumps 220.

(21) In an embodiment, the encapsulating layer 23 is formed on the carrier 20 by molding, coating or lamination method. The encapsulating layer 23 is made of a molding compound, a primer, or a dielectric material such as epoxy resin.

(22) In an embodiment, the top surface of the electronic component 22 may be exposed from the top surface of the encapsulating layer 23.

(23) In an embodiment, it is applicable to form the underfill (not shown) to encapsulate the conductive bumps 220, before the encapsulating layer 23 is formed.

(24) As shown in FIG. 2H, a plurality of conductive elements 24 such as solder balls are formed on the first surface 25a of the insulative layer 25, and a singulation process is performed along the cutting path S as shown in FIG. 2G, to obtain the plurality of package structures 2.

(25) In an embodiment, the conductive elements 24 are coupled and electrically connected to the conductive pads 210a of the wiring layer 21, so as for another electronic devices to be stacked thereon via the conductive elements 24 (not shown).

(26) In the method of fabricating the package structure 2, as merely the single wiring layer 21 is used, the second side 21b of the wiring layer 21 is coupled to the electronic component 22, and the first side 21a is coupled to the conductive elements 24, the signal pathway as well as the signal loss can be reduced, thereby significantly increasing the electrical performance.

(27) Since the package structure 2 according to the present invention requires only one wiring layer 21 to be fabricated, without the need of fabricating the conductive pillars, the overall thickness of the package structure 2 is reduced for meeting the low-profile requirement, and the fabricating cost is also greatly reduced.

(28) Further, since the single wiring layer 21 of the package structure 2 according to the present invention merely generates two interfaces (the first side 21a and second side 21b), the problem of delamination due to a high number of interfaces can be prevented. Besides, as the conductive layer 20 is directly patterned to form the wiring layer 21, the fabricating cost can be greatly reduced.

(29) In addition, since the insulative layer 25 according to the present invention is made of a single material, rather than different material required for a conventional carrier, the problem of warpage caused by CTE masmatch can be prevented.

(30) The package structure 2 comprises: an insulative layer 25, a wiring layer 21, at least one electronic component 22, and an encapsulating layer 23.

(31) The insulative layer 25 has a first surface 25a and an opposing second surface 25b.

(32) The wiring layer 21 is embedded in the insulative layer 25, and the wiring layer 21 has a first side 21a and an opposing second side 21b. The first side 21a of the wiring layer 21 is exposed from the first surface 25a of the insulative layer 25, and the second side 21b of the wiring layer 21 is attached to the second surface 25b of the insulative layer 25.

(33) The electronic component 22 is formed on the second side 21b of the wiring layer 21 and electrically connected to the wiring layer 21. In an embodiment, the electronic component 22 is an active component, a passive component, or a combination thereof, and the electronic component 22 is electrically connected to the second side 21b of the wiring layer 21 in a flip-chip manner.

(34) The encapsulating layer 23 is formed on the second side 21b of the wiring layer 21 and the second surface 25b of the insulative layer 25 and encapsulates the electronic components 22.

(35) In an embodiment, the second side 21b of the wiring layer 21 is for the electronic component 22 to be mounted thereon, and the first side 21a of the wiring layer 21 has a plurality of conductive pads 210a.

(36) In an embodiment, the first side 21a of the wiring layer 21 is flush with the first surface 25a of the insulative layer 25.

(37) In an embodiment, the package structure 2 further comprises a plurality of conductive elements 24 coupled to the first surface 25a of the insulative layer 25 and electrically connected to the first side 21a of the wiring layer 21.

(38) The present invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.