SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

A semiconductor device comprises a substrate body with a surface, a conductor comprising a conductor material covering at least part of the surface, and a dielectric that is arranged on a part of the surface that is not covered by the conductor. Therein, the conductor is in contact with the substrate body, the conductor and the dielectric form a layer, and a bonding surface of the layer has surface topographies of less than 10 nm, with the bonding surface facing away from the substrate body. Moreover, the semiconductor device is free of a diffusion barrier.

Claims

1. A semiconductor device comprising a substrate body with a surface; a conductor comprising a conductor material covering at least part of the surface; and a dielectric arranged on a part of the surface that is not covered by the conductor; wherein the conductor is in contact with the substrate body; the conductor and the dielectric form a layer; a bonding surface of the layer has surface topographies of less than 10 nm, with the bonding surface facing away from the substrate body; and the semiconductor device is free of a diffusion barrier.

2. The semiconductor device according to claim 1, wherein the conductor material comprises one of aluminum, titanium, tungsten, silicon, nitride or any combination thereof.

3. The semiconductor device according to claim 1, wherein the conductor comprises a sacrificial material, which is arranged on a surface of the conductor material facing away from the substrate body; and comprises a conductive material, such as titanium nitride, that is different from the conductor material.

4. The semiconductor device according to claim 1, wherein the substrate body comprises an insulating layer, such as an oxide layer, that is arranged on a substrate, such as a silicon substrate; and the surface is a surface of the insulating layer facing away from the substrate.

5. A semiconductor hybrid device comprising the semiconductor device according to claim 1; and a further semiconductor device with a further bonding surface; wherein the semiconductor device is bonded to the further semiconductor device.

6. The semiconductor hybrid device according to claim 5, wherein the semiconductor device is a CMOS device; and the further semiconductor device is a MEMS and/or CMOS device.

7. The semiconductor hybrid device according to claim 5, wherein the further semiconductor device and the semiconductor device are a same type of semiconductor device.

8. A method of manufacturing a semiconductor device comprising: providing a substrate body with a surface; depositing a conductor on the surface; patterning and structuring the conductor; depositing a dielectric on the conductor and on exposed parts of the surface; and creating a bonding surface of the semiconductor device by removing part of the dielectric using a plurality of chemical-mechanical planarization, CMP, steps; wherein the bonding surface has surface topographies of less than 10 nm.

9. The method according to claim 8, further comprising hybrid bonding a further semiconductor device to the bonding surface.

10. The method according to claim 8, wherein depositing the conductor comprises depositing a conductor material on the surface and depositing a sacrificial material on the conductor material; and creating the bonding surface comprises removing at least part of the sacrificial material.

11. The method according to claim 10, wherein depositing the sacrificial material comprises depositing a conductive material that differs from the conductor material; or a dielectric material that differs from a material of the dielectric layer.

12. The method according to claim 10, wherein the sacrificial material is completely removed during the plurality of CMP steps.

13. The method according to claim 8, wherein the plurality of CMP steps are performed consecutively.

14. The method according to claim 8, wherein at least one of the plurality of CMP steps is a timed CMP step.

15. The method according to claim 8, wherein the plurality of CMP steps differ from each other in terms of slurry composition and/or material selectivity.

16. The method according to claim 8, wherein the plurality of CMP steps comprises a dielectric removal step and a buffing step.

17. The method according to claims 8, wherein a first of the plurality of CMP steps is performed using a first slurry that predominantly removes the dielectric; and a second of the plurality of CMP steps is performed using a second slurry that has a selectivity regarding the dielectric and a material of the conductor, that is between 0.9 and 1.1.

18. The method according to claim 8, wherein slurries used during the plurality of CMP steps are non-ceria based slurries.

19. The method according to claims 8, wherein the method of manufacturing is CMOS-compatible.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The following description of figures of exemplary embodiments may further illustrate and explain aspects of the improved concept. Components and parts of the semiconductor device with the same structure and the same effect, respectively, appear with equivalent reference symbols. Insofar as components and parts of the semiconductor device correspond to one another in terms of the function in different figures, the description thereof is not repeated for each of the following figures.

[0055] FIGS. 1A to 1E show cross sections of intermediate steps of an exemplary embodiment of the improved manufacturing method of a semiconductor device;

[0056] FIG. 2 shows a cross section of an alternative embodiment of the semiconductor device manufactured following an alternative embodiment of the manufacturing method;

[0057] FIG. 3 shows a cross section of an exemplary embodiment of a semiconductor device;

[0058] FIG. 4 shows a cross section of an exemplary embodiment of a hybrid semiconductor device;

[0059] FIG. 5 shows a cross section of a further exemplary embodiment of a semiconductor device; and

[0060] FIG. 6 shows a cross section of a further exemplary embodiment of a hybrid semiconductor device.

DETAILED DESCRIPTION

[0061] FIG. 1A to 1E show cross sections of intermediate steps of an exemplary manufacturing method of a semiconductor device 1 according to the improved concept. In this embodiment, a second step of chemical-mechanical planarization, CMP, entirely removes the sacrificial material 5b deposited on the conductor material 5a.

[0062] FIG. 1A shows a cross section of an intermediate product of a semiconductor device 1 after depositing a layer of conductor material 5a on a surface 3 of a substrate body 2, and a layer of sacrificial material 5b on a surface of the layer of conductor material 5a facing away from the substrate body 2. The substrate body 2 comprises a substrate material, which may be silicon. The substrate body 2 may also comprise an integrated circuit, which may in particular be a CMOS circuit with active and/or passive circuitry. Such integrated circuits are known per se, and are not shown in the figures. The substrate body 2 at this stage may be a wafer or a chip diced from a wafer, for instance. The surface 3 of the substrate body 2 is, for example, a surface parallel to the main extension plane of the substrate body 2 and may be referred to as a top surface without loss of generality.

[0063] The layer deposited on the surface 3 is of a conductor material 5a, such as aluminum, titanium, tungsten, silicon, nitride or any combination thereof. A thickness of said layer typically is in the order of 300 nm to 3 μm but can also be smaller or larger depending on specific requirements of the finalized conductor 5 of the semiconductor device 1.

[0064] The layer of sacrificial material 5b is deposited on a surface of the layer of conductor material 5a that faces away from the substrate body 2. The sacrificial material 5b may either be a conductive material, such as titanium nitride, that is different from the conductor material 5a, or a dielectric material, such as an oxide. A thickness of said layer may be smaller or larger than the layer of the conductor material 5a or be equal in thickness, depending on requirements of subsequent steps of the fabrication process, for instance. Typically, the sacrificial material 5b is deposited with a thickness in the order of 100 nm to 1 μm.

[0065] FIG. 1B shows a cross section of the intermediate product according to FIG. 1A after patterning and structuring the conductor material 5a and the sacrificial material 5b. The patterning and structuring may be performed by means of lithography, such as photo or electron beam lithography, in combination with a wet or dry etching step. Patterning and structuring therefore exposes parts of the surface 3 of the substrate body while the remaining structured conductor material 5a and sacrificial material 5b form a conductor stack on the surface 3, wherein the conductor stack is in contact with the substrate body 2.

[0066] FIG. 1C shows a cross section of the intermediate product according to FIG. 1B after depositing a dielectric 4. Depositing the dielectric 4 means depositing a dielectric material on the conductor stack and onto the surface 3 of the substrate body. The dielectric material is thereby different from the sacrificial material. For example, the dielectric material is an oxide such as silicon dioxide. The deposition of the dielectric 4 is performed such that the conductor stack is buried in the dielectric 4. In other words, a thickness of the dielectric 4 measured from the surface 3 of the substrate body 2 in a vertical direction perpendicular to a main extension plane of the substrate body 2 is at least as large as the thickness of the conductor stack.

[0067] FIG. 1D shows a cross section of the intermediate product according to FIG. 1C after a first step of CMP. During this first step, part of the dielectric 4 is removed such that the dielectric 4 is reduced in thickness at least until the sacrificial material 5b is exposed. In some cases, the first step of CMP may be performed to a point at which also a thickness of the sacrificial material 5b is reduced. However, the sacrificial material 5b is not completely removed during the first step of CMP. The first step of CMP for example is performed using a first slurry that is configured to remove the dielectric material. For example, the first slurry is a standard silicon dioxide slurry.

[0068] FIG. 1E shows a cross section of the semiconductor device 1 according to FIG. 1E after a second step of CMP. During this second step that may also be referred to as a buffing step, the dielectric 4 and the sacrificial material 5b could be removed until the conductor material 5a is exposed to form the finalized conductor 5. After this step, the conductor 5 and the dielectric 4 form a layer 8, meaning that a thickness of the conductor 5 corresponds to a thickness of the dielectric 4. As a result, the bonding surface 6 is a surface of said layer 8. The second step of CMP differs from the first step of CMP in terms of slurry composition and/or material selectivity, for instance. For example, a selectivity of the slurry between the dielectric 4 and the sacrificial material 5b is unity such that both materials are evenly removed. In some cases, the second slurry may have a selectivity regarding the dielectric 4 and the sacrificial material 5b that is different from unity. For example, the selectivity is in the range between 0.9 and 1.1 in order to optimize micro topographies to achieve improved results.

[0069] For example, the second slurry does not contain contaminants, such as ceria, that would leave residues on any planarized surface and hence would require further steps of cleaning.

[0070] The second step of CMP hence leads to the planarized bonding surface 6 of the semiconductor device 1 that is characterized by surface topographies of less than 10 nm size and therefore may be regarded as atomically smooth.

[0071] FIG. 2 shows a cross section of an alternative embodiment of the semiconductor device manufactured following an alternative embodiment of the manufacturing method of a semiconductor device 1 compared to that of FIGS. 1A to 1E. In this embodiment, the sacrificial material 5b is not entirely removed during the second step of CMP and therefore remains as part of the conductor 5 on the finalized semiconductor device 1, as illustrated in FIG. 2.

[0072] In this embodiment, the sacrificial material 5b is a conductive material and together with the conductor material 5a form the finalized conductor 5 of the semiconductor device 1. Leaving a layer of the sacrificial material 5b on the finalized semiconductor device 1 may have the advantage that the sacrificial material 5b promotes a bonding to a further semiconductor device. A thickness of the sacrificial material 5b on the finalized product may be up to 50 nm. A suitable choice for the sacrificial material in this case is titanium nitride, for instance.

[0073] FIG. 3 shows an embodiment of the semiconductor device 1 comprising multiple conductors 5 on the surface 3 of the semiconductor body. The fabrication is analogous to that shown in FIGS. 1A to 1E. Multiple conductors 5 may be required for providing connections to multiple points of an integrated circuit comprised by the substrate body 2.

[0074] A further difference is that the substrate body 2 in this embodiment comprises besides a substrate 2a also an insulating layer 2b to provide electrical insulation of active circuitry of the substrate body 2, for example. The insulating material may be the same as the dielectric 4, such as silicon dioxide.

[0075] FIG. 4 shows a cross section of an exemplary embodiment of a hybrid semiconductor device 10 comprising two semiconductor devices 1, 1a according to the improved concept. The bonding surfaces 6 of the semiconductor devices 1, 1a are bonded to each other by means of direct wafer bonding, for instance. For example, the first semiconductor device 1 is a CMOS device comprising active circuitry for evaluating signals from a transducer while the further semiconductor device 1a is a MEMS device comprising said transducer.

[0076] For providing electrical interconnections, the conductors 5 of the semiconductor devices 1, 1a are connected to active and/or passive circuitry by means of vias 7, such as tungsten vias, for example. The conductors 5 are dimensioned such that offsets due to an imperfect bonding or manufacturing tolerances only insignificantly, if at all, influence the electrical interconnection.

[0077] FIGS. 5 and 6 shows alternative embodiments of the semiconductor device 1 and the semiconductor hybrid device 10, respectively. Compared to those embodiments shown in FIGS. 3 and 4, these embodiments are characterized by residual sacrificial material 5b on the conductor material 5a of each semiconductor device 1, 1a. As described in line with the embodiment of the semiconductor device of FIG. 2, the residual sacrificial material 5b may be beneficial for bonding and lead to an improved result in some cases.

[0078] The embodiments shown in the FIGS. 1A to 6 as stated represent exemplary embodiments of the semiconductor device 1, of the semiconductor hybrid device 10, as well as of the manufacturing method according to the improved concept. Therefore they do not constitute a complete list of all embodiments according to the improved concept. Actual semiconductor device configurations may vary from the embodiments shown in terms of shape, size and materials, for example.