FSK RADIO-FREQUENCY DEMODULATORS

Abstract

A demodulator for a digital radio receiver comprises a frequency discriminator and a Viterbi decoder. The frequency discriminator receives a series digital signal samples representative of an FSK-modulated signal and performs frequency discrimination on the digital signal samples to generate a series of frequency samples. Each frequency sample represents an instantaneous frequency of the signal in a respective frequency-sample period. There are an integer oversampling factor, N>1, of frequency-sample periods in each symbol period. The Viterbi decoder receives the series of frequency samples, determines branch metrics for each symbol period by determining distances between a vector of N successive frequency samples and each of a plurality of reference waveform vectors, each comprising N elements. It use the branch metrics in a Viterbi process to output demodulated symbol values corresponding to a maximum-likelihood decoding of the FSK-modulated signal.

Claims

1. A demodulator for a digital radio receiver, the demodulator comprising: a frequency discriminator; and a Viterbi decoder, wherein the frequency discriminator comprises: an input for receiving a series digital signal samples representative of a frequency-shift-key (FSK)-modulated signal; and digital logic for performing frequency discrimination on the digital signal samples to generate a series of frequency samples, wherein each frequency sample is representative of an instantaneous frequency of the FSK-modulated signal in a respective frequency-sample period, and wherein there are an integer oversampling factor, N, greater than one, of frequency-sample periods in each symbol period of the FSK-modulated signal, and wherein the Viterbi decoder is arranged to: receive the series of frequency samples from the frequency discriminator; determine a plurality of branch metrics for each symbol period of the FSK-modulated signal by determining a plurality of distances between a vector of N successive received frequency samples and each of a plurality of reference waveform vectors, wherein each reference waveform vector comprises N elements; use the determined branch metrics in a Viterbi process to determine a maximum-likelihood decoding of the FSK-modulated signal; and output a series of demodulated symbol values corresponding to the maximum-likelihood decoding of the FSK-modulated signal.

2. The demodulator of claim 1, configured to demodulate a Gaussian-filtered FSK-modulated signal and wherein the reference waveform vectors comprise elements that correspond to Gaussian-filtered waveforms.

3. The demodulator of claim 1, configured to demodulate an FSK-modulated signal modulated on M frequencies, wherein M is equal to two or more, and wherein the Viterbi decoder has M.sup.k states, wherein k is an integer equal to two or more.

4. The demodulator of claim 1, configured to demodulate a binary FSK-modulated signal, filtered with a Gaussian filter having a bandwidth-symbol time product between 0.2 and 0.3, and wherein the Viterbi decoder has four states.

5. The demodulator of claim 1, wherein the plurality of reference waveform vectors consists of eight reference waveform vectors.

6. The demodulator of claim 1, wherein the oversampling factor N is less than ten.

7. The demodulator of claim 1, wherein the frequency discriminator is configured to multiply the signal samples with a delayed copy of the signal samples.

8. The demodulator of claim 1, wherein the Viterbi decoder is implemented as a dedicated hardwired circuit.

9. The demodulator of claim 1, implemented on an integrated-circuit chip.

10. A digital radio receiver comprising a demodulator as claimed in claim 1.

11. The digital radio receiver of claim 10, comprising an antenna for receiving the frequency-shift-key (FSK)-modulated signal as a radio signal, and comprising dedicated digital logic or a processor for further processing the series of demodulated symbol values.

12. The digital radio receiver of claim 10, configured for receiving and demodulating radio signals having a carrier frequency between 2.4 and 2.5 GHz.

13. The digital radio receiver of claim 10, configured for receiving and demodulating radio signals modulated according to a Bluetooth™ specification.

14. The digital radio receiver of claim 10, configured for receiving and demodulating radio signals that are modulated on a channel having a width of 4 MHz and that have a data rate exceeding 2 Mbps.

15. A method for demodulating a frequency-shift-key (FSK)-modulated signal, the method comprising: receiving a series digital signal samples representative of the frequency-shift-key (FSK)-modulated signal; performing frequency discrimination on the digital signal samples to generate a series of frequency samples, wherein each frequency sample is representative of an instantaneous frequency of the FSK-modulated signal in a respective frequency-sample period, and wherein there are an integer oversampling factor, N, greater than one, of frequency-sample periods in each symbol period of the FSK-modulated signal; determining a plurality of branch metrics for each symbol period of the FSK-modulated signal by determining a plurality of distances between a vector of N successive received frequency samples and each of a plurality of reference waveform vectors, wherein each reference waveform vector comprises N elements; using the determined branch metrics in a Viterbi process to determine a maximum-likelihood decoding of the FSK-modulated signal; and outputting a series of demodulated symbol values corresponding to the maximum-likelihood decoding of the FSK-modulated signal.

16. The method of claim 15, wherein the FSK-modulated signal is a Gaussian-filtered FSK-modulated signal, and wherein the reference waveform vectors comprise elements that correspond to Gaussian-filtered waveforms.

17. The method of claim 15, wherein the FSK-modulated signal is modulated on M frequencies, wherein M is equal to two or more, and wherein the Viterbi decoder has M.sup.k states, wherein k is an integer equal to two or more.

18. The method of claim 15, wherein the FSK-modulated signal is a binary FSK-modulated signal, filtered with a Gaussian filter having a bandwidth-symbol time product between 0.2 and 0.3, and wherein the Viterbi decoder has four states.

19. The method of claim 15, wherein the FSK-modulated signal has a carrier frequency between 2.4 and 2.5 GHz.

20. The method of claim 15, wherein the FSK-modulated signal has a data rate exceeding 2 Mbps and is modulated on a channel that has a width of 4 MHz.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Certain preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0047] FIG. 1 is a schematic drawing of a radio communication system including a radio receiver device embodying the invention;

[0048] FIG. 2 is a schematic drawing of receiver circuitry in the radio receiver device; and

[0049] FIG. 3 is a schematic drawing of a demodulator in the receiver circuitry.

DETAILED DESCRIPTION

[0050] FIG. 1 shows an exemplary wearable wireless heart-rate monitor 1 which is in communication with a mobile telephone 7. The heart-rate monitor 1 implements the present invention.

[0051] The wireless heart-rate monitor 1 has a heart-rate sensor 2 which is connected to a radio-on-a-chip 3. The radio-on-a-chip 3 comprises a microcontroller unit (MCU) 4, e.g. based around an ARM™ Cortex M-series processor, and a radio transceiver 5. The radio-on-a-chip 3 and/or MCU 4 may include other components, such as volatile and non-volatile memory, other peripherals, etc. The heart-rate monitor 1 has a radio antenna 6, which may be integrated on the chip 3 or external to it, as well as other standard components, such as a battery, a display screen, buttons, off-chip memory, amplifier circuitry, discrete electronics components, etc. The antenna 6 is suitable for transmitting and receiving short-range radio communications—e.g. according to a 2.4 GHz protocol such as Bluetooth Low Energy™ (BLE).

[0052] The mobile telephone 7 has a microcontroller unit (MCU) 8 and radio transceiver circuitry 9. These may be integrated on a common chip, or be provided as separate integrated circuit chips. The radio transceiver 9 is connected to an antenna 10 that is suitable exchanging short-range radio communications with wireless personal-area-network devices—e.g. according to a 2.4 GHz protocol such as Bluetooth Low Energy™. The telephone 7 may include further components, such as further microprocessors, other radio chips, a display screen, a battery, etc. It may run an operating system and software applications.

[0053] In use, the wireless heart-rate monitor 1 receives periodic heart-rate readings for a human user from the heart-rate sensor 2. The MCU 4 processes the readings into a suitable format for transmission, and controls the radio transceiver 5 to transmit the data to the mobile telephone 7 by a short-range 2.4 GHz radio message. The heart-rate monitor 1 receives a radio acknowledgement message 12 from the mobile telephone 7, generated by the transceiver 9 and transmitter through the antenna 10 of the telephone 7. The radio message 12 is received at the antenna 6 of the heart-rate monitor 1 and decoded by its radio transceiver 5.

[0054] These radio messages may be exchanged using a protocol complying with an existing or future Bluetooth™ standard, which may be a Bluetooth Low Energy™ protocol. In some embodiments, it uses such a protocol in which data is transmitted in a 4 MHz channel, potentially at a data rate exceeding 2 Mbps, such as 4 Mbps. At such high data rates, receiver sensitivity becomes particularly important in order to avoid decoding errors.

[0055] In one example embodiment, radio messages 12 received by the radio transceiver 5 contain encoded data that is modulated on a radio-frequency carrier at around 2.4 GHz using two-level Gaussian frequency-shift keying (GFSK) with a modulation index, h, of 0.5, and with a Gaussian pulse-shaping filter bandwidth-time product, BT, of 0.25 (where B is the −3 dB bandwidth of the filter, and T is the bit duration). Such a filter helps reduce sideband power but creates significant “smear” across bits, leading to high intersymbol interference (ISI), placing additional requirements on receiver sensitivity.

[0056] The radio transceiver 5 performs non-coherent detection of the GFSK signal 12. It uses a frequency discriminator and a Viterbi decoder as a demodulator (i.e. a bit detector), in order to detect a bitstream from the received signal 12, which it can then pass to the microcontroller 4 for further processing. It is important to note that the Viterbi decoder is not here being used to perform a deconvolution decoding of a convolution-encoded data stream, but rather to generate a raw demodulated bitstream from the received RF signal.

[0057] In some embodiments, the bitstream may potentially include convolution-encoded data, but this is not essential, and it is also not of relevance here. The radio-on-a-chip 3 may optionally include logic for performing a subsequent deconvolution operation on the detected bitstream, to decode convolution-encoded data, but that would be separate from this Viterbi decoder 27—e.g. being provided by software executing in the microcontroller 4 or by a further hardware Viterbi decoder circuit (not shown) in the transceiver 5. In some embodiments, the first Viterbi decoder 27 may be configured to perform a soft-output Viterbi algorithm in order to output soft-decision bit values (e.g. a value between 0 and 1), rather than hard-decision bits. This may improve the performance of any subsequent decoding, e.g. by a further Viterbi decoder.

[0058] FIG. 2 provides more detail of the receive-side circuitry in the radio transceiver 5 of the heart-rate monitor 1.

[0059] The 2.4 GHz radio-frequency electrical signal from the antenna 6 is received by a low-noise amplifier 20. The amplified analogue signal is then filtered by an analogue bandpass filter 21 and passed to a quadrature mixer 22 which down-mixes the signal to a lower intermediate frequency (IF). The down-mixed signal is then sampled by an analogue-to-digital converter (ADC) 23. Further filtering may be applied by one or more digital filters 24. The filtered samples are then passed to a demodulator (i.e. a bit detector) 25, which includes a frequency discriminator 26, a Viterbi decoder 27, and a store of reference waveform vectors 28.

[0060] The frequency discriminator 26 acts on the quadrature samples to generate a stream of values that are proportional to the frequency of the received signal. It may do this in any appropriate way. For example, it may implement a digital delay-and-multiply process followed by a low-pass filter, so as to generate a signal that is proportional to the frequency of the sampled down-mixed signal. The frequency discriminator 26 outputs a stream of digital frequency samples at an oversampling rate N—i.e. such that there are N samples for each received bit. N may equal four or eight, or any other value greater than one.

[0061] The frequency samples are passed to a soft-decision Viterbi decoder 27. The Viterbi decoder 27 iterates at each bit period.

[0062] Because the pulse width of a Gaussian pulse shaping filter with BT=0.25 spans approximately two bits, the GFSK modulator in the transmitter 8 can be viewed as a state machine having four states, depending on whether the preceding two bits were “00”, “01”, “10” or “11”. Each bit received by the transceiver 5 can therefore be considered to be a function of i) the modulator state (i.e. what the preceding two bits were), ii) the current modulator input, and iii) the channel. The Viterbi decoder 27 therefore has four states, corresponding to the four possible states of the modulator. Simulations have confirmed the effectiveness of this approach.

[0063] If a different transmission shaping filter, spanning more bits, is used, the Viterbi decoder could have correspondingly more states—e.g. having eight or sixteen states if the filter spans three or four bits.

[0064] Within the Viterbi decoder 27, for each received FSK-encoded bit, a vector of the N frequency samples received from the frequency discriminator 26 for the current bit period is compared with each of eight reference waveform vectors 28, (wref.sub.0,wref.sub.1, . . . , wref.sub.7) each having N elements, by calculating a respective squared Euclidean distance between the frequency-sample vector and each reference waveform vector 28.

[0065] In this embodiments there are eight reference waveform vectors 28 because the trellis has four states (corresponding to the four modelled states of the GFSK modulator, depending on whether the preceding two bits were “00”, “01”, “10” or “11”), and because each state has two possible next states, “0” or “1”, amounting to eight branches in total. Each eight reference waveform vector is pre-calculated to represent the output from a GFSK modulator of BT=0.25 given that the Gaussian filter contains one the preceding bit pairs “00”, “01”, “10” or “11” with the next message input bit to the modulator being either “0” or “1”.

[0066] These comparisons produce a set of eight branch-metric values, bm.sub.j, for j={0, . . . , 7}, as follows:

[00001]$b{m}_j=\underset{i=0}{\overset{N-1}{.Math.}}{\left({\mathrm{wref}}_{j,i}-{\mathrm{fm}}_i\right)}^2$

[0067] where fm.sub.i is the received frequency sample i indexed over the current bit period (0≤i<N), and wref.sub.j,i is the i.sup.th reference sample from the reference waveform j.

[0068] The 8× N reference waveform vector elements 28 may be stored by being hardwired into the digital logic of the hardware Virterbi decoder 27 circuitry (e.g. as corresponding shift and accumulate operations), or they may be retrieved by the Viterbi decoder 27 from volatile or non-volatile registers or from a random access memory (RAM) as inputs to one or more multipliers.

[0069] FIG. 3 shows the Viterbi decoder 27 part of the demodulator 25 in more detail. For reasons of speed, power and silicon area, the demodulator 25 is here implemented in hardware (i.e. using dedicated logic gates) on the chip 3. However, in other embodiments, some or all of the demodulator operations could potentially be implemented by software executing on a processor.

[0070] A branch-metric unit 30 receives N samples for each bit, from the frequency discriminator 26, and calculates a set of branch-metric values, bm.sub.j, for each bit pair, one bit at a time, as described above. These branch metrics are then input to a path-metric unit 31 which uses them to calculate new path metrics at each bit period, based on the preceding path metrics and the new branch metrics, according to the Viterbi algorithm. It compares the path metrics and selects the most likely paths, using the Viterbi algorithm.

[0071] In some embodiments, decision bits from the path-metric unit 31, representing survivor paths, are stored in sequence in the trace-back unit 32, and used for trace back after the maximum-likelihood survivor path has been determined. The path metrics may be accumulated over any appropriate number of bits. They could potentially be accumulated over an entire message, but it may be less than this—e.g. for reasons of speed or resource efficiency. Some embodiments accumulate over 12 bits, which simulations have suggested can still provide good performance. A first-in-last-out (FILO) buffer 33 reverses the path order, so that the decoder 27 outputs a chronological stream of hard-decision bit values, representing the data bits detected from the received signal 12.

[0072] In other embodiments, the Viterbi decoder may use a Register Exchange (RE) architecture, instead of a trace-back unit 32, which may provide a more efficient implementation, given the relatively small size of this Viterbi decoder.

[0073] The output bits may be further processed in hardware and/or software as appropriate—e.g. to check that the mobile telephone 7 correctly received the transmitted heart-rate data, in this example.

[0074] In some variants, the Viterbi decoder may output soft-bits, instead of or as well as hard-bits. This may facilitate further decoding by a downstream decoder, e.g. in cases where the received data is convolution-encoded and requires further processing by a second Viterbi decoder.

[0075] The radio transceiver 5 may include circuitry for performing frame-level and bit-level timing synchronisation. It may include circuitry for automatic gain control, and for other conventional operations related to receiving and decoding digital radio signals. The radio transceiver 5 also includes conventional transmitter circuitry for transmitting radio messages.

[0076] This receiver architecture has been found to offer high sensitivity, making it well suited for receiving signals modulated using a relatively wide Gaussian filter (e.g. spanning two or more bits), which results in high levels of inter-symbol interference (ISI).

[0077] Although embodiments have been described for demodulating binary FSK signals, it will be appreciated that the same principles can also be applied for demodulating higher-level FSK modulated signals, such as four-level FSK (4FSK) or higher, in other embodiments. In this case, the number of states of the Viterbi decoder will increase, as will the number of reference waveform vectors.

[0078] While the receiver design is well suited to demodulating signals transmitted with Gaussian shaping (which helps to reduce sideband power, thereby reducing interference between adjacent channels), the use of GFSK is not essential, and some embodiments may be used to receive differently-shaped BFSK signals, or non-filtered BFSK-modulated signals, by using appropriate reference waveform vectors 28 in the Viterbi decoder 27.

[0079] It will be appreciated by those skilled in the art that the invention has been illustrated by describing one or more specific embodiments thereof, but is not limited to these embodiments; many variations and modifications are possible, within the scope of the accompanying claims.