METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Abstract

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.

Claims

1. A method of manufacturing a semiconductor device, the method comprising: forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.

2. The method of claim 1, wherein the forming of the re-routing layer comprises: creating a first opening in the insulating layer to expose a portion of the metal pad; filling in the first opening simultaneously with the deposition of the bonding dielectric; creating a second opening in the bonding dielectric and recreating the first opening; and depositing a conductive material in the first opening and the second opening.

3. The method of claim 2, wherein the deposition of the conductive material in the first opening and the second opening comprises: overfilling the first opening and the second opening with a copper-containing conductive material, wherein the copper-containing conductive material covers the bonding dielectric; and polishing the copper-containing material to expose a top surface of the bonding dielectric, wherein a top surface of the re-routing layer is coplanar with the top surface of the bonding dielectric after the polishing of the copper-containing conductive material.

4. The method of claim 2, wherein a top surface of the insulating layer is exposed through the second opening.

5. The method of claim 2, wherein a remaining insulating layer is left after the removal of the regions of the insulating layer, and an included angle between the interconnect layer and sidewalls of the remaining insulating layer is greater than 90 degrees.

6. The method of claim 2, further comprising performing a planarizing process to provide the bonding dielectric with a substantially planar top surface.

7. The method of claim 6, wherein the bonding dielectric is planarized from 5.5 μm to 3 μm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims. The disclosure should also be understood to be coupled to the figures' reference numbers, which refer to similar elements throughout the description.

[0023] FIG. 1 is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure.

[0024] FIG. 2 is a cross-sectional view of a semiconductor device assembly in accordance with some embodiments of the present disclosure.

[0025] FIG. 3 is a flow diagram illustrating a method of manufacturing a semiconductor device in accordance with some embodiments of the present disclosure.

[0026] FIGS. 4 through 12 illustrate cross-sectional views of intermediate stages in the formation of a semiconductor device in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

[0027] Embodiments, or examples, of the disclosure illustrated in the drawings are now described using specific language. It shall be understood that no limitation of the scope of the disclosure is hereby intended. Any alteration or modification of the described embodiments, and any further applications of principles described in this document, are to be considered as normally occurring to one of ordinary skill in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that feature(s) of one embodiment apply to another embodiment, even if they share the same reference numeral.

[0028] It shall be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

[0029] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting to the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It shall be understood that the terms “comprises” and “comprising,” when used in this specification, point out the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0030] FIG. 1 is a cross-sectional view of a semiconductor device 10 in accordance with some embodiments of the present disclosure. Referring to FIG. 1, the semiconductor device 10 includes a substrate 100, one or more semiconductor components 110 in the substrate 100, an interconnect layer 120 disposed on the semiconductor components 110, a re-routing layer 130 in contact with the interconnect layer 120, a bonding dielectric 140 over the interconnect layer 120 and an insulating layer 151 between the interconnect layer 120 and the bonding dielectric 140 to surround the re-routing layer 130.

[0031] In some embodiments, the substrate 100 is a semiconductor substrate made of silicon. In alternative embodiments, the substrate 100 may include other semiconductor material such as III-V semiconductor materials. The semiconductor component 110 may include doped regions, isolation features and various layers that are not separately depicted and that combine to form various microelectronic elements, such as metal-oxide semiconductor (MOS) components.

[0032] The re-routing layer 130 is electrically coupled to the semiconductor component 110 through the interconnect layer 120 by methods including alternate stacking of metallic pads M1, M2, M3 and vias V1, V2, V3 embedded in dielectric materials ILD1, ILD2, ILD3. In some embodiments, the re-routing layer 130 includes a bottom portion 132 in direct contact with the interconnect layer 120 and surrounded by the insulating layer 151, and a top portion 134 integrated with the bottom portion 132 and surrounded by the bonding dielectric 140. In some embodiments, the bottom portion 132 has a first width W1 and the top portion 134 has a second width W2 greater than the first width W1 when viewed in a cross-sectional view. In some embodiments, the first width W1 gradually decreases at positions of decreasing distance from the semiconductor component 110, and the second width W2 is a substantially consistent width. In some embodiments, the insulating layer 150 contacts the top portion 134.

[0033] In some embodiments, the re-routing layer 130 made of copper-containing material is easy to diffuse; thus a diffusion barrier layer 160 is laid at least between the re-routing layer 130 and the bonding dielectric 140 and between the re-routing layer 130 and the insulating layer 151. The diffusion barrier layer 160 may also lie between the re-routing layer 130 and the interconnect layer 120. In some embodiments, a top surface 162 of the diffusion barrier layer 160 is level with a top surface 136 of the re-routing layer 130, which is coplanar with a top surface 142 of the bonding dielectric 140. Refractory metals (such as titanium or tantalum), refractory metal nitrides (such as titanium nitride or tantalum nitride), and refractory metal silicon nitrides (such as titanium silicon nitride or tantalum silicon nitride) are typically used for the diffusion barrier layer 160.

[0034] In exemplary embodiments, the bonding dielectric 140 above the insulating layer 151 includes a first thickness T1, and the insulating layer 151 has a second thickness T2 less than the first thickness T1. The insulating layer 150 has either a single-layer structure or a stacked-layer structure, and includes a silicon nitride film. In such embodiments, the insulating layer 151 includes an overlying film 153 of silicon nitride, contacting the bonding dielectric 140, and an underlying film 155 between the interconnect layer 120 and the overlying film 153. In some embodiments, the overlying film 153 may have an etching rate different from that of the underlying film 154 to create the substantially void-free bottom portion 132 of the re-routing layer 130. In some embodiments, the underlying film 155 includes oxide, such as silicon oxide.

[0035] In some embodiments, thicknesses of the overlying film 153 and the underlying film 155 may be modulated to terminate a dangling bond of silicon atoms at the interface of the substrate 100 and the underlying film 154 including silicon. In detail, dangling bonds of silicon atoms at the interface of the underlying film 154 of silicon oxide and the substrate 100 of silicon interface are bonded with and terminated by hydrogen atoms introduced in the overlying film 152 of silicon nitride. In some embodiments, the re-routing layer 130 and the bonding dielectric 140 serve as a bonding layer to facilitate a bonding with another semiconductor device 10.

[0036] FIG. 2 is a cross-sectional view of a semiconductor device assembly 20 in accordance with some embodiments of the present disclosure. Referring to FIG. 2, the semiconductor device assembly 20 includes two semiconductor devices, including a first semiconductor device 10A and a second semiconductor device 10B, bonded together in a front-to-front configuration. The various layers of the first and second semiconductor devices 10A and 10B may be substantially similar to the layers of the semiconductor device 10 shown in FIG. 1, and detailed description of those layers is omitted for brevity.

[0037] In some embodiments, the second semiconductor device 10B is arranged upside down and stacked on the first semiconductor device 10A, and the second semiconductor device 10B is hybrid-bonded to the first semiconductor device 10A for making physical and electrical connection between the first semiconductor device 10A and the second semiconductor device 10B. Various processes may be used to bond the first semiconductor device 10A to the second semiconductor device 10B; in some embodiments, the processes for bonding the first semiconductor device 10A to the second semiconductor device 10B include a metal-to-metal bonding process and a dielectric-to-dielectric bonding process.

[0038] In some embodiments, the first and second semiconductor devices 10A and 10B are aligned to make a first re-routing layer 130A of the first semiconductor device 10A be in contact with a second re-routing layer 130B of the second semiconductor device 10B, and to make a bonding dielectric 140A of the first semiconductor device 10A contact the bonding dielectric 140B of the second semiconductor device 10B, wherein the second re-routing layer 130B includes substantially a same shape as the first re-routing layer 130A.

[0039] After the alignment of the first and second semiconductor devices 10A and 10B, heat and/or force are applied to bond the first re-routing layer 130A to the second re-routing layer 130B and to cure the first bonding dielectric 140A to the second bonding dielectric 140B, thereby forming the semiconductor device assembly 20.

[0040] FIG. 3 is a flow diagram illustrating a method 300 of manufacturing a semiconductor device 100 in accordance with some embodiments of the present disclosure. FIGS. 4 to 12 are schematic diagrams illustrating various fabrication stages constructed according to the method 300 for manufacturing the semiconductor device 100 in accordance with some embodiments of the present disclosure. The stages shown in FIGS. 4 to 12 are also illustrated schematically in the flow diagram in FIG. 3. In the subsequent discussion, the fabrication stages shown in FIGS. 4 to 12 are discussed in reference to the process steps shown in FIG. 3.

[0041] Referring to FIG. 4, one or more semiconductor components 110 and an interconnect layer 120 are provided according to a step 302 in FIG. 3. The semiconductor components 110 may be formed in a semiconductor substrate 100 including silicon. In some embodiments, the semiconductor components 110 are formed using various processes including deposition, etching, implantation, photolithography, annealing, and/or other suitable processes. Moreover, the semiconductor components 110 may interconnect with one another (through the interconnect layer 120) to form, for example, a logic device, a memory device, an input/output device, a system-on-chip device, another suitable type of device, or a combination thereof. In some embodiments, the semiconductor components 110 may be formed in the semiconductor substrate 100 during front-end-of-line (FEOL) processes.

[0042] The interconnect layer 120, formed on the semiconductor component 110 and electrically coupled to the semiconductor component 110, includes alternatingly stacked metallic pads M1, M2, M3 and vias V1, V2, V3 embedded in dielectric materials ILD1, ILD2, ILD3. In such embodiment, the vias V1 contact the semiconductor components 110, and the metallic pads M3 farthest from the semiconductor components 110 are exposed through the dielectric material ILD3. In some embodiments, the metallic pads M1, M2, M3 may include aluminum or aluminum alloys. In some embodiments, the dielectric materials ILD1, ILD2, ILD3 include the same material or different materials. The dielectric materials ILD1, ILD2, ILD3 may include silicon oxide, silicon nitride, oxynitride, borosilicate glass (BSG), low-k material, another suitable material or a combination thereof. In some embodiments, the metallic pads M1, M2, M3 may be formed using plating process, the vias V1, V2, V3 may be formed using CVD processes, and the dielectric materials ILD1, ILD2, ILD3 may be formed using vapor deposition processes.

[0043] Referring to FIG. 5, in some embodiments, an insulating layer 150 is deposited on the interconnect layer 120 according to a step 304 in FIG. 3. In some embodiments, the deposition of the insulating layer 150 may include depositing a blanket underlying film 154, contacting the metallic pads M3 and the dielectric material ILD3 of the interconnect layer 120 farthest from the substrate 100, and depositing a blanket overlying film 152 on the blanket underlying film 154. In some embodiments, after the deposition of the blanket overlying film 152, a planarization process may be performed to provide the blanket overlying film 152 with a substantially planar top surface 156. In some embodiments, the blanket underlying film 154 and the blanket overlying film 152 are deposited by a low-pressure chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. In alternative embodiments, the blanket underlying film 154 and the blanket overlying film 152 may be formed using vapor deposition processes. In some embodiments, the blanket underlying film 154 includes oxide, such as silicon dioxide. The blanket overlying film 152 may include nitride, such as silicon nitride, to provide the semiconductor device 100 with a uniform dangling bond configuration.

[0044] Referring to FIG. 6, in some embodiments, a first opening 210 is formed to expose the interconnect layer 120 according to a step 306 in FIG. 3. In some embodiments, the first opening 210 is formed by coating a first etching mask 220 on the blanket overlying film 152 shown in FIG. 5 and performing a first etching process to remove portions of the blanket overlying film 152 and the blanket underlying film 154 not protected by the first etching mask 220; accordingly, one or more portions of the metallic pads M3 are exposed through the first opening 210. In some embodiments, the first etching mask 220 is formed by performing an exposure process and a develop process on a first photoresist material fully covering the blanket overlying film 152. In some embodiments, the insulating layer 150 is etched to form a remaining insulating layer 151 using a dry etching process, an anisotropic wet etching process, or any other suitable anisotropic process, and the first etching process may utilize multiple etchants to etch the blanket overlying film 152 and the blanket underlying film 154, wherein the etchants are selected based on the materials being etched.

[0045] As shown in FIG. 6, the remaining insulating layer 151, including an overlying film 153 over the interconnect layer 120 and an underlying film 155 between the interconnect layer 120 and the overlying film 153, has sidewalls 157 exposed through the first opening 210. In some embodiments, an included angle θ between the sidewalls 157 and the interconnect layer 120 is greater than 90 degrees to create a void-free re-routing layer to be subsequently formed in the first opening 210. The first etching mask 220 is then removed, for example, by an ashing process or a wet strip process, wherein the wet strip process may chemically alter the first etching mask 220 so that it no longer adheres to the overlying layer 153.

[0046] Referring to FIG. 7, after the first photoresist pattern 220 has been removed, a bonding dielectric 140 is deposited on a top surface 158 of the insulating layer 151 and in the first opening 210 according to a step 308 in FIG. 3. In some embodiments, the bonding dielectric 140 fills up the first opening 210. In some embodiments, after the deposition, the bonding dielectric 140 above the insulating layer 150 has an original thickness T3 of 5.5 μm.

[0047] Referring to FIG. 8, the bonding dielectric 140 is planarized according to a step 310 in FIG. 3. In some embodiments, the bonding dielectric 140 is thinned to a thickness T1 of 3 μm. In some embodiments, after the planarization process, the bonding dielectric 140 has a substantially planar top surface 142. In some embodiments, the bonding dielectric 140 is planarized using a chemical mechanical polishing (CMP) process, for example. Following this, a second etching mask 230 is formed and patterned on the bonding dielectric 140.

[0048] Referring to FIG. 9, in some embodiments, a second etching process is performed to remove regions of the bonding dielectric 140 according to a step 312 in FIG. 3. In some embodiments, the regions of the bonding dielectric 140 exposed through the second etching mask 230 are removed after the second etching process. The removal of the regions of the bonding dielectric 140 creates a second opening 240 in the bonding dielectric 140 and recreates the first opening 220 which, in turn, again exposes the portions of the metallic pads M3 and portions of the top surface 158 of the remaining insulating layer 151. The second opening 240 communicates with the first opening 220. The second etching mask 230 is then removed.

[0049] Referring to FIG. 10, in some embodiments, a diffusion barrier layer 160 is deposited on the top surface 142 of the bonding dielectric 140, on sidewalls 144 of the bonding dielectric 140, on the top surface 158 of the insulating layer 151, and on sidewalls 157 of the insulating layer 151 according to a step 314 in FIG. 3. In some embodiments, the diffusion barrier layer 160 is also deposited on the metallic pads M3 and the insulating material ILD3 of the interconnect layer 120. In some embodiments, the diffusion barrier layer 160, having a substantially uniform thickness, is formed using a physical vapor deposition (PVD) process, for example.

[0050] Referring to FIG. 11, in some embodiments, a conductive material 250 is deposited on the diffusion barrier layer 160 (and the metallic pads M3) according to a step 314 in FIG. 3. In some embodiments, the conductive material 250, which includes copper or copper alloys, not only fills up the first opening 220 and the second opening 240 but also covers the top surface 142 of the bonding dielectric 140. In some embodiments, the conductive material 250 is formed using a plating process.

[0051] Referring to FIG. 12, in some embodiments, a polishing process is performed to remove the conductive material 250 and the diffusion barrier layer 160 from the top surface 142 of the bonding dielectric 140, thereby forming a re-routing layer 130. Accordingly, the semiconductor device 100 is completely formed.

[0052] One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor component, a re-routing layer, a bonding dielectric and an insulating layer. The re-routing layer is disposed over the semiconductor component and electrically coupled to the semiconductor component. The bonding dielectric is disposed over the semiconductor component to surround a top portion of the re-routing layer. The insulating layer is disposed between the semiconductor component and the bonding dielectric to surround a bottom portion of the re-routing layer.

[0053] One aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.

[0054] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.

[0055] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods and steps.