INSULATED TRENCH GATES WITH DOPANTS IMPLANTED THROUGH GATE OXIDE

Abstract

In an insulated trench gate device, polysilicon in the trench is etched below the top surface of the trench, leaving a thin gate oxide layer exposed near the top of the trench. An angled implant is conducted that implants dopants through the exposed gate oxide and into the side of the trench. If the implanted dopants are n-type, this technique may be used to extend an n+ source region to be below the top of the polysilicon in the trench. If the implanted dopants are p-type, the dopants may be used to form a p-MOS device that turns on when the polysilicon is biased with a negative voltage. P-MOS and n-MOS devices can be formed in a single cell using this technique, where turning on the n-MOS device turns on a vertical power switch, and turning on the p-MOS device turns off the power switch.

Claims

1. A method of forming an insulated trench gate device comprising: forming trenches in a semiconductor material of a first conductivity type; oxidizing sidewalls of the trenches to form a gate oxide along the sidewalls; partially filling the trenches with a conductor such that the gate oxide is exposed on the sidewalls of the trenches above the conductor; forming a layer of a second conductivity type above the semiconductor material of the first conductivity type, such that a side of the layer of the second conductivity type abuts the gate oxide along the sidewalls; and implanting dopants of at least one of the first conductivity type or the second conductivity type through the exposed gate oxide and at least into the layer of the second conductivity type.

2. The method of claim 1 wherein the implanting dopants comprises implanting the dopants at an angle with respect to the sidewalls of the trenches.

3. The method of claim 1 wherein the layer of the second conductivity type forms a source region, wherein the step of implanting the dopants comprises implanting dopants of the second conductivity type into the source region and below the source region to form a downward extension of the source region.

4. The method of claim 3 wherein a top of the conductor in the trenches is below a bottom of the source region, and the extension extends below the top of the conductor along the trenches.

5. The method of claim 1 wherein the step of implanting the dopants comprises implanting dopants of the first conductivity type into the layer of the second conductivity type, wherein the dopants of the first conductivity type form a first conductivity region along the sidewalls of the trenches within the layer of the second conductivity type.

6. The method of claim 5 wherein the layer of the second conductivity type forms a source region that extends below a top surface of the conductor, wherein the implanting the dopants forms a first conductivity region extending below the top surface of the conductor, and the source region extends below the first conductivity region.

7. The method of claim 1 wherein the layer of the second conductivity type forms a source region; wherein the step of implanting the dopants comprises implanting dopants of the second conductivity type into the source region and below the source region to form a downward extension of the source region; and further comprising: implanting dopants of the first conductivity type through the exposed gate oxide to form a first conductivity region that extends below the downward extension and below a top of the conductor.

8. The method of claim 1 wherein the implanting dopants further comprises implanting the dopants of the first conductivity type into the semiconductor material of the first conductivity type.

9. The method of claim 1 wherein the implanting dopants comprises implanting the dopants of the first conductivity type into the layer of the second conductivity type.

10. The method of claim 1 wherein the implanting dopants comprises implanting n-type dopants to form a vertical n-channel MOS device.

11. The method of claim 1 wherein the implanting dopants comprises implanting p-type dopants to form a vertical p-channel MOS device.

12. The method of claim 1 wherein the layer of the second conductivity type forms a body region; wherein the implanting the dopants forms a first conductivity region in the body region along the sidewalls of the trenches, such that a portion of the body region is below the first conductivity region and adjacent to the conductor in the trenches, wherein the semiconductor material of the first conductivity type, the body region, the conductor in the trenches, and the first conductivity region form a p-channel MOS device; and the method further comprising: applying a negative voltage to the conductor, relative to the first conductivity region voltage, to invert the body region adjacent to the conductor to turn on the p-channel MOS device.

13. (canceled)

14. The method of claim 1 wherein the trenches are part of cells in the insulated trench gate device, where an individual cell includes both a p-channel MOS device and an n-channel MOS device, wherein the p-channel MOS device turns on with a negative conductor voltage below a negative threshold voltage, and the n-channel MOS device turns on with a positive conductor voltage above a positive threshold voltage.

15. The method of claim 14 wherein the n-channel MOS device, when turned on, turns on the insulated trench gate device, and the p-channel MOS device, when turned on, turns off the insulated trench gate device.

16. The method of claim 1 wherein the insulated trench gate device comprises a vertical MOS switch.

17. An insulated trench gate device comprising: trenches in a semiconductor material; a gate oxide along sidewalls of the trenches; a conductor partially filling the trenches, such that the gate oxide is exposed on the sidewalls of the trenches above the conductor; a source region; and dopants of a first conductivity type implanted through the exposed gate oxide and at least into the source region.

18. The device of claim 17 wherein the source region is of the first conductivity type in a top surface of the semiconductor material, the source region having a first dopant concentration, wherein the dopants of the first conductivity type form a downward extension of the source region having a second concentration lower than the first concentration.

19. The device of claim 17 wherein the source region is of a second conductivity type in a top surface of the semiconductor material, wherein the dopants of the first conductivity type form a first conductivity region in the source region along the sidewalls of the trenches.

20. The device of claim 19 wherein the source region extends below a top surface of the conductor, wherein the implanting the dopants forms a first conductivity region extending below the top surface of the conductor, and the source region extends below the first conductivity region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG. 1 is copied from Applicant's U.S. Pat. No. 9,391,184 and is a cross-section of a vertical power device having trench gates connected in parallel. This device is referred to by Applicant as a Generation 1 device and uses n-MOS turn on devices in the cells.

[0036] FIG. 2 is also copied from Applicant's U.S. Pat. No. 9,391,184 and includes p-MOS turn off devices in the same cell as the n-MOS turn on devices. This device is referred to by Applicant as a Generation 2 device.

[0037] FIG. 3 is a cross-section of a trench in a silicon wafer filled with doped polysilicon, where the polysilicon also covers the top of the silicon wafer.

[0038] FIG. 4 illustrates an example of the polysilicon being blanket etched to remove the polysilicon from the wafer surface, where the polysilicon fills the trench to the level of the silicon substrate.

[0039] FIG. 5 illustrates an example of the polysilicon being blanket etched to remove the polysilicon from the wafer surface, where the polysilicon is etched well below the top of the trench to ensure no polysilicon remains on the surface of the wafer.

[0040] FIG. 6 illustrates the device of FIG. 5 where an n+ source is formed relatively deep into the silicon so that it extends down below the polysilicon in the trench to form an n-MOS device.

[0041] FIG. 7 illustrates the device of FIG. 5 where a relatively shallow n+ source is formed in the silicon so that it does not extend down below the polysilicon in the trench. In this case, no n-MOS is formed and the device does not work.

[0042] FIG. 8 illustrates the device of FIG. 7 where an angled implant of n-type dopants is performed through the gate oxide to extend the edges of the n+ source region down to the polysilicon in the trench, which then forms an n-MOS device. The implanted dopants are later diffused (e.g., by heat) to go below the top of the polysilicon.

[0043] FIG. 9 is a dopant profile of the device of FIG. 8 in the silicon along the outside of the trench, showing the two different n-type dopant concentrations of the top n+ source region and the n-type extension adjacent to the polysilicon in the trench.

[0044] FIG. 10 illustrates the use of a p-type implant through the gate oxide to control the threshold voltage of the n-MOS device.

[0045] FIG. 11 is a dopant profile of the device of FIG. 10 along the outside of the trench.

[0046] FIG. 12 illustrates how a p-type dopant (e.g., boron) can be angle-implanted through the gate oxide to form a p-MOS device, after the implanted dopants are diffused to extend below the polysilicon. The n-type source region adjacent to the polysilicon forms a channel in the p-MOS device.

[0047] FIG. 13 illustrates the device of FIG. 12 with an extra angled implantation of p-type dopants to either control the threshold voltage of the p-MOS device if the p-type dopant is deep enough, or to cause the p-region to extend completely down to the p-well to create a weak connection between the p-well and the cathode electrode to improving tolerance to transients.

[0048] FIG. 14 illustrates how angled n-type implants and angled p-type implants can be performed in different cells to form n-MOS and p-MOS devices for Generation 1 and Generation 2 devices, or for other applications.

[0049] FIG. 15 illustrates the difference between conventional n-MOS devices (on the left side), formed using a deep n+ source, and the combination of n-MOS and p-MOS devices for a Generation 2 device (or other application).

[0050] Elements that are the same or equivalent in the various figures may be labeled with the same numeral.

DETAILED DESCRIPTION

[0051] Although the techniques of the present invention can be used for various applications, a few examples will be given with reference to Applicant's Generation 1 and Generation 2 devices. The general invention is an angled implant through gate oxide lining a trench, where doped polysilicon (or another conductor) in the trench exposes a portion of the gate oxide on the trench sidewall near the top of the trench. Depending on the conductivity and depth of the angled implant, p-MOS and/or n-MOS devices can be formed, threshold voltages can be adjusted, weak connections to p-wells can be performed, and other structures can be achieved.

[0052] In FIG. 7, the doped polysilicon 64, or other conductor, such as a metal silicide or a metal, is etched down below the top of the trench 60 to expose a portion of the gate oxide 62 on the sidewall of the trench 60.

[0053] Prior to formation of the trenches 60 or after the formation of the trenches 60, n-type dopants are implanted in the top of the silicon wafer to form shallow n+ source regions 68. Since the n+ source regions 68 are too shallow and are not adjacent to the polysilicon, no inversion occurs when the gate is positively biased, and no n-MOS device is formed. Shallow n+ sources have advantages, such as providing a higher breakdown voltage compared to deeper n+ sources.

[0054] In FIG. 8, an angled implant 70 is performed to inject n-type dopants (e.g., phosphorous) through the thin gate oxide 62 and into the silicon. The polysilicon 64 acts as a mask so the implant is self-aligned. The optimal implant energy and dosage depends on the application, and one skilled in the art would know the optimal implant energy and dosage from simulations or testing. The resulting n-type extension 72 (after diffusion and activation of the implanted atoms) extends below the polysilicon 64 to effectively extend the n+ source regions 68 to be below the top of the polysilicon 64 to form an n-MOS device. Thus, when the gate is sufficiently positively biased, an inversion forms along the trench 60 to turn on the Generation 1 device. The advantages of the shallow n+ source regions 68 remain.

[0055] In an alternative embodiment, if the device to be formed is a simple vertical MOSFET, the layer 73 below the dashed line 74 would be n-type so the inversion along the trench 60 forms a vertical n-channel between the n-type extension 72 and the lower n-type layer 73 to conduct current between the two n-type materials.

[0056] The angled implant invention applies to many types of trench gate devices, where the devices can be the Generation 1 or 2 devices, or vertical MOSFETs, or IGBTs, or thyristors, or other suitable devices.

[0057] FIG. 9 is a doping profile along the trench sidewall of FIG. 8 showing the shallow n+ source region 68, the n-type extension 72, and the p-well 14. Note that the dopant concentration of the n-type extension 72 is less than that of the n+ source region 68, since the n-type extension 72 only has to ensure that the gate forms an inversion along the trench 60 to initiated full turn-on of the Generation 1 or 2 device. If the device is a vertical MOSFET, where an n-layer (e.g., layer 73 in FIG. 8) is formed near the bottom of the trench 60, the n-type extension 72 may have a higher concentration to improve conductivity.

[0058] In FIG. 10, an angled implant 75 of a p-dopant (e.g., boron) is made through the exposed gate oxide 62 to form a p-type region 76 between the p-well 14 and the n-type extension 72 to adjust a threshold voltage of the n-MOS device. A higher dopant concentration in the p-type region 76 raises the threshold voltage. The implant energy of the p-dopants may be higher than the implant energy used to form the n-type extension 72.

[0059] FIG. 11 is a doping profile along the trench 60 in FIG. 10, similar to FIG. 9 but showing the additional p-type region 76.

[0060] FIG. 12 shows the device of FIG. 6 but with a p+ source region 78 formed using the angled implant 80. With the p+ source region 78 extending down to below the polysilicon 64 (after diffusion), a p-MOS device is formed where the n source 82 acts as either an n source for an n-MOS device or an n-channel for a p-MOS device.

[0061] FIG. 13 shows the device of FIG. 12 but with an extra p-type angled implant 84 to form a p-type extension 86 to effectively extend the p+ source region 78 to below the top of the polysilicon 64, with the n source region 82 still abutting the trench 60 below the p-type extension 86. The p-type extension 86 would not be needed if the p+ source region 78 extended below the polysilicon 64. This p-type extension 86 can be used to control a threshold voltage of the p-MOS device. The p-type extension 86 can have a concentration less than that of the p+ source region 78.

[0062] When the gate is sufficiently positive, the p-well 14 surrounding the trench 60 inverts to effectively reduce the base width of the vertical npn transistor (an n-type layer is below the p-well 14) to turn the power device of FIG. 2 on. This constitutes the n-MOS action. To turn off the power device of FIG. 2, the gate is biased sufficiently negative, and the p-MOS device turns on to effectively connect the p-well 14 to the cathode electrode 20 (FIG. 2) to rapidly turn off the vertical npn transistor and remove carriers from the p-well 14 to more rapidly turn off the power device.

[0063] If the p-type extension 86 were deeper and reached down into the p-well 14, a weak short would be created between the cathode electrode 20 (FIG. 2) and the p-well 14. This dopant profile improves the tolerance to transients that could undesirably turn on the power device. This structure would replace the opening 16 in FIGS. 1 and 2 for weakly connecting the p-well 14 to the cathode electrode 20 at certain locations on the die.

[0064] FIG. 14 compares cells in the Generation 1 device 90 to the Generation 2 device 92. The

[0065] Generation 1 n-MOS cells have doped polysilicon 64 that is etched below the top of the trench 60. The shallow n+ source regions 68 do not extend down to the polysilicon 64. An angled implant through the exposed gate oxide 62 forms n-type extensions 72 so that the n-source extends below the polysilicon 64. The extensions 72 can have an n-type dopant concentration that is the same as or less than the n+ source region 68 concentration. The trenches 60 may be on the order of 5-10 microns deep, and the distance from the top of the silicon wafer to the polysilicon 64 may be 1-3 microns. The n+ source regions 68 or the extensions 72 should be at least 1 micron below the polysilicon 64 to ensure good overlap.

[0066] If an n-layer existed below the p-well 14 and above the bottom of the trench 60, a vertical MOSFET would be formed, as described with respect to FIG. 8.

[0067] The Generation 2 device 92 has the n-type source regions 82 extending below the polysilicon 64 to form n-MOS devices in the cells. The dopant concentration of the n-type source regions 82 tapers down with depth. Additionally, p+ source regions 78 are implanted through the top surface of the silicon wafer, and p-type extensions 86 are angle-implanted through the exposed gate oxide 62 to effectively extend the p-type sources to slightly below the top of the polysilicon 64 and above the bottom of the n-type source regions 82 to form p-MOS devices. A positive gate voltage inverts the p-well 14 surrounding the gate to turn on the n-MOS device, and a negative gate voltage inverts the n-type source region 82 adjacent to the gate. The concentration of n-type dopants adjacent to the gate may be fairly low to easily invert with a small negative gate voltage. Therefore, the turn-on and turn-off gate voltages can be adjusted. An angled n-type dopant implant may also be performed to adjust the turn-off voltage.

[0068] FIG. 15 is similar to FIG. 14 except that the n-type source regions 66 extend below the polysilicon 64, so no n-type extensions are needed.

[0069] The various concepts described can be applied to any type of trench-gate device to control various characteristics of the device and to ensure the source regions extend below the polysilicon (or other conductor) in the trenches.

[0070] Various features disclosed may be combined to achieve a desired result.

[0071] While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.