A transistor includes a wide bandgap semiconductor layer, a gate electrode, a gate pad, and a gate runner. The gate electrode extends to a region where the gate pad is located and a region where the gate runner is located. The gate pad is connected to the gate electrode. The gate runner is connected to the gate electrode. The gate electrode includes a first region connected to the gate pad, a second region connected to the gate runner, and a third region and a fourth region arranged between the first and second regions in different positions in a first direction. In a cross section perpendicular to the first direction, the gate electrode in the fourth region has a cross-sectional area smaller than that of the gate electrode in the third region.

A multi-trench super junction IGBT device includes a metallization collector, a P-type substrate, a first N-type epitaxial layer located above the P-type substrate and a second N-type epitaxial layer located above the first N-type epitaxial layer. The second N-type epitaxial layer includes at least a first dummy MOS cell unit and a MOS cell unit, wherein the first dummy MOS cell unit includes a trench formed by reactive ion etching, a thermally grown gate oxide layer provided inside the trench and deposited heavily doped polysilicon located in the gate oxide layer.

According to an aspect of the present disclosure, a semiconductor device includes a substrate including an IGBT region, and a diode region, a surface electrode provided on a top surface of the substrate and a back surface electrode provided on a back surface on an opposite side to the top surface of the substrate, wherein the diode region includes a first portion formed to be thinner than the IGBT region by the top surface of the substrate being recessed, and a second portion provided on one side of the first portion and thicker than the first portion.

A power semiconductor device includes an active cell region with a drift region of a first conductivity type, a plurality of IGBT cells arranged within the active cell region, each of the IGBT cells includes at least one trench that extends into the drift, an edge termination region surrounding the active cell region, a transition region arranged between the active cell region and the edge termination region, at least some of the IGBT cells are arranged within or extend into the transition region, a barrier region of a second conductivity type, the barrier region is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells and does not extend into the transition region, and a first load terminal and a second load terminal, the power semiconductor device is configured to conduct a load current along a vertical direction between.

Disclosed is a transistor device which includes a semiconductor body having a first surface, a source region, a drift region, a body region being arranged between the source region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric, wherein the field electrode comprises a first layer and a second layer, wherein the first layer has a lower electrical resistance than the second layer, wherein a portion of the second layer is disposed above and directly contacts a portion of the first layer.

The object is to provide a semiconductor device that prevents a snapback operation and has excellent heat dissipation. The semiconductor device includes a semiconductor substrate, transistor portions, diode portions, a surface electrode, and external wiring. The transistor portions and the diode portions are provided in the semiconductor substrate and are arranged in one direction parallel with the surface of the semiconductor substrate. A bonding portion of the external wiring is connected to the surface electrode. The transistor portions and the diode portions are provided in a first region and a second region and alternately arranged in the one direction. A first transistor width and a first diode width in the first region are smaller than a width of the bonding portion. A second transistor width and a second diode width in the second region are larger than the width of the bonding portion.

The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.

Provided is a semiconductor apparatus, wherein a doping concentration distribution in the buffer region has a deepest slope where a doping concentration monotonically decreases to a position where it comes in contact with the drift region in a direction from the lower surface of the semiconductor substrate toward an upper surface, a hydrogen chemical concentration distribution in the buffer region includes in a first depth range provided with the slope: a first decrease portion where a hydrogen chemical concentration decreases toward the upper surface side; a second decrease portion located closer to the upper surface side than the first decrease portion is and where the chemical concentration decreases; and an intermediate portion arranged between the first and second decrease portions, and the intermediate portion has: a flat portion where the distribution is uniform; a peak in a slope of the chemical concentration; or a kink portion of the chemical concentration.

In a semiconductor device, a semiconductor substrate has an IGBT region and a FWD, and includes a first conductivity type drift layer, a second conductivity type base layer disposed on the drift layer, a second conductivity type collector layer disposed opposite to the base layer with respect to the drift layer in the IGBT region, and a first conductivity type cathode layer disposed opposite to the base layer with respect to the drift layer in the FWD region. The collector layer includes an extension portion that covers only a part of the cathode layer on a side adjacent to the drift layer. Alternatively, the collector layer includes an extension portion that entirely covers a region of the cathode layer adjacent to the drift layer, and has an area density of 3.5×10.sup.12 cm.sup.−2 or less.

Provided is a semiconductor device including: a buffer region having a doping concentration higher than a bulk donor concentration; a first low-concentration hydrogen peak in the buffer region; a second low-concentration hydrogen peak in the buffer region closer to a lower surface than the first low-concentration hydrogen peak; a high-concentration hydrogen peak in the buffer region closer to the lower surface than the second low-concentration hydrogen peak, the high-concentration hydrogen peak having a hydrogen chemical concentration higher than that of the second low-concentration hydrogen peak; and a flat region including a region between the two low-concentration hydrogen peaks and a region including the second low-concentration hydrogen peak, and having a doping concentration higher than a bulk donor concentration, an average value of the doping concentration being equal to or smaller than a local minimum value of a doping concentration between the second low-concentration hydrogen peak and the high-concentration hydrogen peak.