Concatenated two-wire data bus

Abstract

Disclosed is a light module and a matching housing for a bus node. The light module is provided to be used in a data bus system for transmitting data for light-emitting components via a differential two-wire data bus. The data bus transmits data between a bus master and at least two bus nodes. The data bus is divided by the bus nodes into at least two two-wire data bus sections. The housing comprises at least two rows of connections arranged opposite each other. Each row comprises one negative supply voltage connection and one positive supply voltage connection, which are arranged to be connected in pairs without intersection. The two connections for each of the respective two-wire data bus sections are arranged between the connections for the supply voltages in each row. A light-emitting component is arranged in a recess of the housing.

Claims

1. A method for initializing a differential two-wire data bus between a bus master, and at least two bus nodes, the at least two bus nodes including one or more terminal bus nodes, wherein the two-wire data bus: comprises a first one-wire data bus and a second one-wire data bus; and is divided by the at least two bus nodes into at least two two-wire data bus sections, each of the at least two two-wire bus sections including a respective first one-wire data bus section and a respective second one-wire data bus section; and wherein each of the two-wire data bus sections is terminated by a respective terminal bus node; the method comprising: determining a new bus node address by the bus master; storing the bus node address in a bus node address register of a bus node of interest, the bus node of interest being one of the at least two bus nodes, by the bus master, wherein the bus master and the bus node of interest are connected by one or more of the at least two two-wire data bus sections, and the bus node address register is one of: a data register of a modified JTAG interface of the bus node of interest, or a part of the data register of the modified JTAG interface of the bus node of interest, or a part of an instruction register of the modified JTAG interface of the bus node of interest, wherein the modified JTAG interface comprises a JTAG test controller comprising a state diagram corresponding to IEEE 1149 standard or a substandard of the IEEE 1149 standard; and connecting one or more of the at least two two-wire data bus sections with one or more other of the at least two two-wire data bus sections by closing a transfer gate of the bus node of interest, whereby a further storage of a further bus node address in the bus node address register of the bus node of interest is prevented by the bus node of interest for as long as the transfer gate is closed.

2. The method according to claim 1, further comprising: storing an instruction to open the transfer gate in the instruction register or a transfer gate control register of the modified JTAG interface of the bus node of interest.

3. The method according to claim 1, further comprising: verifying a correct addressing of at least one of the at least two bus nodes by cyclic writing and reading a bypass register.

4. The method according to claim 3, comprising: determining a number of correctly addressable bus modes by the bus master; comparing the number of correctly addressable bus nodes to a set number; and triggering, by the bus master or a connected system, at least one signal or one measure as a function of the number of correctly addressable bus nodes.

5. A method for transmitting data after the initialization of the differential two-wire data bus according to claim 1, comprising: simultaneously transmitting a transmission address to all accessible bus nodes by writing transmission registers of each of the respective accessible bus nodes by the bus master having the transmission address, wherein the transmission register of each of the respective accessible bus nodes is the data register or a second part of the data register or a second part of the instruction register of the modified JTAG interface of the respective accessible bus node, and wherein the bus node address register is not respectively the second part of the data register or the second part of the instruction register of the respective accessible bus node; comparing the transmission address in the transmission register in each of the respective accessible bus nodes to the bus node address in the bus node address register in the respective accessible bus node using a predetermined comparison algorithm; activating a transmitting capability for the respective accessible bus node at times provided for that purpose, if the predetermined comparison algorithm of the comparison performed by the respective accessible bus node results in a level of congruence of the bus node address stored in the bus node address register of the respective accessible bus node and the transmission address stored in the transmission register of the respective accessible bus node expected for a transmission permission; and deactivating the transmitting capability for the respective accessible bus node, if the comparison algorithm of the comparison performed before by the respective bus node does not result in the level of congruence of the bus node address stored in the bus node address register of the respective accessible bus node and the transmission address stored in the transmission register of the respective accessible bus node expected for the transmission permission.

6. A method for transmitting data after the initialization of the differential two-wire data bus according to claim 1, comprising: simultaneously transmitting a transmission address to all accessible bus nodes by writing transmission registers of each of the respective accessible bus nodes by the bus master having the transmission address, wherein the transmission register of each of the respective accessible bus nodes is the data register or a second part of the data register or a second part of the instruction register of the modified JTAG interface of the respective accessible bus node, and wherein the bus node address register is not respectively the second part of the data register or the second part of the instruction register of the respective accessible bus node; comparing the transmission address in the transmission register in each of the respective accessible bus nodes to the bus node address in the bus node address register in the respective accessible bus node using a predetermined comparison algorithm; activating a receiving capability of the respective accessible bus node for a content of predetermined data registers of the respective accessible bus node, if the predetermined comparison algorithm of the comparison performed before by the respective accessible bus node results in a level of congruence of the bus node address stored in the bus node address register of the respective accessible bus node and the transmission address stored in the transmission register of the respective accessible bus node, expected for a transmission permission; and deactivating the receiving capability of the respective accessible bus node for the content of predetermined data registers of the respective bus node, if the comparison algorithm of the comparison performed before by the respective bus node does not result in the level of congruence of the bus node address stored in the bus node address register of the respective accessible bus node and the transmission address stored in the transmission register of the respective accessible bus node, expected for the transmission permission.

7. A method for transmitting data after the initialization of the differential two-wire data bus according to claim 1, comprising: simultaneously transmitting a transmission address to all accessible bus nodes by writing transmission registers of each of the respective accessible bus nodes by the bus master having the transmission address, wherein the transmission register of each of the respective accessible bus nodes is a data register or a second part of the data register or a second part of the instruction register of the modified JTAG interface of the respective accessible bus node, and wherein the bus node address register is not respectively the second part of the data register or the second part of the instruction register of the respective accessible bus node; comparing the transmission address in the transmission register in each of the respective accessible bus nodes to the bus node address in the bus node address register in the respective accessible bus node using a predetermined comparison algorithm; activating a receiving capability of the respective accessible bus node for a content of predetermined contents of the instruction register of the respective accessible bus node to allow predetermined instructions for an instruction decoder of the modified JTAG interface of the respective accessible bus node, if the predetermined comparison algorithm of the comparison performed before by the respective accessible bus node results in a level of congruence of the bus node address stored in the bus node address register of the respective accessible bus node and the transmission address stored in the transmission register of the respective accessible bus node, expected for a transmission permission; and deactivating the receiving capability of the respective accessible bus node for the content of the predetermined contents of the instruction register of the respective accessible bus node for suppressing the predetermined instructions for the instruction decoder of the modified JTAG interface of the respective accessible bus node, if the predetermined comparison algorithm of the comparison performed before by the respective accessible bus node does not result in the level of congruence of the bus node address stored in the bus node address register of the respective accessible bus node and the transmission address stored in the transmission register of the respective accessible bus node expected for the transmission permission.

Description

DESCRIPTION OF THE FIGURES

(1) The disclosure will be explained in more detail hereunder with reference to various examples and to the drawings.

(2) FIG. 1 shows a state diagram of a test controller according to the IRRR 1149 standard. FIG. 1 has been explained in the introduction.

(3) FIG. 2 shows the basic signal shapes of a JTAG data protocol of the prior art.

(4) FIG. 3 shows the basic signal shapes of the suggested data protocol on the two-wire data bus (b1b2b3) or a connected two-wire data bus section (b1, b2, b3) of the two-wire data bus (b1b2b3).

(5) FIG. 4 shows examples of level sequences for a respective time slot package of a duration T with three successive time slots.

(6) FIG. 5 is an exemplary illustration of the extraction of the data in the respective bus node (BSn) for three successive time slots.

(7) FIG. 6 schematically shows an exemplary two-wire data bus system.

(8) FIG. 7 shows a detail of the exemplary two-wire data bus system: the connection of two successive bus nodes.

(9) FIG. 8 is a schematic simplified illustration of an exemplary implementation of a bus master/two-wire data bus interface.

(10) FIG. 9 is a schematic simplified illustration of an exemplary implementation of a bus node/two-wire data bus interface.

(11) FIG. 10 is a simplified illustration of a JTAG interface of the present disclosure with illumination register (ILR).

(12) FIG. 11 is a simplified illustration of a JTAG interface of the present disclosure with illumination register (ILR) and separate switchable serial data input for the illumination register.

(13) FIG. 12 is a schematic illustration of an exemplary two-wire data bus system with separate serial data bus for illumination data.

(14) FIG. 13 is a simplified illustration of a JTAG interface of the present disclosure with illumination register (ILR) and transfer gate control register (TGCR).

(15) FIG. 14 is a schematic illustration of an exemplary two-wire data bus system, wherein each bus node has a bus master interface for controlling a succeeding bus node.

(16) FIG. 15 is a simplified illustration of a JTAG interface of the present disclosure with illumination register (ILR) and bus master control register (OWMCR).

(17) FIG. 16 shows a particularly advantageous arrangement of the connectors for a device of the present disclosure.

(18) FIG. 17 shows a particularly well-suited housing (GH) for use with the data bus system described herein.

(19) FIG. 18 shows two light modules for assembly across a surface as an area light.

(20) FIG. 19 shows a plurality of light modules of FIG. 18, assembled for an area light.

(21) FIG. 20 illustrates a two-dimensional concatenation of six light modules of FIG. 17, each with two two-wire bus master interfaces (OWM1a to OWM6a and OWM1b to OWM6b) and a two-wire data bus interface (OWS1 to OWS6).

(22) FIG. 21 is a simplified illustration of a JTAG interface of the present disclosure with illumination register (ILR), bus node address register (BKADR) and transmission register (SR).

FIG. 2

(23) FIG. 2 shows the basic signal shapes of the data protocol of the disclosure on the two-wire data bus (b1b2b3) or a connected two-wire data bus section (b1, b2, b3) of the two-wire data bus (b1b2b3). In the upper part of FIG. 2, the signal shapes of the differential levels for a two-wire test bus analogous to the IEEE 1149 standard are schematically shown. The topmost signal (TDA) shows the data signal. The second signal (TCK) shows the associated system clock (TCK). Although they refer to a differential level in this case, both signals are marked as prior art and belong to the 2-wire JTAG standard. Beneath, the digital encoding is noted as an example. It is not yet shown, whether the respective bus node (BSn) or the bus master (BM) transmits. Only the signal shape is outlined.

FIG. 3

(24) FIG. 3 illustrates a suggested signal shape in the form of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or a connected two-wire data bus section (b1, b2, b3) of the two-wire data bus (b1b2b3), which combines the clock and the data.

(25) Various differential voltage levels are outlined. Upon transmission, the differential signal (TOW) has three differential voltage level amounts:

(26) 1. a third differential voltage value level (V.sub.IO),

(27) 2. a medium second differential voltage value level (V.sub.M), and

(28) 3. a first differential voltage value level (−V.sub.IO).

(29) For the extraction of the system clock, a second threshold value (V.sub.1L) is defined in the form of a second threshold voltage value, which is between the first differential voltage value level (−V.sub.IO) and the medium second differential Voltage value level (V.sub.M).

(30) For the extraction of the data, threshold voltage value, the first threshold value (V.sub.1H), of the bus master (BM) and a third threshold voltage value, the third threshold value (V.sub.2H), of the bus nodes (BS1, BS2, BS3) are defined, which are between the third differential voltage value level (V.sub.IO) and the medium second differential voltage value level (V.sub.M) and should be about equal.

(31) A first voltage value range (V.sub.B1) is defined and delimited by the second threshold value (V.sub.2L) in the form of the second threshold voltage value of the bus nodes (BS1, BS2, BS3) and by the first differential voltage value level (−V.sub.IO).

(32) A second voltage value range (V.sub.B2) is defined and delimited by the third threshold voltage value, the third threshold value (V.sub.2H), of the bus nodes (BS1, BS2, BS3) and the first threshold voltage value of the first threshold value (V.sub.1H) of the bus master (BM) on the one hand and the second threshold voltage value of the second threshold value (V.sub.2L) of the bus nodes (BS1, BS2, BS3) on the other hand.

(33) A third voltage value range (V.sub.B3) is defined and delimited by the third threshold voltage value, the third threshold voltage (V.sub.2H) of the bus nodes (BS1, BS2, BS3) and the first threshold voltage value of the first threshold value (V.sub.1H) of the bus master (BM) on the one hand and the third differential voltage value level (V.sub.IO) on the other hand.

(34) Chronologically, the signal on the two-wire data bus (b1b2b3) or a connected two-wire data bus section (b1, b2, b3) of the two-wire data bus (b1b2b3) is divided into time slot packages with at least three time slots (TIN0, TIN1, TDO.sub.z) The time slot packages typically follow each other with a system base clock period (T). The order of the time slots in a time slot package may be optional for a system, but should preferably be the same for all time slot packages. Each system base period (T) is divided into at least three time slots, each with typically two half-clock periods (T.sub.1H, T.sub.2H) which are preferably, but not necessarily equal in length.

(35) Preferably, the system clock is respectively transmitted in one half-clock period of the at least wo half-clock periods (T.sub.1H, T.sub.2H).

(36) Here, the amount of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (b1, b2, b3) of the two-wire data bus (b1b2b3) is in the first voltage value range (V.sub.B1) in one half-clock period of the at least two half-clock periods (T.sub.1H, T.sub.2H). A first logical value of the system clock is transmitted thereby. In the example, it is sufficient that the amount of the signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (b1, b2, b3) of the two-wire data bus (b1b2b3) is below the second voltage threshold value, the second threshold value (V.sub.2L). In many applications, the first voltage value range (V.sub.B1) may be also considered as open in the downward direction.

(37) In the other half-clock period of the at least two half-clock periods (T.sub.1H, T.sub.2H), the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (b1, b2, b3) of the two-wire data bus (b1b2b3) is in the second voltage value range (V.sub.B2) or the third voltage value range (V.sub.B3). Thereby, a second logical value of the system clock is transmitted which is different from the first logical value of the system clock. In the example, it is sufficient that the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (b1, b2, b3) of the two-wire data bus (b1b2b3) is above the second voltage threshold value, the second threshold value (V.sub.2L) in the form of the second threshold value (V.sub.2L). An upward limit by the supply voltage (V.sub.bat) or another upper limit (V.sub.IO) is not relevant to the decision, whether the signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (b1, b2, b3) of the two-wire data bus (b1b2b3) is in the second voltage value range (V.sub.B2) or the third voltage value range (V.sub.B3) and is therefore not used in practice. Thus, in many applications, the third voltage value range (V.sub.B3) may also be considered as open in the upward direction.

(38) Since it is not relevant to the extraction of the system clock in this other half-clock period of the at least two half-clock periods (T.sub.1H, T.sub.2H), whether the signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (b1, b2, b3) of the two-wire data bus (b1b2b3) is in the second voltage value range (V.sub.B2) or the third voltage value range (V.sub.B3), it is now possible to transmit data by differentiating between the third voltage value range (V.sub.B3) and the second voltage value range (V.sub.B2) in this other half-clock period of the at least two half-clock periods (T.sub.1H, T.sub.2H).

(39) In this other half-clock period of the at least two half-clock periods (T.sub.1H, T.sub.2H), the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (b1, b2, b3) of the two-wire data bus (b1b2b3) is in the second voltage value range (V.sub.B2) if a first logical data value is transmitted, and is in the third voltage value range (V.sub.B3) if a second logical data value is transmitted.

(40) For the sake of understanding, exemplary logical states for the three differential states are plotted on the right next to the lower signal.

(41) In this example, the upper differential level corresponds to an exemplary logical value of the system clock (TOW) of 1 and an exemplary logical value of the data signal (TDA) of 1.

(42) In this example, the medium differential level corresponds to an exemplary logical value of the system clock (TCK) of 1 and an exemplary logical value of the data signal (TDA) of 0.

(43) In this example, the lower differential level corresponds to an exemplary logical value of the system clock (TCK) of 0.

FIG. 4

(44) FIG. 4 shows an exemplary protocol sequence of three successive time slots (TIN0, TIN1, TDO.sub.z). in other implementations of the disclosure, a time slot package may also comprise more than three time slots (TIN0, TIN1, TDO.sub.z). In the first time slot (TIN0), typically, control data are transmitted that correspond to the TMS signal of the boundary scan standard (IEEE1149). This signal typically controls the state of the finite automat according to the state diagram in FIG. 1. In the second time slot (TIN1), those data are typically transmitted that correspond to the TDI signal of the boundary scan standard (IEEE1149). In these two time slots, the bus master (BM) transmits data onto the bus node. If the bus node should also transmit in parallel, the bus node overwrites the bus master (BM) if the switchable current source (T1a, T1b) thereof is deactivated. Conversely, the bus master (BM) can overwrite the bus node if the switchable current source (T3a, T3b) of the bus node is deactivated. The bus master (BM) can detect an overwriting of the bus master (BM) by the bus node by examining, using a logic in the bus master (BM), the logical content of the transmitted data (TMS_TDI) for whether these correspond to the received data (TDo) in the respective half-clock in which the system clock (TCK) of the dominant switch (T1a, T1b) does not close. In case of such asynchronicity, the bus master (BM) can, given a suitable configuration of the state machine of the test controllers (TAPC) of the bus nodes, re-synchronize these by permanently maintaining the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected first two-wire data bus section (b1) of the two-wire data bus (b1b2b3) in the third voltage value range (V.sub.B3). For this purpose, the state machine of the test controllers (TAPC) of the bus nodes must be configured such that a permanent maintaining in the third voltage value range (V.sub.B3) causes a reset in the control field, i.e. e.g. in the first time slot (TINO), in the form of assuming a so-called “idle state” (TLR) as a waiting state of the test controllers (TAPC). This is the case with a state diagram of a JTAG controller according to the IEEE 1149 standard. This permanent maintaining of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected first two-wire data bus section (b) of the two-wire data bus (b1b2b3) in the third voltage value range (V.sub.B3) can be effected by the switchable current source (T2a, T2b) of the bus master (BM) being switched on permanently for the duration of the reset operation.

(45) FIG. 5

(46) FIG. 5 shows an exemplary sequence of differential signals according to the disclosure. The two-wire based data referenced as “2 wire data”, which are not differential, are the input. In the example, three successive time slot packages (n−1, n, n+1) are illustrated, each having e.g. three time slots (TIN0, TIN1, TDO.sub.z). Of course, it is conceivable to use more than three time slots per time slot package. The importance of the respective time slots in a time slot package only depends on the chronological position and does not change. When, in this description, reference is made to the first time slot (TIN0), the second time slot (TIN1) and the third time slot (TDO.sub.z), this is a mere denomination and does not refer to the position in a time slot package. Preferably, the chronological positioning of the individual at least three time slots (TIN0, TIN1, TDO.sub.z) in the time slot packages is always the same or can at least be predicted by means of an algorithm. The Figure further shows the associated system clock (non-differential 2-wire clock). In the time slot package n−1, the respective bus node (BSn) supplies a logical 1 in the time slot TDO.sub.Z(n−1) and, in the time slot package n, a logical 1 in the time slot TDO.sub.Z(n) and, in the time slot package n+1, a logical 0 in the time slot TDO.sub.Z(n+1). The data transmitted by the bus master (BM) in the time slots TIN0.sub.n−1, TIN1.sub.n−1, TIN0.sub.n, TIN1.sub.n, TIN0.sub.n+1, TIN1.sub.n+1 are not fixed as examples with respect to their logical content and are therefore shown hatched. The signal referenced as “TOW” is to schematically illustrate the differential potential progression of the differential signal level (TOW) on the two-wire data bus (b1b2b3 . . . b.sub.n, . . . b.sub.m) or a connected n-th two-wire data bus section (b1, b2, b3 . . . b.sub.n, . . . b.sub.m) of the two-wire data bus. From this potential progression of the potential difference on the respective two-wire data bus section (b.sub.n), e.g. the third comparator (cmp3) of the respective bus node (BSn) generates the data (TMS_TDI.sub.n). received by the respective bus node (BSn). From the differential potential progression of the differential signal level (TOW) on the respective two-wire data bus section (b.sub.n), e.g. the second comparator (cmp2) of the respective bus node (BSn) generates the clock signal (TCK.sub.n) received by the respective bus node (BSn), which clock signal corresponds to the reconstructed system clock (TCK). Given a suitable synchronization of the respective bus node (BSn) and the bus master (BM), the respective bus node (BSn) generates an internal system base clock (ITCK.sub.n) which shows a pulse with a duration of a half-clock period only in the second half-clock period (T.sub.2H) of the third time slot (TDO.sub.z) of the system base clock period (T) of the n-th time slot package. With the rising edge of this system base clock signal, the respective bus node (BSn) in this example accepts the logical values of the data (TMS_TDI.sub.n) transmitted by the bus master (BM) which were detected by means of the following falling edge of TCK.sub.n. with the falling edge of the clock signal (TCK.sub.n) at the beginning of the next time slot package, the value (TDO.sub.n) to be transmitted in this example by the respective bus node (BSn) is changed. However, TDO.sub.n will become active only in the third time slot (TDO.sub.Z(n+1)) of the subsequent n+1-th time slot package, when the respective bus node (BSn) is allowed to transmit. A skilled person is aware that the control is possible not only by means of the control illustrated in FIG. 5, using the falling edge of the system clock (TCK.sub.n), but also by using the rising edge.

(47) FIG. 6

(48) FIG. 6 illustrates an exemplary two-wire data bus (b1b2b3) with three bus nodes (BS1, BS2, BS3), three two-wire data bus sections (b1, b2, b3) and one bus master (BM). The first two-wire data bus section (b1) connects the bus master (BM) to the first bus node (BS1).

(49) The second two-wire data bus section (b2) connects the second bus node (BS2) to the first bus node (BS1). The third two-wire data bus section (b3) connects the third bus node ((BS3) to the second bus node (BS2).

(50) The two-wire data bus is controlled by the bus master (BM) by means of a master two-wire data bus interface (OWM) to which the first two-wire data bus section (b1) is connected.

(51) The first two-wire data bus interface (OWS1) is connected to the first two-wire data bus section (b1). Via this first two-wire data bus section (b1), it receives data from the bus master (BM) and transmits such data to the same. Internally, it provides a first reconstructed system clock (TCK1) with which the internal JTAG interface of the first bus node (BS1) is operated. Further, it provides the first combined TMS-TDI signal (TMS_TDI1) which, in this example, includes the test mode signal (TMS) and the data input signal (TDI) in time-division multiplex. The finite automat (finite state machine) of the test controller (TAPC) of the JTAG interface of the first bus node (BS1) is controlled with the test mode signal (TMS). The data of the TDI signal portion are used to load the shift registers of the JTAG interface of the first bus node (BS1). Conversely, the JTAG interface supplies data back from the registers of the JTAG interface of the first bus node (BS1) with the serial TDo output signal. By a first transfer gate (TG1), the first two-wire data bus section (b1) can be connected to the following second two-wire data bus section (b2). For this purpose, the bus master (BM) writes a transfer gate control register (TGCR) of the first bus node (BS1), not shown, via the first two-wire data bus section (b1) and sets a flag in said transfer gate control register (TGCR) of the first bus node (BS1), which flag sets or cancels the first enable line (en.sub.1) in the first bus node (BS1). Depending on this first enable line (en.sub.1) of the first bus node (BS1), the first transfer gate (TG1) of the first bus node (BS1) is opened and closed. Thus, the two-wire data bus (b1b2b3) can be prolonged or shortened by means of an instruction from the bus master (BM) to the first bus node (BS1).

(52) The second two-wire data bus interface (OWS2) is connected to the second two-wire data bus section (b2). Via this second two-wire data bus section (b2), it receives data from the bus master (BM), if the first bus node (BS1) has closed its transfer gate (TG1). The second two-wire data bus interface (OWS2) also transmits such data to the bus master (BM). Internally, it provides a second reconstructed system clock (TCK2) with which the internal JTAG interface of the second bus node (BS2) is operated. Further, it provides the second combined TMS-TDI signal (TMS_TDI2) which, in this example, includes the test mode signal (TMS) and the data input signal (TDI) in time-division multiplex. The finite automat (finite state machine) of the test controller (TAPC) of the JTAG interface of the second bus node (BS2) is controlled with the test mode signal (TMS). The data of the TDI signal portion are used to load the shift registers of the JTAG interface of the second bus node (BS2). Conversely, the JTAG interface of the second bus node (BS2) supplies data back from the registers of the JTAG interface of the second bus node (BS2) with the serial TDo output signal. By a second transfer gate (TG2), the second two-wire data bus section (b2) can be connected to the third two-wire data bus section (b3). For this purpose, the bus master (BM) writes a transfer gate control register (TGCR) of the second bus node (BS2), not shown, via the first two-wire data bus section (b1) and the second two-wire data bus section (b2) and sets a flag in said transfer gate control register (TGCR) of the second bus node (BS2), which flag sets or cancels the second enable line (en.sub.2) of the second bus node (BS2). Depending on this second enable line (en.sub.2) of the second bus node (BS2), the second transfer gate (TG2) of the second bus node (BS2) is opened and closed. Thus, the two-wire data bus (b1b2b3) can be prolonged or shortened even further by means of an instruction from the bus master (BM).

(53) The third two-wire data bus interface (OWS3) is connected to the third two-wire data bus section (b3). Via this third two-wire data bus section (b3), is receives data from the bus master (BM), if the first bus node (BS1) has closed its transfer gate (TG1) and if the second bus node (BS2) has also closed its second transfer gate (TG2). The third two-wire data bus interface (OWS3) also transmits such data to the bus master (BM). Internally, it provides a third reconstructed system clock (TCK3) with which the internal JTAG interface of the third bus node (BS3) is operated. Further, it provides the third combined TMS-TDI signal (TMS_TDI3) which, in this example, includes the test mode signal (TMS) and the data input signal (TDI) for the JTAG interface of the third bus node (BS3) in time-division multiplex. The finite automat (finite state machine) of the test controller (TAPC) of the JTAG interface of the third bus node (BS3) is controlled with the test mode signal (TMS). The data of the TDI signal portion are used to load the shift registers of the JTAG interface of the third node (BS3). Conversely, the JTAG interface of the third bus node (BS3) supplies data back from the registers of the JTAG interface of the third bus node (BS3) with the serial TDo output signal. By a third transfer gate (TG3), of the third bus node (BS3), the third two-wire data bus section (b3) can connect to further two-wire data bus sections (b.sub.n). In the present instance, for the sake of example, the third bus node shall terminate the two-wire data bus (b1b2b3).

(54) Each of the bus nodes (BS1, BS2, BS3) is connected to sets of light emitting components (LM1, LM2, LM3) which are controlled by the respective bus node (BS1, BS2, BS3). Of course, other consumers of electric energy are conceivable.

(55) FIG. 7

(56) FIG. 7 corresponds to the apposition of two bus node data bus interfaces in the form of two right halves of the following FIG. 9. A preceding n-th two-wire data bus section (b.sub.n) is connected to a n-th bus node (BS.sub.n). This n-th bus node (BS.sub.n) can connect this preceding n-th two-wire data bus section (b.sub.n) to the succeeding n+1-th two-wire data bus section (b.sub.(n+1)) via its transfer gate (TGn). If the transfer gate (TG.sub.n) of the n-th bus node (BS.sub.n) is open, a differential switch, not illustrated, sets the differential level (TOW) on the n+1-th two-wire data bus section (b.sub.(n+1)), and thus on all succeeding two-wire data bus sections (b.sub.(n+1) with i>n+1), if existent or switched on by transfer gates, preferably to a defined differential potential difference and thereby prevents unintentional data transmission.

(57) The n+1-th bus node (BS.sub.(n+1)) can again connect this preceding n-th two-wire data bus section (b.sub.n) to the n+2-th two-wire data bus section (b.sub.(n+2) via its transfer gate (TG.sub.(n+2)). If the transfer gate (TG.sub.(n+1)) of the n+1-th bus node (BS.sub.(n+1)) is open, a differential switch, not illustrated, again sets the differential level (TOW) on the n+2-th two-wire data bus section (b.sub.(n+2)), and thus on all succeeding two-wire data bus sections (b.sub.(n+3)), if existent or switched on by transfer gates, preferably to a defined differential potential difference and thereby prevents unintentional data transmission.

(58) FIG. 8

(59) FIG. 8 shows the implementation of the disclosure for a master two-wire data bus interface (OWM).

(60) In FIGS. 7 and 8, the essential parts of an interface for the realization of the protocol for a one-wire data bus or the first two-wire data bus section (b1) of the two-wire data bus (b1b2b3), connected as an example in the present instance, between the bus master (BM) and the respective bus node (BSn). Here, the reference potential for the signals on the two-wire data bus (b1b2b3) and the connected first two-wire data bus section (b1) of the two-wire data bus (b1b2b3) is the second reference potential (GND) of the referential potential line (GND) which as an example is connected to ground.

(61) By the differential voltage divider formed by a lower resistor (R2a) between the first one-wire data bus (b1a) and thus the connected first one-wire data bus section (b1a) of the first one-wire data bus (b1a, b2a, b3a) of the two-wire data bus (b1b2b3) and the reference potential line (GND) with the second reference potential (GND) and a further lower resistor (R2b) between the second one-wire data bus (b1b, b2b, b3b) and thus the connected second one-wire data bus section (b1a) of the second one-wire data bus (b1b, b2b, b3b) of the two-wire data bus (b1b2b3) and the reference potential line (GND) with the second reference potential (GND) and an upper resistor (R1a) between the first one-wire data bus (b1a, b2a, b3a) and thus the connected first one-wire data bus section (b1a) of the first one-wire data bus (b1a, b2a, b3a) of the two-wire data bus (b1b2b3) and the supply voltage (V.sub.bat) with a potential (V.sub.IO) and a further upper resistor (R1b) between the second one-wire data bus (b1b, b2b, b3b) and thus the connected second one-wire data bus section (b1b) of the second one-wire data bus (b1b, b2b, b3b) of the two-wire data bus (b1b2b3) and the supply voltage (V.sub.bat) with a potential (V.sub.IO),

(62) the two-wire data bus (b1b2b3) in the form of the connected first two-wire data bus section (b1) is first maintained, with respect to the amount of the differential voltage level (TOW), on a medium second differential voltage value level (V.sub.M) between these two potentials (−V.sub.IO, V.sub.IO). On the master side, the dominant switches (T1a, T1b) are closed always in one half-clock period of the at least two half-clock periods (T.sub.1H, T.sub.2H) of preferably each of the three time slots of a system base clock period (T) of the system base clock. Thereby, a maximum differential signal level (TOW) on the two-wire data bus (b1b2b3) is forced. Since the internal resistance of the dominating switches (T1a, T1b) is preferably smaller than the internal resistance of the differential voltage divider of the two upper resistors (R1a, R1b) and the two lower resistors (R2a, R2b), the differential voltage level, which is the differential signal level (TOW), on the two-wire data bus (b1b2b3) is pulled from said medium second differential voltage value level (V.sub.M) in a second voltage value range (V.sub.B2) to at least the first differential voltage value level (−V.sub.IO), which is in the first voltage value range (V.sub.B1), in the respective half-clock period of the at least two half-clock periods (T.sub.1H, T.sub.2H) of preferably each of the three time slots of a system base clock period (T) by closing the dominant switches (T1a, T1b). The dominant switches (T1a, T1b) controlled by the system clock on the master side (TCK). If these dominant switches (T1a, T1b) are not closed, data can be transmitted bidirectionally in the other half-clock periods of the at least two half-clock periods (T.sub.1H, T.sub.2H) of preferably each time slot of the typically three time slots (TIN0, TIN1, TDO.sub.z) of a system base clock period (T). on the bus master side, a switched current source (T2a, T2b) feeds current into the two-wire data bus (b1b2b3), if the transmission line (TMS_TDI) from inside the bus master (BM) is active. For this purpose, the transmission line (TMS_TDI) from inside the bus master (BM) closes the switches (T2a, T2b) of the controllable current source. Preferably, these are transistors (MOS transistors in particular) that are operated as current sources in the activated state. Thus, current mirror circuits are particularly well suited to control them. Thereby, the transistor current sources of the controllable differential current source (T2a, T2b), configured in this manner, supply current into the two-wire data bus (b1b2b3). Preferably, the amount of this current is higher than the amount of the current that the differential pull circuit formed by the upper resistors (R1a, R1b) and the lower resistors (R2a, R2b) can discharge. Thus, in this case, the differential signal level (TOW) in the form of the potential difference on the two-wire data bus (b1b2b3) or at least on the connected first two-wire data bus section (b1) of the two-wire data bus (b1b2b3) moves, with respect to its amount, from the medium second differential voltage value level (V.sub.M) in a second voltage value range (V.sub.B2) to a potential near the supply voltage (V.sub.IO) for the switchable differential voltage source (T2a, T2b) of the bus master (BM) in the third voltage value range (V.sub.B3). If, however, the dominant switches (T1a, T1b) are closed, these overwrite the influence of the switchable differential voltage source (T2a, T2b) of the bus master (BM) and of the pull circuit formed by the upper resistors (R1a, R1b) and the lower resistors (R2a, R2b). These are not able, given a suitable configuration of the dominant switches (T1a, T1b), to determine the amount of the signal level (TOW) on the two-wire data bus (b1b2b3) or at least on the first two-wire data bus section (b1) of the two-wire data bus (b1b2b3), connected for the sake of example, against the dominant switches (T1a, T1b).

(63) The second switchable current source on the bus node side operates in the same manner, see FIG. 9. On the bus node side, a switched current source (T3a, T3b) feeds current into the two-wire data bus (b1b2b3) or the connected two-wire data bus section (b1, b2, b3) of the two-wire data bus (b1b2b3), if the transmission line (TDO.sub.n) from inside the bus master (BM) is active. For this purpose, the transmission line (TDO.sub.n) from inside the bus master (BM) of the bus node (BSn) of interest closes the switches (T3a, T3b) of the controllable current source. Preferably, the third transistor (T3a) shown in FIG. 8 and the further third transistor (T3b) are operated as a switchable current source. Thereby, the current source of the controllable current source (T3a, T3b) supplies current into the two-wire data bus (b1b2b3) or the connected two-wire data bus section (bn) of the one-wire data bus. Again, this current is preferably larger than the current that the pull circuit formed by the upper resistors (R1a, R1b) and the lower resistors (R2a, R2b) can discharge. Thus, the amount of the differential signal level (TOW) of the two-wire data bus (b1b2b3) or the connected two-wire data bus section (bn) in this case moves from the medium second differential voltage value level (V.sub.M) in a second voltage value range (V.sub.B2) to a potential near the supply voltage (V.sub.IO) for the switchable current source (T3a, T3b) of the bus node (BSn) of interest in the third voltage value range (V.sub.B3). If, however, the dominant switches (T1a, T1b) in the bus master (BM) are closed, these again overwrite the influence of the switchable current source (T3a, T3b) of the bus node (BSn) of interest and of the differential pull circuit (R1a, R1b, R2a, R2b). Given a suitable configuration of the dominant switch (T1a, T1b), both are unable to determine the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (bn) of the two-wire data bus (b1b2b3) against the dominant switches (T1a, T1b). Even if the switchable current sources (T2a, T2b) of the bus master (BM) are switched on in addition, the dominant switches (T1a, T1b) of the bus master (BM) will, given a suitable configuration thereof, still determine the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (bn) of the two-wire data bus (b1, b2, b3).

(64) On the bus node side, a third comparator (cmp3) compares the amount of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (bn) of the two-wire data bus (b1, b2, b3). to a third threshold value (V.sub.2H). At the same time, a second comparator (cmp2) compares the amount of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (bn) of the two-wire data bus (b1, b2, b3) to a second threshold value (V.sub.2L). The second threshold value (V.sub.2L) differs from the third threshold value (V.sub.2H) and determines the border between the first voltage value range (V.sub.B1) and the second voltage value range (V.sub.B2). The third threshold value (V.sub.2H) determines the boundary between the second voltage value range (V.sub.B2) and the third voltage value range (V.sub.B3). The second comparator (cmp2) recovers the system clock from the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (bn) of the two-wire data bus (b1, b2, b3). This signal is relayed to the inside of the bus node (BSn) of interest as a clock signal (TCK.sub.n) received by the bus node (BSn) of interest. The third comparator (cmp3) recovers the data information from the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (bn) of the two-wire data bus (b1, b2, b3) as data (TMS_TDI.sub.n) received by the bus node (BSn) of interest. Here, the data received by the bus node (BSn) of interest still include parts of the system clock. This can easily be remedied by simple sampling, e.g. in a flipflop, with the edge of a slightly delayed reconstructed system clock (TCK.sub.n) or, alternatively, by delaying the received data and sampling with a non-delayed reconstructed system clock (TCK.sub.n). If needed, the signals have to be processed before use.

(65) In one example, the data output signal (TMI_TDI.sub.n) could be switched to 1 by the third comparator (cmp3), if the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (bn) of the two-wire data bus (b1, b2, b3) is higher than the third threshold value (V.sub.2H), and can conversely be switched to 0, if the amount of the differential signal level (TOW) is lower than this third threshold value (V.sub.2H). In one example, the reconstructed system clock (TCK.sub.n) could be switched to 1 by the second comparator (cmp2), if the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (bn) of the two-wire data bus (b1, b2, b3) is higher than the second threshold value (V.sub.2L), and can conversely be switched to 0, if the amount of the differential signal level (TOW) is lower than this second threshold value (V.sub.2L).

(66) Similarly, the bus master (BM) samples the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (bn) of the two-wire data bus (b1, b2, b3) using a first comparator (cmp). For this purpose, the first comparator (cmp) compares the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (bn) of the two-wire data bus (b1, b2, b3) to a first threshold value (V.sub.2H) and thereby recovers the data on the data line, which also in this case still include parts of the system clock. Again, a suitable sampling is useful. In this manner, the data (TDo) received by the bus master (BM) are obtained. In one example, the data output signal (TDo) could be switched to 1 by the first comparator (cmp), if the amount of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (bn) of the two-wire data bus (b1, b2, b3) is higher than the first threshold value (V.sub.1L), and can conversely be switched to 0, if the potential is lower than this second threshold value (V.sub.1H). Except for a small tolerance range of preferably significantly less than 25% of this value, the first threshold value (V.sub.1H) is equal to the third threshold value (V.sub.2H).

(67) In the further processing, prior art circuits for a data bus with separate data line and system clock line can be used, so that a description thereof can be omitted here. As an example, reference is made to WO 2006/102284 A2.

(68) The following table of the amounts of the signal levels (TOW) and the logical values is obtained as a possible implementation. Other signal levels (TOW) and corresponding logical values are possible, of course, as will be known to a skilled person. It should be noted that in this example TCK=0 closes the dominant switches (T1a, T1b). Of course, this can also be implemented inversely.

(69) TABLE-US-00001 Two-wire data Transmit line/line section of Receive TCK TMS_TDI TDO.sub.n interest TCK.sub.n TMS_TDI.sub.n TDo BM BM BSn b1, b2, b3, b.sub.n BSn BSn BM 0 0 0 −V.sub.IO1 0 0 0 0 0 1 −V.sub.IO1 0 0 0 0 1 0 −V.sub.IO1 0 0 0 0 1 1 −V.sub.IO1 0 0 0 1 0 0 V.sub.M 1 0 0 1 0 1  V.sub.IO2 1 1 1 1 1 0  V.sub.IO1 1 1 1 1 1 1  .sup. V.sub.IO1/2 1 1 1

(70) Preferably, the third threshold value (V.sub.2H) and the first threshold value (V.sub.1H) coincide, whereby the bus master (BM) and the bus nodes detect the same data sequence. Using a correspondingly controlled chronological sampling, these data can then be suitably allocated to the time slots (TIN0, TIN1, TDO.sub.z).

(71) In contrast to German Patents DE-B-10 2015 004 433, DE-B-10 2015 004 434, DE-B-10 2015 004 435 and DE-B-10 2015 004 436, the bus node of the present disclosure typically has a differential transfer gate (TG) that has the function of two switches. The first switch can connect a preceding first one-wire data bus section (bna) of the preceding two-wire data bus section (bn) to a succeeding first one-wire data bus section (b(n+1)a) of the succeeding two-wire data bus section (b(n+1)). The second switch can connect a preceding second one-wire data bus section (bnb) of the preceding two-wire data bus section (b.sub.n) to a succeeding one-wire data bus section (b(n+1)b) of the succeeding two-wire data bus section (b(n+1)). If the transfer gate (TG.sub.n) of the respective bus node (BS.sub.n) is open, two further switches, not shown, preferably connect the succeeding two-wire data bus section (b(n+1)) to a holding potential or another suitable potential. Thereby, the differential signal level of the succeeding two-wire data bus (b(n+1)) is given a predefined signal level amount without a system clock, and thus data, being transmitted.

(72) Referring back to FIG. 8: the two voltage divider pairs which, for the sake of example, form the differential pull circuit, are formed by the first resistors (R1a, R1b) and the second resistors (R2a, R2b), respectively. The differential pull circuit is formed by a first voltage divider pair with a first resistor (R1a) and a second resistor (R2a). The differential pull circuit further comprises a second voltage divider pair with another first resistor (R2a) and another second resistor (R2b). The differential pull circuit maintains the amount of the differential voltage level (TW) on the two-wire data bus (b1b2b3) in the second voltage value range (V.sub.B2) on a medium second differential voltage value level (V.sub.M), if none of the other transmitters (T1a, T1b, T2a, T2b, T3a, T3b) is active. Here, as an example, the first two-wire data bus section (b1) is connected to the output of the master two-wire data bus interface (OWM). The data transmitter of the bus master is formed by the second transistors (T2a, T2b). The one second transistor (T2a) is a p-channel transistor in the present example. The other second transistor (T2b) is an n-channel transistor in the present example. The one first transistor (T1a) is an n-channel transistor in the present example. The other first transistor (T1b) is a p-channel transistor in the present example. The first transistor (T1a) is controlled with the system clock (TCK) via an exemplary inverting buffer circuit (buf). The other first transistor (T1b) is controlled directly in this example. The second transistor (T2a) is controlled with the combined signal TMS-TDI (TMS_TDI) via a NOR gate, if the system clock (TCK) is active. The other second transistor (T2b) is controlled via an exemplary inverting third buffer circuit (buf3), if the system clock (TCK) is inactive. The first amplifier (V1) generates the differential level signal (DPSM) in the bus master interface (OWM) on the basis of the differential voltage difference on the connected first two-wire data bus section (b1). A reference voltage (V.sub.1H), i.e. the first threshold value (V.sub.1H), by the voltage divider (R3), to which the first comparator (cmp) compares the differential signal level (TOW) in the form of the value of the differential level signal (DPSM)Δ in the bus master interface (OWM) and generates the data signal (TDo) for further processing in the bus master (BM). If necessary, the comparison result is delayed by a delay device (Δt).

FIG. 9

(73) FIG. 9 shows an exemplary implementation of the n-th one-wire data bus interface (OWS.sub.n) of an n-th bus node (BS.sub.n) of the bus nodes (BS1, BS2, BS3) corresponding to the master two-wire data bus interface (OWM) of FIG. 8. The two-wire data bus interface (OWS.sub.n) of the n-th bus node (BS.sub.n) is connected, for the sake of example, to the n-th two-wire data bus section (b.sub.n). The data transmitter of the n-th bus node (BSn) is formed by the third transistors (T3a, T3b). Their internal resistance (resistance in the switched-on state) is determined by a respective seventh resistor (R7a, R7b) connected in series to the respective third transistors (T3a, T3b). The second amplifier (V2) forms the differential level signal (DPS) in the bus node interface (OWSn) based on the differential voltage difference on the preceding connected n-th two-wire data bus section (bn). Two reference voltages, a third threshold value (V.sub.2H) and a third threshold value (V.sub.2L) are generated from the supply voltage (V.sub.bat) of the n-th bus node (bn) by the voltage divider formed by the fourth resistor (R4), the fifth resistor (R5) and the sixth resistor (R6). A second comparator (cmp2) and a third comparator (cmp3) compare the differential signal level (TWO) on the exemplary connected preceding n-th two-wire data bus section (b.sub.n) in the form of the value of the differential level signal (DPS) to the two reference voltages, the third threshold value (V.sub.2H) and the third threshold value (V.sub.2L). From this, they generate the reconstructed system clock (TCK.sub.n) of the n-th bus node (BS.sub.n) and the n-th combined TMS-TDI signal (TMS_TDI.sub.n) in the n-th (BS.sub.n) for controlling the test controller (TAPC) of the JTAG interface in the n-th bus node (BS.sub.n). Here, the clock and the data are again synchronized by a delay unit (Δt) for the combined TMS-TDI signal (TMS_TDI.sub.n). In this example, the output signal of the JTAG interface of the n-th bus node (BS.sub.n) is used to control the third transistor (T3a), and to directly control the further third transistor (T3b), via an inverting second buffer circuit (buf2). A person skilled in the art will have no difficulty to ensure the chronological structure of the signals by means of a suitable logic.

(74) FIG. 10

(75) FIG. 10 shows the internal structure of a JTAG interface of the present disclosure. The same is compatible with the architecture provided in the IEEE 1149 standard, so that software available on the market can be used, which is a significant advantage.

(76) In this example, in a test data processing (TB), the combined TMS-TDI signal (TMS_TDI.sub.n) is decomposed synchronous to the reconstructed system clock (TCK.sub.n) into the test mode signal (TMS) and the serial input data (TDI). Using the test mode signal (TMS), the test controller (TAPC) is again controlled synchronous to the clock corresponding to the state diagram already known from prior art and discussed with reference to the description of FIG. 1. In the sense of this disclosure, this state diagram of a test controller (TAPC) characterizes a JTAG interface, since software compatibility is only achieved by observing this state diagram. Due to the control signal (sir_sdr) for the first multiplexer (MUX1), the test controller switches between the instruction register (IR) and the data registers (BR, IDCR, RX, ILR) by means of the first multiplexer (MUX1). The serial data input (TDI) is routed to all data registers (BR, IDCR, RX, ILR), the instruction register (IR) and possibly further data registers. All these registers are typically of a two-stage design. This means that they have a shift register of a bit length m and, in parallel, a shadow register of the same length m. The shift register serves the transport of data, whereas the shadow register contains the valid data. As described before, the data are loaded from the shift register into the shadow register or are loaded or shifted from the shadow register into the shift register, or the data rest, depending on the state of the test controller (TAPC). In the example in FIG. 10, an instruction decoder (IRDC) controls the JTAG interface depending on the content of the instruction register (IR). For example, it is conceivable that the respective bus node may only transmit, if the shadow register of the instruction register (IR) contains certain values at certain bit positions, i.e. a certain transmission address. However, such an addressing may also be made in a separate transmission register (SR) (see FIG. 21).

(77) It is particularly preferred that the JTAG interface comprises a bus node address register (BKADR) (see FIG. 21). The same indicates the identification number of the bus node. Further, the JTAG interface preferably has a transmission register (SR). This transmission register (SR) is set by the bus master (BM) and indicates the number of the bus node which is to/may send. Only, if both addresses, i.e. the address in the bus node address register (BKADR) and the address in the transmission register (SR) coincide, may the respective bus node (BS.sub.n) transmit at the predetermined time. In order to set the bus node addresses in the bus node address registers (BKADR) of the bus nodes upon the initialization of the two-wire data bus system, all transfer gates (TG) of all bus nodes (BS1, BS2, BS3) or initially open. This may preferably be effected by a special instruction to all reachable instruction registers (IR) of all JTAG interfaces of the disclosure connected to the two-wire data bus (b1b2b3) and all reachable bus nodes. For this purpose, the instruction registers (IR) of these JTAG interfaces have to match in the bits with the lowest value, which are the shift register bits that are written first. Following a fixed algorithm, the bus master (BM) then allocates the first bus address to the first and only bus node (BS1) that is directly connected thereto, by writing the first bus node address register (BKADR) of the first bus node (BS1). Thereafter, the bus master (BM) typically, but not necessarily, tests the connection. Preferably, the bus node address register (BKADR) of the respective bus node (BSn) can only be written if the transfer gate (TGn) of the respective bus node (BSn) is not closed. Thereby, it is ensured that only the last bus node, seen from the bus master (BM), i.e. the first bus node in the series of bus node, whose transfer gate (TG) is not closed, accepts a bus node address into its bus node address register (BKADR). After such acceptance, the transfer gate (TG) is typically closed automatically or via software instruction from the bus master (BM). The bus node address stored in the bus address register is thereby frozen. At the same time, the addressing of the succeeding bus node can be performed. To allow an orderly reset of the bus system, e.g. an instruction that is the same for all bus nodes is provided in the instruction register (IR), which instruction opens all transfer gates of all bus nodes, so that a new allocation of addresses can be made. If, after an allocation of an address, the bus node with this bus node address does not answer, the bus node is either defective or it does not exist. In the latter case, the bus master knows the position of all bus nodes and their number.

(78) The exemplary JTAG interface of FIG. 10 comprises a bypass register (BR) compliant with the standard, which serves to bypass data through the JTAG interface. Further, in this example, it comprises an identification register (IDCR) for reading out a series number of the circuit and further data registers (RX) corresponding to the JTAG standard. These may be test registers and other registers, for example.

(79) According to the disclosure, an illumination register (ILR) is provided. In this illumination register (ILR), the bus master (BM) stores data for adjusting the energy supplies to the light emitting component (LM). Typically, the energy supplies are one or a plurality (three in the present instance) pulse width modulation (PWM) drivers (PWM1, PWM2, PWM3) generating a pulse width modulated (PWM) output voltage or a correspondingly modulated current.

FIG. 11

(80) FIG. 11 shows FIG. 10, with the difference that the JTAG interface additionally has an illumination instruction register (ILIR). The same controls a third multiplexer (MUX3). The latter can switch the serial input data for the illumination register (ILR) between a serial input for illumination data (SILDI.sub.n) and the serial data input (TDI) by means of an illumination data selection signal (ilds). At the same time, the output of the illumination register (ILR) is copied to the serial output for illumination data (SILDO.sub.n).

FIG. 12

(81) FIG. 12 shows a possible direct connection of a plurality of circuits with JTAG controllers according to FIG. 11 by a concatenation via the inputs for illumination data (SILDI1, SILDI2, SILDI3) and corresponding outputs for Illumination data (SILDO1, SILDO2, SILDO3).

(82) Thereby, it is possible to quickly transmit data for whole groups of light emitting components without complicated addressing, since only one component has to be addressed.

FIG. 13

(83) FIG. 13 shows a JTAG interface as in FIG. 10, with the difference that it comprises a separate transfer gate control register (TGCR). Instead of placing the flag for opening and closing the transfer gate (TG) in the instruction register (IR), a separate transfer gate control register (TGCR) may be provided which generates the corresponding enable line (en.sub.n) of the corresponding bus node (BS.sub.n).

FIG. 14

(84) FIG. 14 shows the possible direct connection of a plurality of circuits with JTAG controllers according to FIG. 15 through a concatenation by means of point-to-point connections in which data are transmitted bidirectionally and a clock is transmitted unidirectionally via the one-wire data bus sections (b1, b2, b3). Each bus node has a two-wire data bus interface (OWS1, OWS2, OES3) and a master two-wire data bus interface (OWM1, OWM2, OWM3). Thereby, a concatenation equivalent to the other Figures is obtained.

FIG. 15

(85) FIG. 15 shows a JTAG interface corresponding to FIG. 10, with the difference that it has a separate bus master control register (OWMCR). Instead of placing the control bits for controlling the bus master interface (OWM1, OWM2, OWM3) of the respective bus node (BS1, BS2, BS3) in the instruction register (IR), it is also possible to provide a separate bus master control register (OWMCR) that generates the corresponding control lines (ctr.sub.n) in the corresponding bus node (BS.sub.n).

FIG. 16

(86) FIG. 16 illustrates an exemplary housing for a bus node (BSn) in top plan view. The supply voltage lines (V.sub.bat, GND) may be connected free of intersections. The LEDs can be connected to the corresponding connectors (LED1, LED2, LED3, LED4) and to the negative supply voltage, i.e. the second reference potential (GND) of the reference potential line (GND) in a manner free of intersections. Between the bus nodes, the two-wire data bus (b1, b2) can be routed between the two supply voltage lines in a manner free of intersections, which shields the bus even better and allows for the use of microstrip lines with a defined wave impedance. This, in turn, makes the defined termination of the data bus seem possible. It is thus particularly feasible, if the wave impedance of the two-wire data bus (b1b2b3) matches the resistance of the differential pull circuit (R1a, R1b, R2a, R2b).

FIG. 17

(87) FIG. 17 is a top plan view on a light module for serial assembly. In this instance, the two-wire data bus can preferably be connected from the left-hand side. The succeeding two-wire data bus section (b2a, b2b) is preferably connected on the right-hand side. The supply voltage lines may be routed from the left-hand side to the right-hand side. The light emitting components (LED1, LED2, LED3) can be mounted in a recess (AS) of the housing (GH). An assembly on the housing (GH) is possible as well. The use of optical elements, such as lenses and mirrors, is useful for light beam modification.

FIG. 18

(88) FIG. 18 shows a still further simplified version of FIG. 17. The left-hand housing of FIG. 18 is a variant of the right-hand version, only mirrored vertically and horizontally with respect to the connectors for the supply voltage of the bus node (V.sub.bat) and the connector for the supply voltage (GND). Thus, the housings can be assembled across a surface and do not require 16, but only twelve connectors. However, it is a drawback that, on the one hand, an intersection becomes necessary which may e.g. be realized via the die pad of the integrated circuit that forms the bus node. For example, it is feasible, if the integrated circuit of the bus node is mounted on a die pad that is connected to the negative supply potential, i.e. the second reference potential (GND) of the reference potential line (GND). This die pad may serve as a bridge between the opposite supply voltage connectors for the negative supply voltage. If this die pad is electrically insulated towards the printed circuit, the positive supply voltage can be routed on the printed circuit beneath the light module. To enable an intersection-free assembly of the two-wire data busses, the checkerboard-like assembly of the non-mirrored and the mirrored variants on a printed circuit is necessary for forming a light module array.

(89) FIG. 18 also illustrates, how the connectors (V.sub.bat) are electrically connected to each other per housing (GH), while the reference potential connectors (GND) of each housing (GH) are electrically connected to each other in the same manner. Either the two connectors for the supply potential (V.sub.bat) or the two second supply potential connectors are electrically connected to each other via the so-called die paddle of a lead frame. The remaining supply potential connectors that are not electrically connected to each other via the lead frame, may e.g. be connected to each other via lines integrated in the die or via conductor paths on a printed circuit board (PCB).

FIG. 19

(90) FIG. 19 shows how the two light modules in FIG. 18 are arranged in an array form. It can be seen that in the arrangement in FIG. 19, a light module of the type of the right-hand side light module of FIG. 18 is situated below and above the left-hand side light module of FIG. 18. Correspondingly, in the array arrangement in FIG. 19, a light module of the type of the left-hand side light module of FIG. 18 is located above and below the right-hand side light module of FIG. 18.

FIG. 20

(91) FIG. 20 illustrates a two-dimensional concatenation of six light modules of FIG. 18, each with two master two-wire bus interfaces (OWM1a to OWM6a and OWM1b to OWM6b) and a two-wire data bus interface (OWS1 to OWS6). FIG. 20 illustrates the possible direct connection of a plurality of circuits with JTAG controllers as of FIG. 14 by a concatenation using point-to-point connections in which data are transmitted bidirectionally and a clock is transmitted unidirectionally via the one-wire data bus sections. Each bus node (BS1, BS2, BS3, BS4, BS5, BS6) has a two-wire data bus interface (OWS1, OWS2, OWS3, OWS4, OWS5, OWS6) and a first master two-wire bus interface (OWM1a, OWM2a, OWM3a, OWM4a, OWM5a, OWM6a), as well as a second master two-wire bus interface (OWM1b, OWM2b, OWM3b, OWM4b, OWM5b, OWM6b). (Further two-wire data bus interfaces are conceivable, but are not illustrated for the sake of simplification). Thus, as in the other Figures, an equivalent two-dimensional concatenation is obtained.

FIG. 21

(92) FIG. 21 is a simplified illustration of a JTAG interface according to the disclosure with an illumination register (ILR), a bus node address register (BKADR) and a transmission register (SR).

(93) As an alternative, the disclosure can further be described by one of the following groups of features, wherein the groups of features can be combined randomly and individual features of a group of features can be combined with one or a plurality of features of one or a plurality of other groups of features and/or one or a plurality of the above described examples.

(94) 1. Data bus system with a differential two-wire data bus (b1b2b3) for the transmission of data between a bus master (BM) and between at least two bus nodes (BS1, BS2, BS3), a) wherein the two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by the bus nodes (BS1, BS2, BS3), and b) wherein the two-wire data bus (b1b2b3) is terminated by one of the bus nodes (BS1, BS2, BS3), i.e. the terminal bus node (BS3), and c) wherein each of the bus nodes (BS1, BS2, BS3), except for a first bus node (BS1), is connected to a preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3) via a preceding two-wire data bus section (b2, b3) of the two-wire data bus sections (b1, b2, b3), and d) wherein said one first bus node (BS1) is connected to the bus master (BM) via a preceding two-wire data bus section (b1) of the two-wire data bus sections (b1, b2, b3), and e) wherein each bus node (BS1, BS2, BS3), except for a terminal bus node (BS3), is connected to a subsequent bus node (BS3, BS4) of the bus nodes (BS1, BS2, BS3) via a subsequent two-wire data bus section (b2, b3) of the two-wire data bus sections (b1, b2, b3), and f) wherein the two-wire data bus system (b1, b2, b3) has a bus master (BM) with a master two-wire data bus interface (OWM), and g) wherein the master two-wire data bus interface (OWM) of the bus master (BM) is provided to bidirectionally transmit data via the two-wire data bus (b1b2b3) or at least a two-wire data bus section (b1, b2, b3) of the two-wire data bus sections (b1, b2, b3), hereinafter referred to as the two-wire data bus section (bn) of interest, and to receive data from the same, using a data bus protocol with more than two differential physical signal levels (TOW), and h) wherein the two-wire data bus section (bn) of interest comprises two signal lines (bna, bnb), and i) wherein a two-wire data bus interface (OWSn) of a bus node of interest of the bus nodes (BS1, BS2, BS3), hereinafter referred to as the bus node (BSn) of interest, is electrically connected to the two-wire data bus section (bn) of interest, and j) wherein the two-wire data bus interface (OWSn) of the bus node (BSn) of interest is provided to receive data via the two-wire data bus section (bn) of interest, using a data bus protocol with more than two differential physical levels (TOW), and k) wherein the two-wire data bus interface (OWSn) of the bus node (BSn) of interest is provided to transmit data via the two-wire data bus section (bn) of interest, using a data bus protocol with more than two differential physical signal levels (TOW), and l) wherein the bus node (BSn) of interest is in turn provided with a master two-wire data bus interface (OWMn), and m) wherein the master two-wire data bus interface (OWMn) of the bus node (BSn) of interest is provided to bidirectionally transmit data via at least one subsequent two-wire data bus section (b(n+1)) of the two-wire data bus sections (b1, b2, b3), hereinafter referred to as the subsequent two-wire data bus section (b(n+1)), to a subsequent bus node (BS(n+1)) and receive data from the same, using a data bus protocol with more than two differential physical signal levels (TOW), and n) wherein the bus node (BSn) of interest comprises a first bus master control register (OWMCRn) configured to control the master two-wire data bus interface (OWMn) of the bus node (BSn) of interest, and o) wherein the bus master (BM) is adapted to write the bus master control register (OWMCRn) of the bus node (BSn) of interest via the master two-wire data bus interface (OWM) of the bus master (BM) and the two-wire data bus (b1b2b3) or the two-wire data bus section (bn) of interest and the two-wire data bus interface (OWSn) of the bus node (BSn) of interest, and to thereby control the state of the master two-wire data bus interface (OWMn) of the bus node (BSn) of interest.

(95) 2. Method for operating a data bus between a first sub-device, i.e. the bus master (BM), and at least two further sub-devices, i.e. the bus nodes (BS1, BS2, BS3), a) wherein the data bus comprises a two-wire data bus (b1b2b3) divided into at least two two-wire data bus sections (b1, b2, b3) by the at least two bus nodes (BS1, BS2, BS3), and b) wherein the data bus is terminated by at least one of the bus nodes (BS1, BS2, BS3), i.e. the terminal bus nodes (BS3),

(96) the method comprising the following steps: c) bidirectional transmission of data, using a data protocol with more than two physical differential signal levels (TOW), via the two-wire data bus (b1b2b3) or at least one two-wire data bus section (b1, b2, b3) of the two-wire data bus sections (b1, b2, b3), hereinafter referred to as the two-wire data bus section of interest, between the bus master (BM) and at least one bus node (BS1, BS2, BS3), hereinafter referred to as the bus node (BSn) of interest, d) simultaneous transmission of a clock signal (TCK) via the two-wire data bus (b1b2b3) or the two-wire data bus section (bn) of interest from the bus master (BM) to at least the bus node (BSn) of interest with a system clock period (T) which is divided into at least three successive time slots (TIN0, TIN1, TDO.sub.z), each divided into at least a first half-clock period (T.sub.1H) and a second half-clock period (T.sub.2H), e) comparison of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or at least on the two-wire data bus section (bn) of interest to a third threshold value (V.sub.2H) by a first means of the bus node (BSn) of interest, f) comparison of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or at least on the two-wire data bus section (b1, b2, b3) of interest to a second threshold value (V.sub.2L), which second threshold value is different from the third threshold value (V.sub.2H), by a second means of the bus node (BSn) of interest, wherein the third and the second threshold value (V.sub.2L, V.sub.2H) define three signal voltage value ranges (V.sub.B1, V.sub.B2, V.sub.B3) between an operating voltage (V.sub.IO, V.sub.IO1, V.sub.IO2) and a reference potential (−V.sub.IO), and g) wherein a medium voltage value range as the second voltage value range (V.sub.B2) is delimited in the upward or the downward direction by a first voltage value range (V.sub.B1) of the three signal voltage value ranges (V.sub.B1, V.sub.B2, V.sub.B3), and wherein the second voltage value range (V.sub.B2) is delimited in the downward or the upward direction, i.e. opposite to the first voltage value range (V.sub.B1), by a third voltage value range (V.sub.B3) of the three signal voltage value ranges (V.sub.B1, V.sub.B2, V.sub.B3), h) transmission of the data on the two-wire data bus (b1b2b3) or at least on the two-wire data bus section (bn) of interest in a time slot package with a duration of a system clock period (T) with at least three successive time slots (TIN0, TIN1, TDO.sub.z), wherein the order of the time slots (TIN0, TIN1, TDO.sub.z) within the succession of these at least three time slots (TIN0, TIN1, TDO.sub.z) in one time slot package can be selected system-specifically, i. comprising the transmission of at least a check datum and/or a first datum in a first time slot (TIN0) and in a second time slot (TIN1) from the bus master (BM) to the bus node (BS1, BS2, BS3) of interest, wherein the bus node (BSn) of interest receives the check datum and the first datum, and ii. comprising the transmission of a second datum in the second voltage value range (V.sub.B2) and the third voltage value range (V.sub.B3) on the two-wire data bus (b1b2b3) or at least the two-wire data bus section (b1, b2, b3) of interest from the bus node (BS1, BS2, BS3) of interest to the bus master (BM) in the third time slot (TDO.sub.z) of the at least three successive time slots (TIN0, TIN1, TDO.sub.z), wherein the bus master (BM) receives the second datum, iii. wherein the transmission of the first datum and/or the second datum is performed in one half-clock period of the at least two half-clock periods (T.sub.1H, T.sub.2H) of the respective time slot by changing the differential signal level (TOW) on the two-wire data bus (b1b2b3) or at least the two-wire data bus section (bn) of interest between the second voltage value range (V.sub.B2) on the one hand and the third voltage value range (V.sub.B3) on the other hand via the first voltage value range (V.sub.B1) and by changing the differential signal level (TOW) in the opposite direction via the first voltage value range (V.sub.B1), iv. wherein the transmission of a system clock is performed in the respective other half-clock period of the at least two half-clock periods (T.sub.1H, T.sub.2H) of the respective time slot, wherein no data are transmitted in this half-clock period, and wherein the transmission of the system clock in the respective time slot is effected by changing the differential signal level (TOW) on the two-wire data bus (b1b2b3) or at least the two-wire data bus section (b.sub.n) of interest between the first voltage value range (V.sub.B1) on the one hand and the second voltage value range (V.sub.B2) and/or the third voltage value range (V.sub.B3) on the other hand and by changing in the opposite direction.

(97) 3. Housing (GH) for a bus node (BSn) in a data bus system according to one of the above numbers, for transmitting illumination data for light emitting components (LM1, LM2, LM3) by means of a differential two-wire data bus (b1b2b3), a) wherein the two-wire data bus (b1b2b3) serves to transmit data between the bus master (BM) and one of the bus nodes (BS1, BS2, BS3) on the one hand and between at least two bus nodes (BS1, BS2, BS3), and b) wherein the two-wire data bus (b1b2b3) is again divided by the bus nodes (BS1, BS2, BS3) into at least two two-wire data bus sections (b1, b2, b3), and c) wherein the housing (GH) of the bus node (BSn) comprises at least two rows of connectors, i.e, a first row of connectors (GND, b1a, b1b, V.sub.bat) and a second row of connectors (GND, b2a, b2b, V.sub.bat), and d) wherein at least these at least two rows of connectors are arranged opposite each other on the housing (GH), and e) wherein each of the rows of connectors comprises a connector for a first, in particular negative supply potential (GND), and a connector for a second, in particular positive supply potential (V.sub.bat), f) wherein the connector for the first supply potential (GND) of the first row of connectors (GND, b1a, b1b, V.sub.bat) is connected to the connector for the first supply potential (GND) of the second row of connectors (GND, b2a, b2b, V.sub.bat), and the connector for the second supply potential (V.sub.bat) of the first row of connectors (GND, b1a, b1b, V.sub.bat) is connected to the connector for the second supply potential (V.sub.bat) of the second row of connectors (GND, b2a, b2b, V.sub.bat), each being connected in a manner free of intersections, and g) wherein the two connectors (b1a, b1b) for a two-wire data bus section (b1) preceding the bus node are arranged in the first row of connectors (GND, b1a, b1b, V.sub.bat) between the connector for the first supply potential (GND) and the connector for the second supply potential (V.sub.bat), and h) wherein the two connectors (b2a, b2b) for a two-wire data bus section (b2) succeeding the bus node in the second row of connectors (GND, b2a, b2b, V.sub.bat) are arranged between the connector for the negative supply potential (GND) and the connector for the second reference potential (V.sub.bat), and i) wherein the connectors for connecting or controlling of light emitting components (LED1, LED2, LED3, LED4) in their respective row of connectors are arranged such that, in the respective row of connectors, the connector for the supply voltage via which the electric current is to be discharged again, which current flows through the light emitting components (LED1, LED2, LED3, LED4) from these connectors for the operation and/or for the control of light emitting components (LED1, LED2, LED3, LED4), are positioned, in the respective row of connectors, between the two connectors (b1a, b1b and b2a, b2b, respectively) for the associated two-wire data bus section (b1 and b2, respectively) and the connectors for connecting and/or controlling of light emitting components (LED1, LED2, LED3, LED4).

(98) 4. Light module having a housing (GH) for a bus node (BSn) in a data bus system as defined in numeral 1, for the transmission of illumination data for light emitting components (LED1, LED2, LED3) by means of a differential two-wire data bus (b1b2b3), a) wherein the two-wire data bus (b1b2b3) is provided for the transmission of data between a bus master (BM) and between at least two bus nodes (BS1, BS2, BS3) of light emitting components, and b) wherein the two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by the bus nodes (BS1, BS2, BS3), and c) wherein each bus node (BS2, BS3), except for a first bus node (BS1), is provided for connection to a preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3) via a preceding two-wire data bus section (b2, b3) of the two-wire data bus sections (b1, b2, b3) and the first bus node (BS1) is provided for connection to the bus master (BM) via a preceding two-wire data bus section (b1) of the two-wire data bus sections (b1, b2, b3), and d) wherein the housing (GH) of the bus node (BSn) comprises at least two rows of connectors, i.e. a first row of connectors (GND, b1a, b1b, V.sub.bat) and a second row of connectors (GND, b2a, b2b, V.sub.bat), and e) wherein at least these two rows of connectors are arranged opposite each other on the housing (GH), and f) wherein each of the rows of connectors has a connector for the supply potential (GND), and g) wherein each of the rows of connectors has a connector for the second supply potential (V.sub.bat), and h) wherein the connectors for the first supply potential and for the second supply potential are arranged such in each row of connectors that they can be connected in a manner free of intersections, if the connector for the first supply potential (GND) of the first row of connectors (GND, b1a, b1b, V.sub.bat) is connected to the connector for the first supply potential (GND) of the second row of connectors (GND, b2a, b2b, V.sub.bat) and if the connector for the second supply potential (V.sub.bat) of the first row of connectors (GND, b1a, b1b, V.sub.bat) is connected to the connector for the second supply potential (V.sub.bat) of the second row of connectors (GND, b2a, b2b, V.sub.bat), and i) wherein the two connectors (b1a, b1b) for a preceding two-wire data bus section (b1) of the bus node in the first row of connectors (GND, b1a, b1b, V.sub.bat) are arranged between the connector for the first supply potential (GND) of the first row of connectors (GND, b1a, b1b, V.sub.bat) and the connector for the second supply potential (V.sub.bat) of the first row of connectors (GND, b1a, b1b, V.sub.bat), and j) wherein the two connectors (b2a, b2b) for a succeeding two-wire data bus section (b2) of the bus node in the second row of connectors (GND, b2a, b2b, V.sub.bat) are arranged between the connector for the second supply potential (V.sub.bat) of the first row of connectors (GND, b1a, b1b, V.sub.bat) and the connector for the second supply potential (V.sub.bat) of the second row of connectors (GND, b2a, b2b, V.sub.bat), and k) wherein at least one light emitting component (LED1, LED2, LED3) is arranged in a recess (ASP) of the housing (GH) or on the housing (GH).

(99) 5. Light module of one of the preceding numerals, wherein at least three light emitting components (LED1, LED2, LED3) are arranged in a recess (ASP) of the housing and each of these at least three light emitting components (LED1, LED2, LED3) has a light color that, in human perception, differs from the others.

(100) 6. Light module having a housing (GH) for a bus node (BSn) in a data bus system as defined in one of the preceding numerals, for the transmission of illumination data for light emitting components (LED1, LED2, LED3) by means of a differential two-wire data bus (b1b2b3), a) wherein the two-wire data bus (b1b2b3) is provided for the transmission of data between a bus master (BM) and between at least two bus nodes (BS1, BS2, BS3) of light emitting components, and b) wherein the two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by the bus nodes (BS1, BS2, BS3), and c) wherein each bus node (BS2, BS3), except for a first bus node (BS1), is provided for connection to a preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3) via a preceding two-wire data bus section (b2, b3) of the two-wire data bus sections (b1, b2, b3) and the first bus node (BS1) is provided for connection to the bus master (BM) via a preceding two-wire data bus section (b1) of the two-wire data bus sections (b1, b2, b3), and d) wherein at least one bus node (BS.sub.n) is connectible to at least three two-wire data bus sections (b1, b2, b3), and e) wherein the housing (GH) of the bus node (BS.sub.n) comprises at least three rows of connectors, i.e. a first row of connectors (V.sub.bat, b1a, b1b), a second row of connectors (GND, b2a, b2b) and a third row of connectors (V.sub.bat, b3a, b3b) and possibly a fourth row of connectors (GND, b4a, b4b), and f) wherein each of the three or four rows of connectors has at least one adjacent row of connectors on the housing (GH), which is arranged at an angle of 90° with respect to said row of connectors, and g) wherein each row of connectors has exactly one connector for a supply potential (GND, V.sub.bat), and h) wherein each row of connectors that is adjacent to another row of connectors, has a connector for another supply potential than the supply potential whose connector is included in the other row of connectors, and i) wherein—with respect to a clockwise or counter-clockwise counting direction—this supply potential connector is the first connector of the row of connectors in all rows of connectors, respectively, and j) wherein each row of connectors comprises the two connectors of a two-wire data bus section, and k) wherein these two bus connectors of said one two-wire data bus section are situated adjacent to the supply potential connector of the row of connectors, and l) wherein at least one light emitting component (LED1, LED2, LED3) is arranged in a recess (ASP) of a housing (GH) or on the housing (GH).

(101) 7. Light module of one of the preceding numerals, a) comprising a mounting support (lead frame), b) wherein a first connector for a first supply potential (either GND or V.sub.bat) is situated in a first row of connectors, and c) wherein a second connector of this first supply potential (either GND or V.sub.bat) is situated in a second row of connectors, and d) wherein the first row of connectors is arranged opposite the second row of connectors, and e) wherein the first connector is electrically connected to the oppositely arranged second connector by the mounting support (lead frame).

(102) 8. Light module having a housing (GH) for a bus node (BS.sub.n) in a data bus system as defined in one of the preceding numerals, a) comprising connectors (b1a, b1b, b2a, b2b) for receiving illumination data via the differential two-wire data bus (b1b2b3), b) wherein the connectors (b1a, b1b, b2a, b2b) of the two-wire data bus (b1b2b3) are arranged between a supply potential connector (V.sub.bat) for the second supply potential and a supply potential connector (GND) for the first supply potential, and c) comprising at least one light emitting component (LED1, LED2, LED3), and d) comprising an illumination register (ILR) configured to be written via the two-wire data bus (b1b2b3), and e) comprising means for operating the light emitting components (LED1, LED2, LED3), wherein the brightness of the light emitting components depends on the data content of the illumination register (ILR).

(103) 9. Light module as defined in one of the preceding numerals, wherein the light module comprises at least two light emitting components (LED1, LED2, LED3), whose brightness can be adjusted differently depending on the data content of an illumination register (ILR) by adjusting different luminosities for the light emitting components (LED1, LED2, LED3).

LIST OF REFERENCE NUMERALS

(104) AS recess of the housing b1b2b3 two-wire data bus b1b2b3b4 two-wire data bus b1 first two-wire data bus section b1a first one-wire data bus section of the first two-wire data bus section (b1) b2 second two-wire data bus section b2a first one-wire data bus section of the second two-wire data bus section (b2) b2b second one-wire data bus section of the second two-wire data bus section (b2) b3 third two-wire data bus section b3a first one-wire data bus section of the third two-wire data bus section (b3) b3b second one-wire data bus section of the third two-wire data bus section (b3) b4 fourth two-wire data bus section b4a first one-wire data bus section of the fourth two-wire data bus section (b4) b4b second one-wire data bus section of the fourth two-wire data bus section (b4) b5 fifth two-wire data bus section b6 sixth two-wire data bus section bn n-th two-wire data bus section bna first one-wire data bus section of the n-th two-wire data bus section (bn) bnb second one-wire data bus section of the n-th two-wire data bus section (bn) b(n+1) (n+1)-th two-wire data bus section b(n+1)a first one-wire data bus section of the (n+1)-th two-wire data bus section (b(n+1)) b(n+1)b second one-wire data bus section of the (n+1)-th two-wire data bus section (b(n+1)) BKADR bus node address register BKADRn bus node address register of the bus node (BSn) of interest BM bus master BR bypass register BRn bypass register of the bus node (BSn) of interest BS1 exemplary first bus node BS2 exemplary second bus node BS3 exemplary third bus node BS4 exemplary fourth bus node BS5 exemplary fifth bus node BS6 exemplary sixth bus node BSn exemplary n-th bus node (the relevant bus node or bus node of interest is referred to at different locations in this disclosure as BS.sub.n). Thus, it is a random bus node (BS1, BS2, BS3). The number of the bus nodes can differ from 3. BS(n+1) exemplary (n+1)-th bus node buf buffer circuit buf2 second buffer circuit buf3 third buffer circuit bus node bus node circuit the bus node typically is the integrated circuit or another electric system controlled by the host processor, i.e. the bus master, via the two-wire data bus (b1b2b3) or at least a connected two-wire data bus section (b1, b2, b3). bus master master circuit the bus master (BM) typically is the host processor via which the integrated circuit, i.e. the respective bn (BSn) is controlled. cmp first comparator on the master side. The first comparator compares the amount of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or on the connected two-wire data bus section (b1, b2, b3) in the form of the value of the differential level signal (DPSM) in the bus master interface (OWM) to a first threshold value (V.sub.1H) and relays the data signal (TDo) received by the bus master (BM) to the inside of the circuit of the bus master (BM), typically the host processor. The first comparator detects the change of the amount of the signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (b1, b2, b3) from the third voltage value range (V.sub.B3) on the one hand into the first voltage value range (V.sub.B1) or the second voltage value range (V.sub.B2) on the other hand, and vice versa. cmp2 second comparator on the bus node side. The second comparator compares the amount of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or on the connected two-wire data bus section (b1, b2, b3) in the form of the value of the differential level signal (DPS) to a second threshold value (V.sub.2L) and relays the reconstructed system clock (TCK.sub.n) received by the respective bus node (BSn) to the inside of the circuit of the respective bus node (BSn), typically the integrated circuit or the system to be controlled. The second comparator detects the change of the amount of the signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (b1, b2, b3) from the first voltage value range (V.sub.B1), on the one hand, into the second voltage value range (V.sub.B2) or the third voltage value range (V.sub.B3), on the other hand, and vice versa. cmp3 third comparator on the bus node side. The third comparator compares the amount of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or on the connected two-wire data bus section (b1, b2, b3) in the form of the value of the differential level signal (DPSn) to a third threshold value (V.sub.2H) and relays the data signal (TMS_TDI.sub.n) received by the respective bus node (BS.sub.n) to the inside of the circuit of the respective bus node (BS.sub.n), typically the integrated circuit or the system to be tested or controlled. The third comparator detects the change of the amount of the signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus section (b1, b2, b3) from the third voltage value range (V.sub.B3), on the one hand, into the first voltage value range (V.sub.B1) or the second voltage value range (V.sub.B2), on the other hand, and vice versa. CIR state “load instruction register data” of the test controller (TAPC) CDR state “load data register data” of the test controller (TAPC) ctr1 control lines for controlling the bus master interface (OWM1) of the first bus node (BS1) ctr1a control lines for controlling the first bus master interface (OWM1a) of the first bus node (BS1) ctr1b control lines for controlling the second bus master interface (OWM1b) of the first bus node (BS1) ctr2 control lines for controlling the bus master interface (OWM2) of the second bus node (BS2) ctr2a control lines for controlling the first bus master interface (OWM2a) of the second bus node (BS2) ctr2b control lines for controlling the second bus master interface (OWM2b) of the second bus node (BS2) ctr3 control lines for controlling the bus master interface (OWM3) of the third bus node (BS3) ctr3a control lines for controlling the first bus master interface (OWM3a) of the third bus node (BS3) ctr3b control lines for controlling the second bus master interface (OWM3b) of the third bus node (BS3) ctr4 control lines for controlling the bus master interface (OWM4) of the fourth bus node (BS4) ctr4a control lines for controlling the first bus master interface (OWM4a) of the fourth bus node (BS4) ctr4b control lines for controlling the second bus master interface (OWM4b) of the fourth bus node (BS4) ctr5 control lines for controlling the bus master interface (OWM5) of the fifth bus node (BS5) ctr5a control lines for controlling the first bus master interface (OWM5a) of the fifth bus node (BS5) ctr5b control lines for controlling the second bus master interface (OWM5b) of the fifth bus node (BS5) ctr6 control lines for controlling the bus master interface (OWM6) of the sixth bus node (BS6) ctr6a control lines for controlling the first bus master interface (OWM5a) of the sixth bus node (BS5) ctr6b control lines for controlling the second bus master interface (OWM6b) of the sixth bus node (BS2) ctr.sub.n control lines for controlling the bus master interface (OWM.sub.n) of the n-th bus node (BS.sub.n) DPS Level signal of the bus node. The level signal is formed by the output of the second differential input amplifier (V2) of the respective two-wire data bus interface (OWS.sub.n) of a bus node. DPSn Level signal of the respective bus node (BSn). The level signal is formed by the output of the second differential input amplifier (V2n) of the respective two-wire data bus interface (OWS.sub.n) of a respective bus node (BSn). DPSM Level signal of the respective bus master (BM). The level signal is formed by the output of the first differential input amplifier (V1) of the bus master (BM) of the respective two-wire data bus interface (OWM) of the bus master (BM). DR Data register of the JTAG interface. (typically, a plurality of interfaces is connected in parallel and is selected via the second multiplexer (MUX2), while the data registers (DR) are read.) DRn Data register of the JTAG interface of the respective bus node (BSn). (typically, a plurality of interfaces is connected in parallel and is selected via the second multiplexer (MUX2n) of the respective bus node (BS.sub.n), while the data registers (DR) are read.) drs Selection signal for the data register to be read Δt Delay unit for the combined TMS-TDI signal in the bus node (TMS_TDI.sub.n) or the TDo signal in the bus master. EDR1 State “data register exit 1” of the test controller (TAPC) EDR2 State “data register exit 2” of the test controller (TAPC) EIR1 State “instruction register exit 1” of the test controller (TAPC) EIR2 State “instruction register exit 2” of the test controller (TAPC) en1 First enable line for opening and closing the first transfer gates (TG1) of the first bus node (BS1) en2 second enable line for opening and closing the second transfer gates (TG2) of the second bus node (BS2) en3 third enable line for opening and closing the third transfer gates (TG3) of the third bus node (BS3) en.sub.n n-th enable line for opening and closing the n-th transfer gates (TGn) of the n-th, respective bus node (BSn) GH Housing GND Reference potential line. The same is typically, but not necessarily, connected to ground. It has the second reference potential (GND). iTCK.sub.n Internal system base clock of the respective bus node (BSn) IDCR Identification register IDCRn Identification register of the bus node (BSn) of interest Ilds Illumination data selection signal Ildsn Illumination data selection signal of the bus node (BSn) of interest ILR Illumination register ILRn Illumination register of the bus node (BSn) of interest ILIR Illumination instruction register ILIRn Illumination instruction register of the bus node (BSn) of interest IR Instruction register of the JTAG interface IRn Instruction register of the JTAG interface of the bus node (BSn) of interest IRDC Instruction decoder IRDCn Instruction decoder of the bus node (BSn) of interest LED Light emitting diode. In the sense of this disclosure, this may also be the parallel and/or series connection of a plurality of LEDs. LED1 Connector for the first LED set (one LED or a plurality of LEDs connected in series and/or in series) LED2 Connector for the second LED set (one LED or a plurality of LEDs connected in series and/or in series) LED3 Connector for the third LED set (one LED or a plurality of LEDs connected in series and/or in series) LED4 Connector for the fourth LED set (one LED or a plurality of LEDs connected in series and/or in series) LM1 Set of light emitting components 1, controlled by the first bus node (BS1) LM2 Set of light emitting components 2, controlled by the second bus node (BS2) LM3 Set of light emitting components 3, controlled by the third bus node (BS3) LM4 Set of light emitting components 4, controlled by the fourth bus node (BS4) LM5 Set of light emitting components 5, controlled by the fifth bus node (BS5) LM6 Set of light emitting components 6, controlled by the sixth bus node (BS6) LMn Set of light emitting components, controlled by the bus node (BSn) of interest MUX1 First multiplexer in the JTAG interface for switching between the data registers (DR) and the instruction register (IR) MUX12 second multiplexer in the JTAG interface for selecting the active data register (DR) MUX3 third multiplexer for switching between a serial input for Illumination data (SILDI) and the serial input data (TDI) MUXn multiplexer for switching between a serial input for illumination data (SILDI.sub.n) and the serial input data (TDIn) of the bus node of interest NOR Inverting OR circuit OWM Master two-wire data bus interface OWM1 Master two-wire data bus interface of the first bus node (BS1) OWM1a First master two-wire data bus interface of the first bus node (BS1) OWM1b Second master two-wire data bus interface of the first bus node (BS1) OWM2 Master two-wire data bus interface of the second bus node (BS2) OWM2a First master two-wire data bus interface of the second bus node (BS2) OWM2b Second master two-wire data bus interface of the second bus node (BS2) OWM3 Master two-wire data bus interface of the third bus node (BS3) OWM3a First master two-wire data bus interface of the third bus node (BS3) OWM3b Second master two-wire data bus interface of the third bus node (BS3) OWM4 Master two-wire data bus interface of the fourth bus node (BS4) OWM4a First master two-wire data bus interface of the fourth bus node (BS4) OWM4b Second master two-wire data bus interface of the fourth bus node (BS4) OWM5 Master two-wire data bus interface of the fifth bus node (BS5) OWM5a First master two-wire data bus interface of the fifth bus node (BS5) OWM5b Second master two-wire data bus interface of the fifth bus node (BS5) OWM6 Master two-wire data bus interface of the sixth bus node (BS6) OWM6a First master two-wire data bus interface of the sixth bus node (BS6) OWM6b Second master two-wire data bus interface of the sixth bus node (BS6) OWMn Master two-wire data bus interface of the bus node (BSn) of interest OWMCR Bus master control register OWMCRn Bus master control register of the bus node (BSn) of interest OWS1 Two-wire data bus interface of the first bus node (BS1) OWS2 Two-wire data bus interface of the second bus node (BS2) OWS3 Two-wire data bus interface of the third bus node (BS3) OWS4 Two-wire data bus interface of the fourth bus node (BS4) OWS5 Two-wire data bus interface of the fifth bus node (BS5) OWS6 Two-wire data bus interface of the sixth bus node (BS6) OWS.sub.n Two-wire data bus interface of the bus node (BSn) of interest PCM Pulse code modulation PDM Pulse density modulation PDR State “pause data register” of the test controller (TAPC) PFM Pulse frequency modulation PIR State “pause instruction register” of the test controller (TAPC) POM Pulse-on-time modulation and/or pulse-off-time modulation PWM Pulse width modulation. (In the sense of the present disclosure, this term comprises all known types of pulse modulation, such as e.g. PFM, PCM, PDM, POM etc.) PWM1 First PWM unit PWM2 Second PWM unit PWM3 Third PWM unit PWMn PWM unit of the bus node (BSn) of interest R.sub.0 Internal resistance of the pull circuit (R.sub.1a, R.sub.1b, R.sub.2a, R.sub.2b) which, as a fourth real voltage source, maintains the two-wire data bus (b1b2b3) or the connected two-wire data bus section (b1, b2, b3) on a medium second differential voltage value level (V.sub.M), if the other transmitters (T1a, T1b, T2a, T2b, T3a, T3b) are not active. (Not illustrated in the Figures) R1a Upper resistor of the first voltage divider, which, for the sake of example, forms the differential pull circuit together with the second voltage divider. The differential pull circuit maintains the amount of the differential signal level (TOW) on the two-wire data bus (b1b2b3b4) in the second voltage value range (V.sub.B2) on a medium second differential voltage value level (V.sub.M), if none of the other transmitters (T1a, T1b, T2a, T2b, T3a, T3b) is active. R1b Upper resistor of the second voltage divider, which, for the sake of example, forms the differential pull circuit together with the first voltage divider. The differential pull circuit maintains the amount of the differential signal level (TOW) on the two-wire data bus (b1b2b3b4) in the second voltage value range (V.sub.B2) on a medium second differential voltage value level (V.sub.M), if none of the other transmitters (T1a, T1b, T2a, T2b, T3a, T3b) is active. R2a lower resistor of the first voltage divider, which, for the sake of example, forms the differential pull circuit together with the second voltage divider. The differential pull circuit maintains the amount of the differential signal level (TOW) on the two-wire data bus (b1b2b3b4) in the second voltage value range (V.sub.B2) on a medium second differential voltage value level (V.sub.M), if none of the other transmitters (T1a, T1b, T2a, T2b, T3a, T3b) is active. R2b lower resistor of the second voltage divider, which, for the sake of example, forms the differential pull circuit together with the first voltage divider. The differential pull circuit maintains the amount of the differential signal level (TOW) on the two-wire data bus (b1b2b3b4) in the second voltage value range (V.sub.B2) on a medium second differential voltage value level (V.sub.M), if none of the other transmitters (T1a, T1b, T2a, T2b, T3a, T3b) is active. R1 First resistor R.sub.1H Internal resistance of the second switchable real voltage source in the switched-on state, which is formed by the switchable current source, i.e. the transistors (T1a, T1b), of the bus master (BM). (Not illustrated in the Figures). R2 second resistor R.sub.2H Internal resistance of the third switchable real voltage source in the switched-on state, which is formed by the switchable current source, i.e. the transistors (T3a, T3b), of the respective bus node (BSn). (Not illustrated in the Figures). R3 Third resistor R4 Fourth resistor R5 Fifth resistor R6 Sixth resistor R7a Seventh resistor for adjusting the internal resistance of the switch of the controllable current source (T3a) for the transmitter of the respective bus node (BSn) R7b Seventh resistor for adjusting the internal resistance of the switch of the controllable current source (T3b) for the transmitter of the respective bus node (BSn) RUN State “wait” of the test controller (TAPC) RX Further data registers (DR) which correspond to the JTAG standard RXn Further data registers (DRn) of the respective bus node (BSn) which correspond to the JTAG standard SDRS State “start of data register shifting” in the test controller (TAPC) SILDIn Serial input for illumination data of the respective bus node (BSn) SILD11 Serial input for illumination data of the first bus node (BS1) SILD12 Serial input for illumination data of the second bus node (BS2) SILD13 Serial input for illumination data of the third bus node (BS3) SILDOn Serial output for illumination data of the respective bus node (BSn) SILDO1 Serial output for illumination data of the first bus node (BS1) SILDO2 Serial output for illumination data of the second bus node (BS2) SILDO3 Serial output for illumination data of the third bus node (BS3) SIRS State “start of instruction register shifting” in the test controller (TAPC) SIR State “shift instruction register” of the test controller (TAPC) sir_sdr Control signal for the first multiplexer (MUX1) between the instruction register (IR) and the data registers (DR) SDR State “shift data register” of the test controller (TAPC) SR Transmission register SRn Transmission register of the respective bus node (BSn) T System base clock period T1a First transistor for controlling the first one-wire data bus (b1a, b2a, b3a, b4a) of the two-wire data bus (b1b2b3b4) for transmitting the system clock from the bus master (BM) to bus nodes. The first transistor forms a dominant switch with respect to other transmitters (T2a, T3a, R1a, R2a) on the first one-wire data bus (b1a, b2a, b3a, b4a) of the two-wire data bus (b1b2b3b4). T1b Further first transistor for controlling the second one-wire data bus (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3b4) for transmitting the system clock from the bus master (BM) to bus nodes. The further first transistor forms a dominant switch with respect to other transmitters (T2b, T3b, R1b, R2b) on the second one-wire data bus (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3b4). T.sub.1H First half-clock period of at least two half-clock periods (T.sub.1H, T.sub.2H) of the system clock period T2a Second transistor for controlling the first one-wire data bus (b1a, b2a, b3a, b4a) of the two-wire data bus (b1b2b3b4) for transmitting data from the bus master (BM) to bus nodes. The second transistor forms a dominant switch with respect to the voltage divider of the differential pull circuit (R1a, R2a) on the first one-wire data bus (b1a, b2a, b3a, b4a) of the two-wire data bus (b1b2b3b4). The internal resistance of the second transistor in the switched-on state is set such that the first transistor (T1a) can overwrite one or a plurality of second and third transistors transmitting on the first one-wire data bus (b1a, b2a, b3a, b4a) of the two-wire data bus (b1b2b3b4). The second transistor preferably is on par with a third transistor (T3a). T2b Further second transistor for controlling the second one-wire data bus (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3b4) for transmitting data from the bus master (BM) to bus nodes. The further second transistor forms a dominant switch with respect to the voltage divider of the differential pull circuit (R1b, R2b) on the second one-wire data bus (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3b4). The internal resistance of the further second transistor in the switched-on state is set such that the further first transistor (T1b) can overwrite one or a plurality of further second and third transistors transmitting on the second one-wire data bus (b1a, b2a, b3a, b4a) of the two-wire data bus (b1b2b3b4). The further second transistor preferably is on par with a further third transistor (T3b). T.sub.2H Second half-clock period of at least two half-clock periods (T.sub.1H, T.sub.2H) of the system clock period T3a Third transistor for controlling the first one-wire data bus (b1a, b2a, b3a, b4a) of the two-wire data bus (b1b2b3b4) for transmitting data from the bus node (BSn) of interest to the bus master (BM). The third transistor forms a dominant switch with respect to the voltage divider of the differential pull circuit (R1a, R2a) on the first one-wire data bus of the two-wire data bus (b1b2b3b4). The internal resistance of the third transistor in the switched-on state is set such that the first transistor (T1a) can overwrite one or a plurality of second and third transistors transmitting on the first one-wire data bus (b1a, b2a, b3a, b4a) of the two-wire data bus (b1b2b3b4). The third transistor preferably is on par with a second transistor (T2a). T3b Further third transistor for controlling the second one-wire data bus (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3b4) for transmitting data from the bus node (BS.sub.n) of interest to the bus master (BM). The further third transistor forms a dominant switch with respect to the further voltage divider of the differential pull circuit (R1b, R2b) on the second one-wire data bus (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3b4). The internal resistance of the further third transistor in the switched-on state is set such that the further first transistor (T1b) can overwrite one or a plurality of further second and third transistors transmitting on the second one-wire data bus (b1a, b2a, b3a, b4a) of the two-wire data bus (b1b2b3b4). The further third transistor preferably is on par with a further second transistor (T2b). TAPC Test controller TAPCn Test controller of the respective bus node (BS.sub.n) TB Data processing TCK Clock input (test clock input) and system clock and clock signal (system clock) to be transmitted by the bus master (BM) TCK1 Reconstructed system clock in the first bus node (BS1) TCK1i Reconstructed system clock in the first bus node (BS1), coming from the first two-wire data bus interface (OWS1) of the first bus node (BS1) TCK1o Reconstructed system clock in the first bus node (BS1) for the master two-wire data bus interface (OWM1) of the first bus node (BS1) TCK1ao Reconstructed system clock in the first bus node (BS1) for the first master two-wire data bus interface (OWM1a) of the first bus node (BS1) TCK1bo Reconstructed system clock in the first bus node (BS1) for the second master two-wire data bus interface (OWM1b) of the first bus node (BS1) TCK2 Reconstructed system clock in the second bus node (BS2) TCK2i Reconstructed system clock in the second bus node (BS2), coming from the second two-wire data bus interface (OWS2) of the second bus node (BS2) TCK2o Reconstructed system clock in the second bus node (BS2) for the master two-wire data bus interface (OWM2) of the second bus node (BS2) TCK2ao Reconstructed system clock in the second bus node (BS2) for the second master two-wire data bus interface (OWM2a) of the second bus node (BS2) TCK2bo Reconstructed system clock in the second bus node (BS2) for the second master two-wire data bus interface (OWM2b) of the second bus node (BS2) TCK3 Reconstructed system clock in the third bus node (BS3) TCK3i Reconstructed system clock in the third bus node (BS3), coming from the third two-wire data bus interface (OWS3) of the third bus node (BS3) TCK3o Reconstructed system clock in the third bus node (BS3) for the master two-wire data bus interface (OWM3) of the third bus node (BS3) TCK3ao Reconstructed system clock in the third bus node (BS3) for the third master two-wire data bus interface (OWM3a) of the third bus node (BS3) TCK3bo Reconstructed system clock in the third bus node (BS3) for the third master two-wire data bus interface (OWM3b) of the third bus node (BS3) TCK4 Reconstructed system clock in the fourth bus node (BS4) TCK4i Reconstructed system clock in the fourth bus node (BS4), coming from the fourth two-wire data bus interface (OWS4) of the fourth bus node (BS4) TCK4o Reconstructed system clock in the fourth bus node (BS4) for the master two-wire data bus interface (OWM4) of the fourth bus node (BS4) TCK4ao Reconstructed system clock in the fourth bus node (BS4) for the fourth master two-wire data bus interface (OWM4a) of the fourth bus node (BS4) TCK4bo Reconstructed system clock in the fourth bus node (BS4) for the fourth master two-wire data bus interface (OWM4b) of the fourth bus node (BS4) TCK5 Reconstructed system clock in the fifth bus node (BS5) TCK5i Reconstructed system clock in the fifth bus node (BS5), coming from the fifth two-wire data bus interface (OWS5) of the fifth bus node (BS5) TCK5o Reconstructed system clock in the fifth bus node (BS5) for the master two-wire data bus interface (OWM5) of the fifth bus node (BS5) TCK5ao Reconstructed system clock in the fifth bus node (BS5) for the fifth master two-wire data bus interface (OWM5a) of the fifth bus node (BS5) TCK5bo Reconstructed system clock in the fifth bus node (BS5) for the fifth master two-wire data bus interface (OWM5b) of the fifth bus node (BS5) TCK6 Reconstructed system clock in the sixth bus node (BS6) TCK6i Reconstructed system clock in the sixth bus node (BS6), coming from the sixth two-wire data bus interface (OWS6) of the sixth bus node (BS6) TCK6o Reconstructed system clock in the sixth bus node (BS6) for the master two-wire data bus interface (OWM6) of the sixth bus node (BS6) TCK6ao Reconstructed system clock in the sixth bus node (BS6) for the sixth master two-wire data bus interface (OWM6a) of the sixth bus node (BS6) TCK6bo Reconstructed system clock in the sixth bus node (BS6) for the sixth master two-wire data bus interface (OWM6b) of the sixth bus node (BS6) TCK.sub.n Reconstructed system clock in the respective bus node (BSn) TDI Third time slot or bus node transmission time slot. The third time slot is typically used for transmission of the TDO signal of the JTAG test port according to the IEEE standard 1149 from the addressed bus node with permission to transmit to the bus master (BM). However, it is not ultimately necessary that this time slot is placed at the third chronological position. Other chronological orders are possible. TDo Serial data output (test data output) and data signal received by the bus master (BM) TDO1i Reconstructed data signal in the first bus node (BS1), coming from the first two-wire data bus interface (OWS1) of the first bus node (BS1) TDO1o Reconstructed data signal in the first bus node (BS1) for the master two-wire data bus interface (OWM1) of the first bus node (BS1) TDO1ao Reconstructed data signal in the first bus node (BS1) for the first master two-wire data bus interface (OWM1a) of the first bus node (BS1) TDO1bo Reconstructed data signal in the first bus node (BS1) for the second master two-wire data bus interface (OWM1b) of the first bus node (BS1) TDO2i Reconstructed data signal in the second bus node (BS2), coming from the second two-wire data bus interface (OWS2) of the second bus node (BS2) TDO2o Reconstructed data signal in the second bus node (BS2) for the master two-wire data bus interface (OWM2) of the second bus node (BS2) TDO2ao Reconstructed data signal in the second bus node (BS2) for the first master two-wire data bus interface (OWM2a) of the second bus node (BS2) TDO2bo Reconstructed data signal in the second bus node (BS2) for the second master two-wire data bus interface (OWM2b) of the second bus node (BS2) TDO3i Reconstructed data signal in the third bus node (BS3), coming from the third two-wire data bus interface (OWS3) of the third bus node (BS3) TDO3o Reconstructed data signal in the third bus node (BS3) for the master two-wire data bus interface (OWM3) of the third bus node (BS3) TDO3ao Reconstructed data signal in the third bus node (BS3) for the first master two-wire data bus interface (OWM3a) of the third bus node (BS3) TDO3bo Reconstructed data signal in the third bus node (BS3) for the second master two-wire data bus interface (OWM3b) of the third bus node (BS3) TDO4i Reconstructed data signal in the fourth bus node (BS4), coming from the fourth two-wire data bus interface (OWS4) of the fourth bus node (BS4) TDO4o Reconstructed data signal in the fourth bus node (BS4) for the master two-wire data bus interface (OWM4) of the fourth bus node (BS4) TDO4ao Reconstructed data signal in the fourth bus node (BS4) for the first master two-wire data bus interface (OWM4a) of the fourth bus node (BS4) TDO4bo Reconstructed data signal in the fourth bus node (BS4) for the second master two-wire data bus interface (OWM4b) of the fourth bus node (BS4) TDO5i Reconstructed data signal in the fifth bus node (BS5), coming from the fifth two-wire data bus interface (OWS5) of the fifth bus node (BS5) TDO5o Reconstructed data signal in the fifth bus node (BS5) for the master two-wire data bus interface (OWM5) of the fifth bus node (BS5) TDO5ao Reconstructed data signal in the fifth bus node (BS5) for the first master two-wire data bus interface (OWM5a) of the fifth bus node (BS5) TDO5bo Reconstructed data signal in the fifth bus node (BS5) for the second master two-wire data bus interface (OWM5b) of the fifth bus node (BS5) TDO6i Reconstructed data signal in the sixth bus node (BS6), coming from the sixth two-wire data bus interface (OWS6) of the sixth bus node (BS6) TDO6o Reconstructed data signal in the sixth bus node (BS6) for the master two-wire data bus interface (OWM6) of the sixth bus node (BS6) TDO6ao Reconstructed data signal in the sixth bus node (BS6) for the first master two-wire data bus interface (OWM6a) of the sixth bus node (BS6) TDO6bo Reconstructed data signal in the sixth bus node (BS6) for the second master two-wire data bus interface (OWM6b) of the sixth bus node (BS6) TDO.sub.n Serial data to be transmitted from within the bus node (BSn) of interest TINI0 first time slot. The first time slot is typically used for transmission of the TMS signal of the JTAG test port according to the IEEE standard 1149 from the bus master (BM) to the respective bus node (BS1, BS2, BS3). However, it is not ultimately necessary that this time slot is placed at the first chronological position. Other chronological orders are possible. TINI1 second time slot. The second time slot is typically used for transmission of the TDI signal of the JTAG test port according to the IEEE standard 1149 from the bus master (BM) to the bus node (BS1, BS2, BS3). However, it is not ultimately necessary that this time slot is placed at the second chronological position. Other chronological orders are possible. TLR State “reset test logic” TMS Mode input (test mode input) or test mode signal TMS_TDI1 Combined TMS_TDI signal in the first bus node (BS1) TMS_TDI1i Combined TMS_TDI signal in the first bus node (BS1), coming from the first two-wire data bus interface (OWS1) of the first bus node (BS1) TMS_TDI1o Combined TMS_TDI signal in the first bus node (BS1) for the master two-wire data bus interface (OWM) of the first bus node (BS1) TMS_TDI1ao Combined TMS_TDI signal in the first bus node (BS1) for the first master two-wire data bus interface (OWM1a) of the first bus node (BS1) TMS_TDI1bo Combined TMS_TDI signal in the first bus node (BS1) for the second master two-wire data bus interface (OWM1b) of the first bus node (BS1) TMS_TDI2 Combined TMS_TDI signal in the second bus node (BS2) TMS_TDI2i Combined TMS_TDI signal in the second bus node (BS2), coming from the second two-wire data bus interface (OWS2) of the second bus node (BS2) TMS_TDI2o Combined TMS_TDI signal in the second bus node (BS2) for the master two-wire data bus interface (OWM) of the second bus node (BS2) TMS_TDI2ao Combined TMS_TDI signal in the second bus node (BS2) for the first master two-wire data bus interface (OWM2a) of the second bus node (BS2) TMS_TDI2bo Combined TMS_TDI signal in the second bus node (BS2) for the second master two-wire data bus interface (OWM2b) of the second bus node (BS2) TMS_TDI3 Combined TMS_TDI signal in the third bus node (BS3) TMS_TDI3i Combined TMS_TDI signal in the third bus node (BS3), coming from the third two-wire data bus interface (OWS3) of the third bus node (BS3) TMS_TDI3o Combined TMS_TDI signal in the third bus node (BS3) for the master two-wire data bus interface (OWM) of the third bus node (BS3) TMS_TDI3ao Combined TMS_TDI signal in the third bus node (BS3) for the first master two-wire data bus interface (OWM3a) of the third bus node (BS3) TMS_TDI3bo Combined TMS_TDI signal in the third bus node (BS3) for the second master two-wire data bus interface (OWM3b) of the third bus node (BS3) TMS_TDI4 Combined TMS_TDI signal in the fourth bus node (BS4) TMS_TDI4i Combined TMS_TDI signal in the fourth bus node (BS4), coming from the fourth two-wire data bus interface (OWS4) of the fourth bus node (BS4) TMS_TDI4o Combined TMS_TDI signal in the fourth bus node (BS4) for the master two-wire data bus interface (OWM) of the fourth bus node (BS4) TMS_TDI4ao Combined TMS_TDI signal in the fourth bus node (BS4) for the first master two-wire data bus interface (OWM4a) of the fourth bus node (BS4) TMS_TDI4bo Combined TMS_TDI signal in the fourth bus node (BS4) for the second master two-wire data bus interface (OWM4b) of the fourth bus node (BS4) TMS_TDI5 Combined TMS_TDI signal in the fifth bus node (BS5) TMS_TDI5i Combined TMS_TDI signal in the fifth bus node (BS5), coming from the fifth two-wire data bus interface (OWS5) of the fifth bus node (BS5) TMS_TDI5o Combined TMS_TDI signal in the fifth bus node (BS5) for the master two-wire data bus interface (OWM) of the fifth bus node (BS5) TMS_TDI5ao Combined TMS_TDI signal in the fifth bus node (BS5) for the first master two-wire data bus interface (OWM5a) of the fifth bus node (BS5) TMS_TDI5bo Combined TMS_TDI signal in the fifth bus node (BS5) for the second master two-wire data bus interface (OWM5b) of the fifth bus node (BS5) TMS_TDI6 Combined TMS_TDI signal in the sixth bus node (BS6) TMS_TDI6i Combined TMS_TDI signal in the sixth bus node (BS6), coming from the sixth two-wire data bus interface (OWS6) of the sixth bus node (BS6) TMS_TDI6o Combined TMS_TDI signal in the sixth bus node (BS6) for the master two-wire data bus interface (OWM) of the sixth bus node (BS6) TMS_TDI6ao Combined TMS_TDI signal in the sixth bus node (BS6) for the first master two-wire data bus interface (OWM6a) of the sixth bus node (BS6) TMS_TDI6bo Combined TMS_TDI signal in the sixth bus node (BS6) for the second master two-wire data bus interface (OWM6b) of the sixth bus node (BS6) TMS_TDI.sub.n Combined TMS_TDI signal in the bus node (BS.sub.n) of interest TRST Optional reset input (test reset input) TG1 Transfer gate of the exemplary first bus node (BS1) TG2 Transfer gate of the exemplary second bus node (BS2) TG3 Transfer gate of the exemplary third bus node (BS3) TGn Transfer date of the exemplary bus node (BSn) of interest TGCR Transfer gate control register TGCRn Transfer gate control register of the bus node (BSn) of interest TOW Differential signal level. The differential signal level on the two-wire data bus (b1b2b3b4) is the potential difference between the first one-wire data bus and the second one-wire data bus of the two-wire data bus (b1b2b3b4). UDR2 State “write data register” of the test mode controller UIR2 State “write instruction register” of the test mode controller V.sub.bat Supply voltage of the bus node V.sub.M Medium second differential voltage value level in the second voltage value range (V.sub.B2) that occurs, when no other transmitter (T1a, T1b, T2a, T2b, T3a, T3b) is active and thus the pull circuit (R1a, R1b, R.sub.2a, R2b) prevails. V.sub.1H First threshold value. The first threshold value separates the third voltage value range (V.sub.B3), on the one hand, from the first voltage value range (V.sub.B1) and the second voltage value range (V.sub.B2), on the other hand, on the bus master side. The first threshold value is preferably equal or similar to the third threshold value (V.sub.2H). It is used for the transmission of data. V.sub.2L second threshold value. The second threshold value separates the first voltage value range (V.sub.B1), on the one hand, from the third voltage value range (V.sub.B3) and the second voltage value range (V.sub.B2), on the other hand, on the bus node side. It is used for the transmission of the clock. V.sub.2H third threshold value. The third threshold value separates the third voltage value range (V.sub.B3), on the one hand, from the first voltage value range (V.sub.B1) and the second voltage value range (V.sub.B2), on the other hand, on the bus node side. The third threshold value is preferably equal or similar to the first threshold value (V.sub.1H). It is used for the transmission of data. V.sub.B1 First voltage value range delimited towards the second voltage value range (V.sub.B2) by the second threshold value (V.sub.2L). it is used for the transmission of the clock. V.sub.B2 Second voltage value range between the first voltage value range (V.sub.B1) and the third voltage value range (V.sub.B3), which is delimited towards the first voltage value range (V.sub.B1) by the second threshold value (V.sub.2L) and which is delimited towards the third voltage value range (V.sub.B3) by the third threshold value (V.sub.2H) of the bus node and/or by the first threshold value (V.sub.1H) of the bus master (BM). It is used for the transmission of data. V.sub.B3 Third voltage value range which is delimited towards the second voltage value range (V.sub.B2) by the third threshold value (V.sub.2H) of the bus node and/or by the first threshold value (V.sub.1H) of the bus master (BM). It is used for the transmission of data. V.sub.ext1 External supply voltage −V.sub.IO First differential voltage value level V.sub.IO Third differential voltage value level and supply voltage for the pull circuit, in this instance for the voltage divider (R1a, R2a; R1b, R2b). V.sub.IO1 Supply voltage of the switchable current source (T2a, T2b) of the bus master, i.e. the host processor. The voltage level is in the third voltage value range (V.sub.B3). V.sub.IO2 Supply voltage of the switchable current source (T3a, T3b) of the bus node, i.e. the integrated circuit or the system to be tested or controlled. The voltage level is in the third voltage value range (V.sub.B3). VREF Reference voltage