ELECTRONIC DRIVING CIRCUIT FOR DRIVING ELECTRODES OF A MICROFLUIDIC DEVICE FOR MANIPULATION OF PARTICLES, AND CORRESPONDING ANALYSIS APPARATUS

Abstract

An electronic driving circuit for a microfluidic device, having a number of synchronized driving stages to generate a respective driving signal for each electrode or group of electrodes of the microfluidic device, the driving signals having a desired amplitude, frequency and phase-shift. Each driving stage has a switching-mode amplifier stage to receive a clock signal and a target signal and to generate, at an output thereof, an output signal defining a respective driving signal. The amplifier stage has: a switching module, coupled to a first internal node and controlled by the clock signal for selectively bringing the first internal node to a control signal; a filter module, coupled between the first internal node and the output, to provide the output signal; and a feedback module.

Claims

1. An electronic driving circuit (20) for a microfluidic device (1) having a number of electrodes (4,6), comprising a number of synchronized driving stages configured to generate a respective driving signal (V.sub.1,V.sub.2,V.sub.3) for each electrode or group of electrodes (4,6), the driving signals (V.sub.1,V.sub.2,V.sub.3) having a desired amplitude, frequency and phase-shift, wherein each driving stage includes a switching-mode amplifier stage (22) configured to receive a clock signal (CK) and a target signal (V.sub.t) and to generate, at an output (Out) thereof, an output signal (V.sub.out) defining a respective driving signal, the amplifier stage (22) comprising: a switching module (23), coupled to a first internal node (N.sub.1) and controlled by the clock signal (CK) for selectively bringing said first internal node (N.sub.1) to a control signal (V.sub.c); a filter module (25,26), coupled between the first internal node (N.sub.1) and the output (Out) and configured to provide the output signal (V.sub.out); and a feedback module (29), coupled to a feedback input (IN.sub.fb) of said driving stage, designed to receive a feedback signal (V.sub.fb) indicative of the value of the respective driving signal, and configured to generate, as a function of the comparison between said feedback signal (V.sub.fb) and said target signal (V.sub.t), the control signal (V.sub.c) for said switching module (23).

2. The circuit according to claim 1, wherein the clock signals (CK) of the amplifier stages (22) are designed to define the frequency and phase-shift of the respective driving signals (V.sub.1,V.sub.2,V.sub.3); and the target signals (V.sub.t) are designed to define the amplitude of the respective driving signals (V.sub.1,V.sub.2,V.sub.3).

3. The circuit according to claim 1, wherein the feedback module (29) is configured to feed-back the control signal (V.sub.c) towards the switching module (23), to amplitude-modulate the clock signal (CK), and thus define the amplitude of the output signal (V.sub.out).

4. The circuit according to claim 1, wherein the filter module (25,26) includes a band-pass filter (25) configured to select an operating frequency of the output signal (V.sub.out), and a blocking capacitor (26), at the output of the band-pass filter (25), configured to block any DC component.

5. The circuit according to claim 1, further including an offset generator (30), coupled to all the amplifier stages (22), configured to generate a unique offset voltage (V.sub.off) that is injected at the output (Out) of said amplifier stages (22), to define a controlled DC offset value of the respective driving signals (V.sub.1,V.sub.2,V.sub.3).

6. The circuit according to claim 5, further including an offset inductor (32) for each of the amplifier stages (22), the offset inductors (32) of the amplifier stages (22) having a first terminal in common, coupled to the output of the offset generator (30), and a second terminal coupled to the output (Out) of the respective amplifier stage (22).

7. The circuit according to claim 1, wherein the feedback module (29) includes: a filter-and-rectifier module (36-38), coupled to the feedback input (IN.sub.FB) of the amplifier stage (22) and configured to provide a comparison signal (V.sub.FB′), as a function of said feedback signal (V.sub.FB); a subtraction unit (39), configured to receive the comparison signal (V.sub.FB′) and the target signal (V.sub.t), to generate an error signal (V.sub.e), based on the difference between the comparison signal (V.sub.FB′) and the target signal (V.sub.t); and a voltage converter (40), coupled at the output of the subtraction unit (39) and configured to generate the control signal (V.sub.c) based on the error signal (V.sub.e).

8. The circuit according to claim 7, wherein the filter-and-rectifier module (36-38) includes: a high-pass filter (36), coupled to the feedback input (IN.sub.FB) of the amplifier stage (22); a rectifier (37), coupled to the output of the high-pass filter (36); and a low-pass filter (38), coupled to the output of the rectifier (37).

9. The circuit according to claim 1, wherein the switching module (23) of the amplifier stage (22) comprises: a switching element (24), coupled between a reference terminal (GND) and the first internal node (N.sub.1), and having a control terminal designed to receive the clock signal (CK); and an impedance element (28), coupled between the first internal node (N.sub.1) and a second internal node (N.sub.2) designed to receive the control signal (V.sub.c); and wherein said feedback module (29) is connected between the feedback input (IN.sub.FB) of said driving stage and the second internal node (N.sub.2), and is configured to generate said control signal (V.sub.c) on said second internal node (N.sub.2).

10. The circuit according to claim 9, wherein said impedance element (28) includes an inductor element.

11. The circuit according to claim 1, wherein the microfluidic device (1) defines a non-linear variable impedance load for the electronic driving circuit (20).

12. The circuit according to claim 1, wherein the driving signals (V.sub.1,V.sub.2,V.sub.3) are designed to generate dielectric fields at the electrodes (4,6) of the microfluidic device (1), as a function of the frequency, time-shift and amplitude of the driving signals (V.sub.1,V.sub.2, V.sub.3).

13. The circuit according to claim 12, wherein said dielectric fields are dielectrophoretic fields.

14. The circuit according to claim 13, wherein said dielectrophoretic fields define closed dielectrophoretic potential cages (11), designed to trap one or more particles (8) immersed in a fluid contained in the microfluidic device (1).

15. The circuit according to claim 1, wherein the output (Out) of the amplifier stages (22) are designed to be coupled to respective contact pads (9a, 9b, 9c) of the microfluidic device (1), electrically contacting respective electrode or group of electrodes (4,6).

16. The circuit according to claim 1, wherein said feedback signal (VFB) is designed to be picked-up within said microfluidic device (1).

17. An automated analysis apparatus (50), configured to cooperate with the microfluidic device (1) to perform analysis and/or separation operation on one or more particles (8) immersed in a fluid contained in the microfluidic device (1); the automated analysis apparatus (50) including the electronic driving circuit (20) according to claim 1.

18. The apparatus according to claim 16, including a control unit (52), configured to control the driving circuit (20) and to provide the clock signals (CK) and target signals (V.sub.t) to the amplifier stages (22) thereof.

19. A microfluidic device (1), configured to manipulate particles (8) immersed in a fluid, the microfluidic device (1) including an array (2) of electrodes (4) carried by a substrate (5), and a plate electrode (6), arranged suspended above the array (2), an analysis chamber (7) containing the fluid being defined between the array (2) and the plate electrode (6), the microfluidic device (1) being configured to cooperate with the electronic driving circuit (20) according to claim 1; wherein the driving signals (V.sub.1,V.sub.2,V.sub.3) are designed to drive electrodes or group of electrodes (4,6), to generate dielectric fields at the electrodes (4), as a function of the frequency, time-shift and amplitude of the driving signals (V.sub.1,V.sub.2,V.sub.3).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG. 1 shows a schematic view of a portion of a microfluidic device for manipulation of particles, with a related electronic driving circuit;

[0032] FIG. 2 is an electric representation of the electric load defined by the microfluidic device;

[0033] FIG. 3 is a schematic block diagram of the electronic driving circuit for the microfluidic device, according to one embodiment of the present solution;

[0034] FIG. 4 is a schematic block diagram of an amplifier stage of the electronic driving circuit of FIG. 3;

[0035] FIG. 5 is a schematic block diagram of the electronic driving circuit for the microfluidic device, according to a possible implementation of the present solution;

[0036] FIG. 6 is a schematic block diagram of an amplifier stage of the electronic driving circuit of FIG. 5;

[0037] FIGS. 7a and 7b show plots of electrical quantities related to a known electronic driving circuit (FIG. 7a) and to the electronic driving circuit, according to the present solution (FIG. 7b); and

[0038] FIG. 8 is a schematic block diagram of an analysis machine, operatively coupled to the microfluidic device.

DETAILED DESCRIPTION OF THE INVENTION

[0039] FIG. 3 shows an electronic driving circuit, denoted with 20, coupled to a microfluidic device, in the example the microfluidic device 1 discussed with reference to FIG. 1, here shown with its electric-load equivalent representation (as discussed with reference to FIG. 2).

[0040] Accordingly, the microfluidic device 1 here represents an unbalanced three-phase non-linear low impedance load in “Delta” configuration, with the first impedance Z.sub.12 between the first and second pads 9a, 9b; the second impedance Z.sub.31 between the first and third pads 9a, 9c; and the third impedance Z.sub.23 between the second and third pads 9a, 9b.

[0041] For example, in the simplified electrical model for the load: the first impedance Z.sub.12 has a resistive component R.sub.12 with a value comprised between 0.5e40Ω and a capacitive component C.sub.12 with a value comprised between 24 pF e2.4 nF; the second impedance Z.sub.31 has a resistive component R.sub.31 with a value comprised between 0.1e130Ω and a capacitive component C.sub.31 with a value comprised between 70 pF e7 nF; and the third impedance Z.sub.23 has a resistive component R.sub.23 with a value comprised between 0.01 e 1Ω and a capacitive component C.sub.23 with a value comprised between 0.5 e50 nF.

[0042] As discussed previously, a respective electrode or group of electrodes 4, 6 of the microfluidic device 1 is coupled to each of the pads 9a, 9b, 9c.

[0043] The impedance of the active chip of the microfluidic device 1 may have real and imaginary part, be non-linear and change during time.

[0044] Electronic driving circuit 20 is configured to provide to each of the pads 9a, 9b, 9c a respective driving signals, again denoted with V.sub.1, V.sub.2 and V.sub.3, for driving the respective electrode or group of electrodes.

[0045] In particular, the electronic driving circuit 20 includes a number of synchronized switching-mode amplifier stages 22, one for each electrode or group of electrodes to be driven with a respective driving signal V.sub.1, V.sub.2, V.sub.3, or, analogously, one for each pad 9a, 9b, 9c of the microfluidic device 1.

[0046] Each amplifier stage 22 has:

[0047] an output Out, that is to be coupled to a respective pad 9a, 9b, 9c of the microfluidic device 1 (and the respective electrode or group of electrodes), on which an output voltage V.sub.out is present (defining the respective driving signal for the microfluidic device 1);

[0048] a first input IN.sub.1, designed to receive a clock signal CK, e.g. a pulse train (or square wave) signal with a given frequency f;

[0049] a second input IN.sub.2, designed to receive a target signal V.sub.t, in particular a voltage signal defining a target (or desired) amplitude for the output voltage V.sub.out (as will be clarified hereinafter);

[0050] a feedback input IN.sub.fb, designed to receive a feedback signal V.sub.fb, for example a voltage signal, indicative of the driving signal supplied to the load (i.e., of the output voltage V.sub.out).

[0051] In particular, the feedback signal V.sub.fb is picked-up as close as possible to the load; in a possible embodiment, as shown in FIG. 3, the pick-up point of the feedback signal V.sub.fb is located within the active chip of the microfluidic device 1, in the example at the respective pad 9a, 9b, 9c.

[0052] In particular, clock signals CK received by the amplifier stages 22 are designed to synchronize operation of the same amplifier stages 22.

[0053] In detail, each amplifier stage 22 comprises:

[0054] a switching module 23, having a switching input coupled to the first input IN.sub.1 and receiving the clock signal CK, an output coupled to a first internal node N.sub.1, a signal input coupled to a second internal node N.sub.2 and receiving a control signal V.sub.c, and also a reference input coupled to a reference terminal, or ground (GND);

[0055] a reconstruction filter module 25, in particular a band-pass filter, having an input terminal coupled to the first input IN.sub.1 and an output terminal coupled to the output Out of the amplifier stage 22 via a blocking capacitor 26; and

[0056] a feedback module 29, having an input coupled to the feedback input IN.sub.fb of the amplifier stage 22, thereby being designed to receive the feedback voltage V.sub.fb, a reference input coupled to the second input IN.sub.2 of the same amplifier stage 22 and a feedback output coupled to the second internal node N.sub.2 (and to the switching module 23).

[0057] The feedback input of feedback module 29 is positioned as close to the load as possible, typically not inside the amplifier stage 22; according to a possible solution, the feedback input is within the active chip of the microfluidic device 1.

[0058] The electronic driving circuit 20 has a supply input 20a designed to receive a power supply voltage VDD, and further comprises, common to all the amplifier stages 22, a DC offset generator 30, configured to generate, at an offset output thereof, a controlled DC offset voltage V.sub.off (the DC offset generator 30 may include a voltage generator of a known type, e.g. of the band-gap type, here not discussed in detail).

[0059] According to a possible embodiment, the DC offset voltage V.sub.off is equal to 50% of the supply voltage V.sub.DD of the microfluidic device 1, for example 2.5 V in the case in which the supply voltage V.sub.DD is 5 V.

[0060] Each amplifier stage 22 is coupled to the offset output of the DC offset generator 30 via a respective offset inductor 32, which is coupled between the offset output and the output Out of the same amplifier stage 22.

[0061] As shown in the same FIG. 3, therefore, the offset inductors 32 of the various amplifier stages 22 are connected in a so-called “Wye” configuration, having a first terminal in common (coupled to the output of the DC offset generator 30), and a second terminal coupled to the output Out of the respective amplifier stage 22, injecting therein the DC offset voltage V.sub.oif.

[0062] Electronic driving circuit 20 operates to generate at the output Out of the amplifier stages 22 output signals V.sub.out having desired frequency, amplitude and mutual phase-shift (as discussed, these output signals V.sub.out are to be supplied as driving signals to the microfluidic device 1). According to a possible embodiment, the output signals V.sub.out are analog sinusoidal signals.

[0063] In particular, the frequency and phase-shift characteristics of each output signal V.sub.out are determined by the clock signal CK received at the first input IN.sub.1 of the respective amplifier stage 22, which determines the switching timing of the switching element 24.

[0064] The reconstruction filter module 25 has a very narrow bandwidth, centered at the desired operating frequency for the output signal V.sub.out, thus selecting from the signal at the first internal node N.sub.1 only this fundamental operating frequency and transferring it to the output Out.

[0065] The desired amplitude of the output signal V.sub.out is instead controlled by the target signal V.sub.t received at the second input IN.sub.2 of the respective amplifier stage 22, via the closed feedback loop defined by the feedback module 29.

[0066] In particular, the feedback module 29 is configured to generate, based on the comparison between the feedback signal V.sub.fb and the target signal V.sub.t, a control signal V.sub.c.

[0067] The control signal V.sub.c, provided to the switching module 23, defines the amplitude of the voltage that is selectively provided at the first internal node N.sub.1, when the switching module 23 internally defines a coupling between the first and second internal nodes N.sub.1i, N.sub.2. The control signal V.sub.c thus defines the amplitude of the output signal V.sub.out, amplitude-modulating the clock signal CK received at the first input IN.sub.1 of the amplifier stage 22.

[0068] The blocking capacitor 26, before the output Out, blocks any spurious DC component at the output of the reconstruction filter module 25, so that the DC offset voltage V.sub.off, provided by the DC offset generator 30 via the offset inductor 32, comes to constitute the only DC component in the output signal V.sub.out.

[0069] In particular, a unique and controlled DC offset value is therefore present in all the output signals V.sub.out of the various amplifier stages 22.

[0070] It is noted that the offset inductor 32 moreover decouples the DC offset generator 30 from the AC output signal V.sub.out.

[0071] With reference to FIG. 4, a possible circuit embodiment for the feedback module 29 of each amplifier stage 22 is now discussed; in the same FIG. 4, a buffer amplifier 34 is also shown, receiving the clock signal CK and providing a switching signal to the switching input of the switching module 23 based on the same clock signal CK (the signal switching between 0 V and the power supply voltage V.sub.DD.

[0072] In this embodiment, the feedback module 29 includes:

[0073] a high-pass-filter 36, coupled to the feedback input IN.sub.fb of the amplifier stage 22 and configured to perform a high-pass filtering of the feedback signal V.sub.fb, thereby blocking-out the low frequency (particularly the DC) components thereof;

[0074] a rectifier 37, coupled to the output of the high-pass filter module 36 and configured to extract the amplitude value from the filtered feedback signal V.sub.fb;

[0075] a low-pass filter 38 coupled to the output of the rectifier module 37 and configured to perform a low-pass filtering operation, for generating a comparison signal V.sub.FB′, that is therefore indicative of the amplitude value of the output signal V.sub.out;

[0076] a subtraction unit 39, receiving the comparison signal V.sub.FB′ from the rectifier 37 and the target signal V.sub.t provided at the second input IN.sub.2 of the amplifier stage 22, and configured to generate a difference (or error) signal V.sub.e, based on the difference between the comparison signal V.sub.FB′ and the target signal V.sub.t; and

[0077] a voltage converter 40, in particular a step-down voltage converter, which receives the error signal V.sub.e and generates a regulated DC output voltage representing the control signal V.sub.c that is fed-back to the switching module 23, for modulating the input clock signal CK and setting the amplitude of the output signal V.sub.out.

[0078] As shown in FIGS. 5 and 6 (that correspond to above FIGS. 3 and 4, respectively), in a possible implementation, the switching module 23 comprises:

[0079] a switching element 24, in particular a transistor, e.g. a MOSFET transistor (a BJT, or any other suitable transistor), coupled between the reference terminal, or ground (GND), and the first internal node N.sub.1, and having a control terminal (gate terminal of the MOSFET transistor) coupled to the first input IN.sub.1 and receiving the clock signal CK;

[0080] an impedance element 28, in particular including an inductor element, coupled between the first internal node N.sub.1 (being connected to the switching element 24) and the second internal node N.sub.2, thus receiving the control signal V.sub.c.

[0081] As will be evident, in this implementation, the impedance element 28 defines coupling between the first and second internal nodes N.sub.1, N.sub.2, selectively bringing the same second internal node N.sub.2 to the control signal V.sub.c, when the switching element 24 is open (the second internal node N.sub.2 being instead brought to ground, when the same switching element 24 is closed).

[0082] The performance of the electronic driving circuit 20 has been evaluated by the present Applicant by means of extensive simulations and tests.

[0083] A comparison between the plots shown in FIGS. 7a and 7b allow to immediately perceive the improved performance of the electronic driving circuit 20 according to the present solution (plots of FIG. 7b) with respect to that of a traditional solution (plots of FIG. 7a).

[0084] In particular, FIG. 7a refers to an electronic driving circuit of a traditional type, including class-AB amplifiers; the generated sine waves show a strong harmonic distortion, and a maximum power higher than 150 W is required from the power supply source.

[0085] As shown in FIG. 7b, the sine waves generated by the electronic driving circuit 20 according to the present solution show negligible harmonic distortion and a desired phase shifting (the driving signals V.sub.1 and V.sub.2 being in-phase signals, while the driving signal V.sub.3 being a counter-phase signal). Moreover, a maximum power lower than 70 W is required from the power supply source, in the same operating conditions.

[0086] As schematically shown in FIG. 8, the electronic driving circuit 20 may be included in an electronic analysis apparatus 50, e.g. performing analysis operations on cells that are selected and sorted via the microfluidic device 1.

[0087] Analysis apparatus 50 is provided with a receptacle 51, designed to receive the microfluidic device 1 filled with a buffer solution wherein the particles 8 (e.g. cells) to be analyzed are immersed.

[0088] A control unit 52 of the analysis apparatus 50 controls the electronic driving circuit 20 in order to provide the driving signals V.sub.1, V.sub.2, V.sub.3 to the electrodes 4, 6 of the same microfluidic device 1; in particular, the control unit 52 provides the clock signals CK and target signals V.sub.t to the amplifier stages 22, according to the analysis operations to be performed.

[0089] The analysis apparatus 50 may further include an imaging device 54, controlled by the control unit 52 to image the chamber 7 of the microfluidic device 1 and the particles 8 contained therein.

[0090] Control unit 52 is provided with suitable software to process the images acquired by the imaging device 54 and provide to a user visual depictions of the particles 8 in the microfluidic device 1 via a display (here not shown).

[0091] Particles 8 of interest may thus be identified and suitable driving signals V.sub.1, V.sub.2, V.sub.3 may be provided to the electrodes 4, 6 in order to move the same particles towards a reservoir of the microfluidic device 1, from which the same particles 8 may be extracted by a pick-up device 56 of the analysis apparatus 50.

[0092] The advantages of the solution described emerge clearly from the previous discussion.

[0093] In particular, the amplifier stages 22, implementing the discussed closed-loop control, allow to minimize the non-linearity introduced by the low-impedance active chip load, thereby offering a drastic reduction of the total harmonic distortion (THD).

[0094] The unique and controlled DC offset voltage V.sub.off, simultaneously injected at the output Out of the various amplifier stages 22, eliminates DC offset differences between the driving signals V.sub.1, V.sub.2, V.sub.3 and thus allows to avoid possible electrolytic and electro-corrosion phenomena, gas bubbles formation and damages to the electrodes 4, 6.

[0095] Moreover, the electrical characteristics of the output signals V.sub.out may advantageously be controlled by varying the input clock and target signals ck, V.sub.t, thus providing an easy to be configured driving solution (e.g. in terms of programmable amplitude, frequency and phase-shift of the driving signals V.sub.1, V.sub.2, V.sub.3).

[0096] In general, the present solution allows to achieve, with respect to traditional solutions: a high efficiency with low impedance loads; a high reliability due to lower heat dissipation; a high thermal stability; and cost, size and weight reduction.

[0097] Finally, it is clear that modifications and variations can be made to what described and illustrated herein, without thereby departing from the scope of the present invention as defined in the appended claims.

[0098] In particular, it is underlined that the electronic driving circuit 20 may include a different (e.g. higher) number of amplifier stages 22, in the case in which it is required to drive a different (e.g. higher) number of electrodes or group of electrodes (that may in that case constitute a different electric-load configuration).

[0099] Moreover, the output signals V.sub.out may have different patterns, e.g. may be square waves, instead of sine waves.

[0100] The frequency of the same output signals V.sub.out may be fixed, chosen for example between 100 kHz and 100 MHz (e.g. 2 MHz), or variable during time, e.g. in the same range 100 kHz-100 MHz.

[0101] As an alternative, the feedback signals V.sub.fb may be picked-up at pick-up points external to the chip of the microfluidic device 1, for example within interface electronic devices that couple the electronic driving circuit 20 to the same chip of the microfluidic device 1.

[0102] It is moreover underlined that the discussed electronic driving circuit 20 may advantageously be used in different applications, where it is required to drive electrodes or group electrodes with driving signals, providing a low total harmonic distortion and a controlled DC offset.