Electronic system comprising a lower redistribution layer and method for manufacturing such an electronic system

Abstract

The invention relates to a method for producing an electronic system, comprising: a step of forming a plurality of interconnect paths obtained via metal deposition on the sacrificial member to form a lower redistribution layer defining a plurality of lower connection ports connected to a plurality of inner connection ports; a step of depositing at least one electronic component on the lower redistribution layer; and a step of forming a plurality of three-dimensional interconnect paths obtained via metal deposition in order to connect the connectors of the electronic component to the inner connection ports of the lower redistribution layer.

Claims

1. A method for manufacturing an electronic system comprising: a step of applying a sacrificial element on a carrier, a step of producing a lower redistribution layer defining a plurality of lower connection ports connected to a plurality of inner connection ports forming connection ports of the system, the lower redistribution layer being formed by a plurality of interconnections produced by metal deposition, a step of transferring at least one electronic component onto the lower redistribution layer, the at least one electronic component comprising a front surface comprising a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the at least one electronic component being positioned facing the lower redistribution layer on a side of the inner connection ports, a step of depositing a passivation layer so as to cover a surface of the lower redistribution layer and the at least one electronic component while maintaining the plurality of connectors of the at least one electronic component and the inner connection ports uncovered, a step of producing a plurality of three-dimensional interconnections produced by metal deposition so as to connect the plurality of connectors of the at least one electronic component to the inner connection ports of the lower redistribution layer, the plurality of three-dimensional interconnections being produced by metal deposition in openings formed in a photosensitive resin layer, said openings defining shapes of the three-dimensional interconnections, an encapsulation step, and a step of separating the system from the sacrificial element.

2. The method according to claim 1, wherein the sacrificial element is an adhesive film.

3. The method according to claim 1, wherein the sacrificial element is configured to lose its adherence characteristics from a predetermined temperature.

4. The method according to claim 1, wherein the sacrificial element is configured to lose its adherence characteristics following an illumination.

5. The method according to claim 1, wherein lower connection ports extend under the at least one electronic component.

6. The method according to claim 1, further comprising a step of producing an opening in the system so as to uncover a front face of at least one electronic component having a sensor function.

7. The method according to claim 1, further comprising a step of forming a three-dimensional passive component on the at least one electronic component during the step of producing a plurality of three-dimensional interconnections.

8. The method according to claim 1, comprising a step of transferring at least two superimposed electronic components onto the lower redistribution layer and a step of connecting connectors of said at least two superimposed electronic components during the step of producing the plurality of three-dimensional interconnections.

9. The method according to claim 1, wherein the passivation layer is deposited conformally.

10. The method according to claim 1, further comprising a step of producing an upper redistribution layer connected to the plurality of connectors of said at least one electronic component.

11. The method according to claim 10, further comprising a step of depositing at least one electronic component on the upper redistribution layer, the at least electronic component on the upper redistribution layer comprising a front surface comprising a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the at least one electronic component on the upper redistribution layer being positioned facing the upper redistribution layer.

12. The method according to claim 1, wherein at least one connector and at least one inner connection port of the lower redistribution layer are spaced apart by a vertical distance greater than 10 μm and three-dimensionally interconnected.

13. The method according to claim 12, wherein at least one interconnection, connecting at least one connector and at least one inner connection port, has an aspect ratio greater than 2.5:1 for a vertical distance comprised between 10 μm and 100 μm.

14. A method for manufacturing an electronic system comprising: a step of applying a sacrificial element on a carrier, a step of producing a lower redistribution layer defining a plurality of lower connection ports connected to a plurality of inner connection ports forming connection ports of the system, the lower redistribution layer being formed by a plurality of interconnections produced by metal deposition, a step of transferring at least one electronic component onto the lower redistribution layer, the at least one electronic component comprising a front surface comprising a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the at least one electronic component being positioned facing the lower redistribution layer on a side of the inner connection ports, a step of producing a plurality of three-dimensional interconnections produced by metal deposition so as to connect the plurality of connectors of the at least one electronic component to the inner connection ports of the lower redistribution layer, the plurality of three-dimensional interconnections being produced by metal deposition in openings formed in a photosensitive resin layer, said openings defining shapes of the three-dimensional interconnections, a step of producing an opening in the system so as to uncover a front face of at least one electronic component having a sensor function, an encapsulation step, and a step of separating the system from the sacrificial element.

15. A method for manufacturing an electronic system comprising: a step of applying a sacrificial element on a carrier, a step of producing a lower redistribution layer defining a plurality of lower connection ports connected to a plurality of inner connection ports forming connection ports of the system, the lower redistribution layer being formed by a plurality of interconnections produced by metal deposition, a step of transferring at least one electronic component onto the lower redistribution layer, the at least one electronic component comprising a front surface comprising a plurality of connectors and a rear surface opposite to the front surface, the rear surface of the at least one electronic component being positioned facing the lower redistribution layer on a side of the inner connection ports, a step of producing a plurality of three-dimensional interconnections produced by metal deposition so as to connect the plurality of connectors of the at least one electronic component to the inner connection ports of the lower redistribution layer, the plurality of three-dimensional interconnections being produced by metal deposition in openings formed in a photosensitive resin layer, said openings defining shapes of the three-dimensional interconnections, a step of transferring at least two superimposed electronic components onto the lower redistribution layer and a step of connecting connectors of said at least two superimposed electronic components during the step of producing the plurality of three-dimensional interconnections, an encapsulation step, and a step of separating the system from the sacrificial element.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will be better understood on reading the description that follows, given uniquely as an example, and by referring to the appended drawings in which:

(2) FIGS. 1A-1I are schematic representations of steps of producing a system according to the invention,

(3) FIG. 2 is a schematic representation of an electronic component,

(4) FIG. 3 is a schematic representation of a system with connection balls integrated in a passivation layer,

(5) FIG. 4 is a schematic representation of a system with two passivation layers,

(6) FIG. 5 is a schematic representation of a system with two metal layers of three-dimensional interconnections,

(7) FIG. 6 is a schematic representation of a system with an opening for accessing an electronic component having a sensor function,

(8) FIGS. 7 and 8 represent a system comprising a surface mounted component,

(9) FIG. 9 represents a system comprising a three-dimensional passive component,

(10) FIGS. 10 and 11 represent several embodiments of systems comprising a redistribution layer placed in the upper part so as to connect to other electronic components, and

(11) FIG. 12 is a schematic representation of the mounting of a system according to the invention on an integrated circuit.

(12) The figures may obviously serve to better define the invention if need be.

DETAILED DESCRIPTION

(13) An electronic system will now be described comprising a plurality of electronic components capable of being mounted on a printed circuit in order to form an electronic board. Such an electronic board may be mounted in any sort of electronic device, for example, a computer, a watch, a smartphone, a connected object, an item of clothing, a portable item of equipment, etc.

(14) A “system in package” type system is advantageously formed, which comprises several electronic components. In the example that follows, the production of a system comprising conductive balls will be described but it goes without saying that it is also possible to produce a system of the QFN or LGA type of which the connection ports extend in a same plane in the continuity of said system, that is to say, without projecting.

(15) An example of manufacture of a system according to the invention will be described with reference to FIG. 1 illustrating several technical manufacturing steps.

(16) Firstly, with reference to FIG. 1A, a step of applying a sacrificial element 2 on a carrier 1 is represented.

(17) In a preferred manner, the carrier 1 is in the form of a flat surface based on silicon, glass, ceramic, metal, organic materials or any type of material capable of serving as support. The carrier 1 is preferably circular or rectangular but it goes without saying that other shapes could be suitable. Preferably, the surface area of the support is greater than 2000 mm.sup.2.

(18) The sacrificial element 2 has a double function. It makes it possible, on the one hand, to position in a precise and robust manner the lower redistribution layer 7 of the system during its production and, on the other hand, to be able to release it when the system is produced. In other words, the sacrificial element 2 forms a temporary support for the lower redistribution layer 7 in order that it is integrated in the system S.

(19) Further preferably, the sacrificial element 2 is in the form of a layer which is organic, inorganic, polymeric or metallic. The sacrificial element 2 may be deposited by spin coating, by spray, by lamination, by stamping, by growth or analogous. As an example, a sacrificial element 2 of the “ZoneBond”®, “WaferBond”® and “BrewerBond”® from Brewer Science, “WSS”® from 3M, “SELFA”® from Sekisui and “Revalpha”® from Nitto type. In a preferred manner, the sacrificial element 2 is in the form of an adhesive film which is simple to handle, in particular, double-sided. Preferably, the sacrificial element 2 is configured to lose its adherence characteristics from a predetermined temperature. For this purpose, a sacrificial element 2 of the “Revalpha”® from Nitto type is particularly suited. In another preferred manner, the sacrificial element 2 is configured to lose its adherence characteristics following an illumination, in particular, by a UV light source such as a laser and/or a mercury lamp. During such an illumination, the sacrificial element 2 converts the light into thermal energy or generates a gas, which cancels the adherence characteristics. For this purpose, a sacrificial element 2 of the “BrewerBond”® from Brewer Science or “WSS”® from 3M or “SELFA”® from Sekisui type is particularly suited. Further preferably, the sacrificial element 2 enables a lift-off of the system by mechanical action without deterioration. For this purpose, a sacrificial element 2 of the “TM-X12”® from Hitachi Chemicals type is particularly suited.

(20) With reference to FIG. 1B, a step is represented of producing a plurality of interconnections produced by metal deposition on the sacrificial element 2 in order to form a lower redistribution layer 7 defining a plurality of lower connection ports 71 connected to a plurality of inner connection ports 72. Such a redistribution layer 7 makes it possible to connect the connection ports 71, 72 which are spaced apart from each other in order to improve the integration.

(21) The lower redistribution layer 7 comprises lower connection ports 71 in contact with the sacrificial element 2 and inner connection ports 72, in the upper part, intended to connect with the electronic components 3. The lower connection ports 71 form the connection ports of the system S.

(22) With reference to FIG. 1B, a step is represented of depositing a first passivation layer 4 so as to cover the lower redistribution layer 7 while forming openings 40 maintaining a plurality of inner connection ports 72 of the lower redistribution layer 7 uncovered.

(23) The first passivation layer 4 may be composed of an organic or inorganic material, such as a semiconductor oxide, a metal oxide, a polymer or any other electrically insulating material. It may be deposited by spin coating, by spray, by lamination, by stamping, by growth, by printing (inkjet), by vacuum deposition or by any type of deposition known to those skilled in the art. Preferably, the openings 40 are produced by means of a photolithography method or by means of a wet and/or dry chemical etching, by plasma or by laser. In a preferred manner, photosensitive materials are favoured given the advantages offered by photolithography methods.

(24) The deposition of the first passivation layer 4 is optional, the electronic components 3 being able to be deposited directly on the lower redistribution layer 7.

(25) With reference to FIG. 1C, the method comprises a step of transferring at least one electronic component 3 onto the first passivation layer 4. As illustrated in FIG. 2, each electronic component 3 comprises a front surface 3A comprising a plurality of connectors 30 and a rear surface 3B opposite to the front surface 3A. Preferably, the rear surface 3B of each electronic component 3 is devoid of connectors 30. The rear surface 3B of the electronic component 3 is positioned in contact with the first passivation layer 4, facing the lower redistribution layer 7. The electronic components 3 are positioned outside of the openings 40 of the first passivation layer 4 as illustrated in FIG. 1C.

(26) In this example, as illustrated in FIG. 1C, two electronic components 3 are positioned directly in contact with the first passivation layer 4 and are designated level 1 electronic components. Other electronic components may be positioned in superposition on the level 1 electronic components 3, these electronic components 3 being designated level 2 electronic components. When an electronic component 3 is superimposed on an electronic component of given level n, the superimposed electronic component 3 has a level n+1. With reference to the right part of FIG. 1C, a level 2 electronic component is positioned on one of the level 1 electronic components. The rear surface 3B of the level 1 electronic components 3 is positioned on the first passivation layer 4.

(27) The positioning of the electronic components 3 is preferably achieved by a so-called “pick and place” transfer method. Furthermore, an adhesive layer is applied between two superimposed electronic components 3. The adhesive layer is deposited between the rear surface 3B of the upper level electronic component 3 and the front surface 3A of the lower level electronic component 3. The precise positioning makes it possible to guarantee an optimal interconnection.

(28) In a preferred manner, the total vertical thickness (electronic component(s) 3 and adhesive layer(s)) is greater than 10 μm, more particularly, greater than 40 μm. The sides of the electronic components 3 may be straight, overcut and/or undercut. For the sake of clarity, only electronic components 3 having straight sides have been used in the figures.

(29) With reference to the right part of FIG. 1C, the electronic system S comprises several electronic components 3 assembled vertically to form a stack. The electronic components 3 have the same orientation in the stack. The rear surface 3B of the upper level electronic component 3 is mounted on the front surface 3A of the lower level electronic component 3. It goes without saying that the electronic system S could comprise a stack of a large number of electronic components 3 of different natures.

(30) In a preferred manner, each upper level electronic component 3 of a stack has dimensions smaller than the lower level electronic component 3 so as to form a stack facilitating the formation of three-dimensional interconnections between the different electronic components 3. The compactness and integration density are thus increased in a practical manner.

(31) In a preferred manner, the stack is pyramidal or staircase-shaped. According to the latter case, it is possible to stack electronic components 3 having an identical size or instead electronic components 3 of larger size above electronic components 3 of smaller size. It goes without saying that the electronic components 3 may have different dimensions.

(32) In the absence of passivation layer 4, the electronic components 3 are transferred directly onto the lower redistribution layer 7.

(33) With reference to FIG. 1D, a step is represented of depositing a second passivation layer 4′ so as to cover the surface of the first passivation layer 4 and the front surface 3A of the electronic component 3 while forming openings 40′ maintaining the plurality of inner connection ports 72 of the redistribution layer 7 and the connectors 30 of the electronic components 3 uncovered.

(34) According to the need of the system, the second passivation layer 4′ is deposited conformally or so as to adapt the angle of the sides of the electronic components 3. The second passivation layer 4′ may be composed of an organic or inorganic material, such as a semiconductor oxide, a metal oxide, a polymer or any other electrically insulating material. It may be deposited by spin coating, by spray, by lamination, by stamping, by growth, by printing (inkjet), by vacuum deposition or by any type of deposition known to those skilled in the art.

(35) Still with reference to FIG. 1D, the openings 40′ are produced in the second passivation layer 4′, in order to uncover the connectors 30 of the electronic components 3 and the inner connection ports 72. Preferably, the openings 40′ are produced by means of a photolithography method or by means of a wet and/or dry chemical etching, by plasma or by laser. In a preferred manner, photosensitive materials are favoured given the advantages offered by photolithography methods.

(36) According to the need of the system, the passivation layer 4′ is deposited uniquely to cover the sides of the electronic components 3 as well as a part of the surface of the electronic component 3, thus forming a sarcophagus around said electronic component 3. In this case, the openings 40 in the passivation layer 4 are directly accessible to the three-dimensional interconnections.

(37) In the case where the surfaces and the sides of the electronic components 3 are insulating except at the level of the connectors 30, the deposition of the second passivation layer 4′ may not be applied, thus reducing the manufacturing time and cost.

(38) With reference to FIG. 1E, a step is represented of producing a plurality of three-dimensional interconnections 5 produced by metal deposition so as to connect the uncovered zones 40′ of the redistribution layer 7 to the connectors 30 of the electronic component 3.

(39) The three-dimensional interconnections are known per se, in particular, by the patent application FR2965659. In this example, to produce the three-dimensional interconnections 5, the method comprises: a step of depositing a metal layer by evaporation, by spray or other, which fulfils both a function of seed and growth base for the metal constituting the three-dimensional interconnections. This metal layer may be composed of a single or of several electrically conductive materials and/or semiconductors. a step of depositing a thick layer of photosensitive resin and a step of producing openings by photolithography techniques, by laser ablation or others, in order to create a mould necessary for the deposition of the metal constituting the three-dimensional interconnections. These openings define the shape of the three-dimensional interconnections 5 as well as those of the metal tracks connecting the connectors 30 of the electronic component 3 to the inner connection ports 72. According to the integration need, the thickness of the photosensitive resin layer can vary from 20 to 700 μm and the aspect ratio (resolution) from 0.5:1 to 50:1. a step of depositing a metal layer by electrolysis or any other metal growth technique. The deposited metal may be copper, gold, silver, nickel, an alloy of metals or any other electrically conductive material. a step of dissolution of the resin mould and a step of etching of the seed layer. These methods are known to those skilled in the art. However, in the case where the seed layer contains gold, a solution based on KI+I2 and additives could be used to etch this layer without damaging the three-dimensional interconnections.

(40) In this example, the lower connection ports 71 and the connectors 30 of the electronic components 3 are respectively connected together by the redistribution layer formed by the three-dimensional interconnections 5 produced by metal deposition and by the lower redistribution layer 7. Advantageously, even in the case of a plurality of electronic components 3, the three-dimensional interconnections 5 are produced during a single and same step, which procures an important time saving. The number of connectors 30 connected together depends on the degree of interaction between the two electronic components 3 in the electronic system S. The planar redistribution layer makes it possible to improve the routing between the electronic components 3 as well as the input/output ports of the system S, in particular, in the case of high density of connectors 30.

(41) With reference to FIG. 1F, an encapsulation step 6 is represented so as to encapsulate the electronic components 3 and the interconnections 5. In a preferred manner, the encapsulation layer 6 is made of polymer, for example made of epoxy, and filled or not with particles such as silica, alumina, etc., but it goes without saying that other analogous materials could be suitable. In a preferred manner, the encapsulation step is carried out by screen printing, injection moulding, transfer or by compression. Such an encapsulation layer 6 advantageously makes it possible to improve the mechanical robustness and the reliability of the electronic system S.

(42) With reference to FIG. 1G, a step of separating the systems S from the sacrificial element 2 is represented. The separation step depends on the nature of the sacrificial element 2. For this purpose, the separation step may be carried out by dissolution or etching, by sliding or by deactivating the sacrificial element 2 by means of a laser, UV or by heating it as in the case of “Revalpha”® from Nitto. In this example, the assembly is heated to a temperature comprised between 120° C. and 250° C. as a function of the sacrificial element 2 used, which does not damage the system S.

(43) With reference to FIG. 1H, in order to enable a making integral by flipping, the system S comprises conductive balls 150 made integral with the lower connection ports 71 of the system S to connect to a printed circuit. Such conductive balls 150 are known to those skilled in the art under the designation “solder-balls” or “micro-bumps” and will not be described in detail. It goes without saying that the packaging could also be carried out without using conductive balls 150. For example, the system S could be in the form of a package of the QFN or LGA type comprising flat lower connection ports 71.

(44) With reference to FIG. 1I, a cutting step so as to separate the electronic systems S in order to be able to use them in an individual manner is represented. Electronic systems S are thus obtained which may be mounted on a circuit printed by different techniques. The mounting may be carried out with tin, alloys or conductive or insulating adhesives.

(45) Several other embodiments of an electronic system S according to the invention are represented with reference to FIGS. 3 to 11. For the sake of clarity and concision, identical or analogous elements between the other embodiments are referenced with the same numerical reference, only differences between the embodiments are described in detail.

(46) With reference to FIG. 3, in order to form the input/output pads of the system S, the system S comprises a preliminary passivation layer 400 which is applied on the sacrificial element 2 before the production of the lower redistribution layer 7. After separation of the sacrificial element 2, openings are formed in the lower surface of the system S so as to reach the lower connection ports 71 of the redistribution layer 7. This advantageously enables the mounting of conductive balls 150 in the preliminary passivation layer 400 in contact with the lower connection ports 71. A system S comprising conductive balls 150 but of which the thickness is reduced is thus obtained.

(47) With reference to FIG. 4, as a function of the needs, a third passivation layer 4″ may be applied after the production of the interconnections 5 and before the encapsulation step. With reference to FIG. 5, as a function of the complexity, the steps of depositing passivation layers 4′, 4″ and of depositing the three-dimensional interconnections 5, 5′ may be repeated to respond to the need for integration of systems S with high density on interconnects. In other words, superimposed redistribution layers are formed to enable complex connections between a large number of connectors 30 and a large number of lower connection ports 71. This is particularly advantageous for routing a very large number of inputs/outputs, to integrate separately the supply layers or to integrate a shield protecting the circuit from electromagnetic and electrostatic interferences, etc. By repeating the steps of passivation and of production of interconnections 5, it becomes possible to produce a system S comprising several metal layers or a system comprising electronic components 3 of same size which are stacked vertically.

(48) With reference to FIG. 6, when one of the electronic components 3 has a sensor function, an opening 60 is produced in the system S in order that the front face 3A of the electronic component 3, having a sensor function, is uncovered. This opening 60 may be created during the encapsulation step, in particular by “transfer moulding” or after encapsulation by locally etching the encapsulation layer or by means of other techniques known to those skilled in the art.

(49) With reference to FIGS. 7 to 8, the electronic system S comprises at least one additional electronic member XI, for example a component of the “Surface Mounted Component” type, which may be positioned in the system S after the production of the three-dimensional interconnections 5 (FIG. 7) or before the production of the three-dimensional interconnections 5 (FIG. 8). The additional electronic member XI is thus arranged beside the stack of electronic components 3. Losses are then reduced. When the additional electronic member XI is made integral before the production of the three-dimensional interconnections 5, it is the three-dimensional interconnections 5 which make it possible to produce the connection, which limits the number of steps of manufacturing the system S.

(50) With reference to FIG. 9, instead of an additional electronic member XI mounted beside the electronic component(s) 3, the electronic system S comprises one or more passive three-dimensional components X2 which are, preferably, produced simultaneously with the three-dimensional interconnections 5. Losses are then reduced and manufacture is rapid and easy.

(51) According to an aspect of the invention, not represented, the electronic component 3 comprises built-up conductive pads transferred onto the connectors 30 of said electronic component 3. Such built-up pads make it possible to offset vertically the connectors 30 with respect to the front surface 3A of the electronic component 3. In other words, the conductive pads extend vertically projecting from the front surface 3A of the electronic component 3. Such built-up pads make it possible to improve the compatibility with the interconnections 5 or to offset the position of the connectors 30 in order to limit the risk of interference between the three-dimensional interconnections 5 and the electronic component 3. In a preferred manner, the transferred built-up pads are formed prior to the step of producing three-dimensional interconnections. Advantageously, the built-up pads make it possible to make the three-dimensional interconnections 5 compatible with the connectors 30 of the electronic component 3 by forming a compatible metal interface.

(52) With reference to FIG. 10, a system is represented comprising an upper redistribution layer 7′ created on one or more electronic components 3 of the system S so as to enable the mounting of additional electronic components on the upper face of the system S. In a preferred manner, the upper redistribution layer 7′ is planar and produced during the same production step as the plurality of three-dimensional interconnections 5 such as described previously. With reference to FIG. 10, the system S comprises an upper redistribution layer 7′ created above electronic components 3 on which are mounted a first electronic component X3 through conductive balls 150′ and a second electronic component X4 through wire-bonds. Thus, a mixed vertical integration may be achieved, which offers great design flexibility. It goes without saying that the additional electronic components may be protected by an encapsulation layer, which offers a mechanical and chemical protection of said additional components. This encapsulation may be carried out at the same time as the deposition of the encapsulation layer 6 of the system S or in a separate manner after encapsulation of said system S.

(53) With reference to FIG. 11, a system S may be produced comprising a plurality of sub-systems SS1, SS2 separated by one or more built-up redistribution layers 7″. The built-up redistribution layer 7″ is created between a lower sub-system SS1 comprising one or more electronic components 3 and an upper sub-system SS2 comprising one or more electronic components 3. Advantageously, the built-up redistribution layer 7″ makes it possible to form an electronic system S comprising a stack of sub-systems SS1, SS2 each comprising a stack of electronic components 3 as described previously. Advantageously, the built-up redistribution layer 7″ fulfils the function of the lower redistribution layer 7 when it is wished to form an upper sub-system SS2 on a lower sub-system SS1. In other words, the lower sub-system SS 1 is formed as taught previously with reference to FIG. 1 then the built-up redistribution layer 7″ is formed and the upper sub-system SS2 is formed using the built-up redistribution layer 7″ instead of the lower redistribution layer 7. An electronic system S is thus formed in so called “Build-up”. The built-up redistribution layer 7″ may be produced in one or more steps. In this example, it is produced in a first step of producing three-dimensional interconnections and a second step of producing a planar redistribution layer. Preferably, the built-up redistribution layer 7″ is larger than the surface of the highest electronic component 3 of the lower sub-system SS1 so as to cooperate in an optimal manner with the lowest electronic component of the upper sub-system SS2. The built-up redistribution layer 7″ advantageously makes it possible to form the link between the strata. In a preferred manner and according to the need of the system, a passivation layer is deposited below and/or above the built-up redistribution layer 7″. Openings are produced in this layer to ensure the electrical connections between the three-dimensional interconnections 5 and the built-up redistribution layer 7″.

(54) With reference to FIG. 12, the electronic system S may be connected to a printed circuit 9 by connecting the conductive balls 150 on the tracks of the printed circuit 9. The presence of a lower redistribution layer 7 advantageously makes it possible to offer great freedom for the positioning of the conductive balls 150 in order to adapt to all the constraints of the printed circuit 9.

(55) Thanks to the invention, electronic systems S enabling a heterogeneous and three-dimensional integration may be produced. This type of integration enables considerable miniaturisation and an improvement in the performances of the systems S without using complex technologies such as that of through vias.

(56) Advantageously, the manufacturing method only necessitates a small number 10 of technological steps making it possible to produce several electronic systems S simultaneously, which reduces the manufacture time and cost.

(57) This method enables great design flexibility. Furthermore, the topology may be optimised to improve the electrical and thermal performances and to respond to the needs of applications having a large number of inputs/outputs and/or integrating sensors. The three-dimensional integration, by use of a same metallisation layer or by integrating several metal layers, makes it possible to obtain optimal miniaturisation without degrading the functions.

(58) The different exemplary embodiments have been described for electronic components being in the form of electronic chips. Nevertheless, it is recalled that other types of electronic components could be suitable.