METHOD FOR PRODUCING A CIRCUIT CARRIER, CIRCUIT CARRIER, METHOD FOR PRODUCING A SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE

Abstract

One aspect relates to a method for producing a circuit carrier for a semiconductor component. At least one first copper layer or one first copper-alloy layer with a first coefficient of expansion and at least one second layer made from a second material of low expandability with a second coefficient of expansion, which is smaller than the first coefficient of expansion, are bonded to one another by means of a low-temperature sintering method at a bonding temperature of 150° C. to 300° C.

Claims

1-18. (canceled)

19. A method for producing a circuit carrier for a semiconductor component, comprising: bonding together at least one first copper layer or one first copper-alloy layer with a first coefficient of expansion and at least one second layer made from a second material of low expandability with a second coefficient of expansion, which is smaller than the first coefficient of expansion; wherein the layers are bonded to one another by means of a low-temperature sintering method, at a bonding temperature of 150° C.-300° C.

20. The method of claim 19, further comprising forming at least one first bonding layer, made from a bonding material, between the first copper layer or the first copper-alloy layer and the second layer, wherein the bonding material produces a bond that withstands temperatures above the bonding temperature and has a diffusion metal comprising one of a group comprising silver (Ag), a silver alloy, gold (Au), a gold alloy, copper (Cu), and a copper alloy.

21. The method of claim 19, wherein the bonding temperature is between 240° C.-260° C., wherein the bonding temperature essentially corresponds to a mounting temperature during the bonding of the circuit carrier produced to at least one semiconductor component.

22. The method of claim 19, wherein the second material comprises one of a group comprising a nickel alloy, Invar (Fe.sub.65Ni.sub.35), Invar 36 (Fe.sub.64Ni.sub.36), Kovar (Fe.sub.54Ni.sub.29Co.sub.17), tungsten (W), an iron-nickel-cobalt alloy (FeNiCo alloy), and molybdenum (Mo).

23. The method of claim 19, wherein the bonding of the copper layer or the copper-alloy layer to the second layer and the bonding layer takes place by means of the application of pressure between 10 MPa-28 MPa.

24. A circuit carrier for a semiconductor component, comprising: at least one first copper layer or a first copper-alloy layer with a first coefficient of expansion, and at least one second layer made from a second material of low expandability with a second coefficient of expansion which is smaller than the first coefficient of expansion, the second layer bonded to the at least one first copper layer or one first copper-alloy layer; wherein the second material comprises one of a group comprising a nickel alloy, Invar (Fe.sub.65Ni.sub.35), Invar 36 (Fe.sub.64Ni.sub.36), Kovar (Fe.sub.54Ni.sub.29Co.sub.17), tungsten (W), an iron-nickel-cobalt alloy (FeNiCo alloy), and molybdenum (Mo).

25. The circuit carrier of claim 24, wherein at least one first bonding layer is formed between the first copper layer or the first copper-alloy layer and the second layer, and wherein the at least one first bonding layer comprises a diffusion metal comprising one of a group comprising silver (Ag), a silver alloy, gold (Au), a gold alloy, copper (Cu), and a copper alloy.

26. The circuit carrier of claim 25, wherein at least the first bonding layer is formed as a boundary layer of the first copper layer or the first copper-alloy layer and at least the second layer.

27. The circuit carrier of claim 24, wherein at least one second copper layer or a second copper-alloy layer, which is bonded by means of a second bonding layer comprising a bonding material, to the second layer comprising the second material of low expandability.

28. The circuit carrier of claim 24, wherein the second layer is embedded in a copper layer or a copper-alloy layer.

29. The circuit carrier of claim 24, wherein the second layer is formed in one of a frame-like, grid-like, and wire-like manner.

30. A method for producing a semiconductor module, comprising: providing a circuit carrier comprising: bonding together at least one first copper layer or one first copper-alloy layer with a first coefficient of expansion and at least one second layer made from a second material of low expandability with a second coefficient of expansion, which is smaller than the first coefficient of expansion; wherein the layers are bonded to one another by means of a low-temperature sintering method, at a bonding temperature of 150° C.-300° C.; providing at least one semiconductor component that is bonded to the circuit carrier; bonding the semiconductor component by means of a contacting layer to the circuit carrier at a mounting temperature of 150° C.-300° C.; wherein the mounting temperature substantially corresponds to the bonding temperature during the bonding of the layers of the circuit carrier.

31. The method of claim 30, wherein the bonding of the layers of the circuit carrier and the bonding of the circuit carrier to the semiconductor component take place simultaneously.

32. The method of claim 30, wherein the mounting temperature is between 240° C.-260° C.

33. A semiconductor module, comprising a circuit carrier, comprising: at least one first copper layer or a first copper-alloy layer with a first coefficient of expansion, and at least one second layer made from a second material of low expandability with a second coefficient of expansion which is smaller than the first coefficient of expansion, the second layer bonded to the at least one first copper layer or one first copper-alloy layer; wherein the second material comprises one of a group comprising a nickel alloy, Invar (Fe.sub.65Ni.sub.35), Invar 36 (Fe.sub.64Ni.sub.36), Kovar (Fe.sub.54Ni.sub.29Co.sub.17), tungsten (W), an iron-nickel-cobalt alloy (FeNiCo alloy), and molybdenum (Mo); and at least one semiconductor component comprising one of a diode, an IGBT, and a MOSFET transistor that is bonded to the circuit carrier.

34. The semiconductor module of claim 33, wherein the second layer is embedded in a copper layer or a copper-alloy layer, and wherein the semiconductor component is constructed above the second layer.

35. The semiconductor module of claim 33, wherein the second layer is embedded in a copper layer or a copper-alloy layer, wherein the second layer is constructed in a frame-like manner and frames a copper-layer section or a copper-alloy-layer section, and wherein the semiconductor component is constructed above the copper-layer section or copper-alloy-layer section.

36. The semiconductor module of claim 35, wherein edge lengths of the copper-layer section or the copper-alloy-layer section are at most 150% of edge lengths of the semiconductor component and the width of the second layer of frame-like construction is 10%-100% of the shortest edge length of the semiconductor component.

Description

[0067] The invention is explained in more detail in the following with further details and with reference to the attached schematic drawings on the basis of exemplary embodiments. In the figures:

[0068] FIG. 1a shows the arrangement of individual layers of a circuit carrier;

[0069] FIG. 1b shows a circuit carrier according to FIG. 1a in the bonded state;

[0070] FIG. 2 shows a semiconductor module according to a first exemplary embodiment;

[0071] FIG. 3 shows a semiconductor module according to a second exemplary embodiment;

[0072] FIG. 4 shows a semiconductor module according to a third exemplary embodiment;

[0073] FIG. 5 shows a semiconductor module according to a fourth exemplary embodiment;

[0074] FIG. 6 shows a semiconductor module according to a fifth exemplary embodiment; and

[0075] FIG. 7 shows a semiconductor module according to a sixth exemplary embodiment.

[0076] In the following, the same reference numerals are used for the same parts and parts with the same action.

[0077] The individual layers of a circuit carrier 10 (see FIG. 1b) to be produced are illustrated in FIG. 1a. Consequently, the circuit carrier 10 to be produced comprises a first layer 20 made from copper, a second layer 30 made from a second material M2 and a second copper layer 25.

[0078] The material M2 is a material of low expandability with a second coefficient of expansion, which is lower than the coefficient of expansion of copper. The second material M2 may be a nickel alloy, particularly Invar (Fe.sub.65Ni.sub.35) or Invar 36 (Fe.sub.64Ni.sub.36) or Kovar (Fe.sub.54Ni.sub.29Co.sub.17), and/or tungsten (W) and/or an iron-nickel-cobalt alloy (FeNi Co alloy).

[0079] In the present exemplary embodiment the material M2 is molybdenum.

[0080] A first bonding layer 40 made from a bonding material VM is formed between the first copper layer 20 and the second layer 30. A second bonding layer 41 made from the bonding material VM is formed between the second layer 30 and the second copper layer 25. The bonding material VM of the bonding layers 40 and 41 creates a bond between the layers 20, 25 and 30, which withstands temperatures above a bonding temperature. The bonding layer preferably has diffusion material, particularly silver and/or a silver alloy and/or gold and/or a gold alloy and/or copper and/or a copper alloy.

[0081] The bonding layer is preferably formed as a sinter layer, particularly as a sinter paste. This sinter paste, which preferably has one of the listed diffusion metals, can for example be applied by means of a printing method.

[0082] Preferably, the layers 20, 25, 30, 40 and 41 are bonded to one another by means of a low-temperature sintering method at a bonding temperature of 150° C.-300° C. The bonding temperature is particularly preferably 250° C. The bonding temperature for bonding the layers 20, 25 and 30 with the aid of the bonding layers 40 and 41 substantially corresponds to the mounting temperature during the bonding of the circuit carrier 10 produced to a semiconductor component which is to be applied.

[0083] The bonding of the first copper layer 20 to the second layer 30 and to the second copper layer 25 preferably takes place by means of pressure loading, particularly with a pressure of 5 MPa-30 MPa, particularly of 25 MPa.

[0084] The circuit carrier 10 produced can be seen in FIG. 1b. The bonding layers 40 and 41 can be seen in the same. It is possible that the bonding layers 40 and 41 are formed as boundary layers of the first copper layer 20, the second copper layer 25 and the second layer 30.

[0085] As can be seen in FIGS. 1a and 1b, the layer thicknesses d1 of the first copper layer 20, d2 of the second layer 30 and d3 of the second copper layer 25 are the same. With the aid of the axis of symmetry S drawn in FIG. 1b it becomes clear that the structure of the circuit carrier 10 is a symmetrical structure of the individual layers 20, 25 and 30 and the bonding layers 40 and 41. The axis of symmetry S halves the total thickness D of the circuit carrier 10. The total thickness D is formed by means of the addition of the layer thicknesses d1, d2 and d3 and the layer thicknesses of the bonding layers 40, 41. A symmetrical structure of the circuit carrier 10 is shown above and below the axis of symmetry S.

[0086] In a preferred embodiment, the layer thickness d1 of the first copper layer 20 is 0.5 mm-3.0 mm, the layer thickness d2 of the second layer 30 is 0.1 mm-1.0 mm and the layer thickness d3 of the second copper layer 25 is 0.5 mm-3.0 mm. The thicknesses of the first bonding layer and second bonding layer are preferably 1 μm-50 μm.

[0087] A semiconductor module 100 is illustrated in FIG. 2. The semiconductor module 100 comprises a semiconductor component 90 and a circuit carrier 10. The semiconductor component 90 may for example be a diode or an IGBT or a MOSFET transistor. The semiconductor component 90 is bonded to the circuit carrier 10 by means of a contacting layer 50. The contacting layer 50 may for example be a solder layer or an electrically conductive adhesive layer or a sinter layer.

[0088] The illustrated circuit carrier 10 consists of a first copper layer 20 and a second layer 30 made from a second material M2. The second material M2 is molybdenum. The first layer 20 is bonded to the second layer 30 by means of a bonding layer 40, which consists of bonding material VM.

[0089] The semiconductor component 90 is applied onto the side 15 of the circuit carrier 10 facing the semiconductor component 90 with the aid of the contacting layer 50. The surface 15 of the circuit carrier 10 to be bonded to the semiconductor component 90 is the first side 15 of the first copper layer 20, wherein the first side 15 of the copper layer 20 is formed facing away from the second layer 30.

[0090] The indicated axis of symmetry S shows that in the embodiment according to FIG. 2, an asymmetric arrangement of the layers 20, 30 and 40 is present. The layer thickness d1 of the first copper layer 20 is larger than the layer thickness d2 of the second layer 30.

[0091] A semiconductor module 100 according to a second exemplary embodiment is illustrated in FIG. 3. The circuit carrier 10 of FIG. 3 is the circuit carrier 10 illustrated in FIG. 1b, that is to say a circuit carrier 10 with symmetrical arrangement. Also, in this embodiment the semiconductor component 90 is applied on the first side 15 of the first copper layer 20 by means of a contacting layer 50.

[0092] A further exemplary embodiment with regards to a circuit carrier 10 of a semiconductor module 100 according to the invention is illustrated in FIG. 4. Consequently, the second layer 30 made from a second material M2, particularly from molybdenum, is embedded into the second copper layer 25. Both the width b2 of the second layer 30 and the thickness d2 of the second layer 30 are lower than the width b3 of the second copper layer will 25 and the thickness d3 of the second copper layer 25. The semiconductor component 90 is mounted on the circuit carrier 10 above the second layer 30. The width b2 of the second layer is slightly smaller in this case than the width bHL of the semiconductor component 90.

[0093] The circuit carrier 10 comprises a first copper layer 20, which is arranged in certain sections above the second copper layer 25 and above the second layer 30. To bond the first copper layer 20 to the second copper layer 30, a bonding layer 40 made from bonding material VM is formed between the first copper layer 20 and the second layer 30 made from second material. M2.

[0094] As the layer thickness d2 of the second layer 30 is lower than the layer thickness d3 of the second copper layer 25, the first bonding layer 40 can be introduced for example by means of a doctor blade into the recess formed owing to the different layer thicknesses d2 and d3. Preferably, the first copper layer 20 is a copper conducting path.

[0095] A method according to the invention for producing the circuit carrier 10 or the semiconductor module 100 first provides that the second layer 30 is bonded to the first copper layer 20 for example by means of a low-temperature sintering method. Owing to the asymmetric structure of the circuit carrier 10, a deformation occurs first upon cooling of the circuit carrier 10 to room temperature. If the semiconductor element 90 is then mounted on the circuit carrier 10 in a second work step, particularly by means of sintering, diffusion soldering or adhesive bonding, a mechanical stress equalization occurs which in turn leads to a flat conducting path shape.

[0096] This type of stress-equalized bonding can also take place in one process step. To this end, the first copper layer 20, particularly the copper conducting path, is positioned onto the second layer 30, which is embedded into the second copper layer 25, and in turn the semiconductor component 90 is positioned thereon. The bonding layer 40 is located between the first copper layer 20 and the second layer 30 made from a second material. M2 and the contacting layer 50 is located between the semiconductor component 90 and the first copper layer 20. Preferably, both the contacting layer 50 and the first bonding layer 40 are a silver sinter layer, so that all layers and the semiconductor component 90 can be bonded to one another in a single process step.

[0097] A similar embodiment of a semiconductor module 100 compared to FIG. 4 is illustrated in FIG. 5. In this case also, the second layer 30 is embedded into the second copper layer 25. The first copper layer 20 is formed between the semiconductor component 90 and the second layer 30. Furthermore, a third copper layer 26 is formed. The second copper layer 25 and the second layer 30 are bonded to the third copper layer 26 by means of a second bonding layer 41 made from bonding material VM.

[0098] Overall, the area of the second layer 30 made from material of low expandability, such as e.g. molybdenum, is substantially smaller than the areas of the second copper layer 25 and the third copper layer 26. The reduction in the area of the second layer 30 is not less than 80% of the area of the semiconductor component 90 however. In the example illustrated according to FIG. 5, the area of the second layer 30, as is indicated by the width b2 of the second layer, is larger than the area of the semiconductor component 90. The area of the second layer 30 preferably has the same side ratio as the semiconductor component 90. The reduction in the area of the second layer 30 made from material of low expandability compared to the areas of the second copper layer 25 and the third copper layer 26 reduces the expansion maladjustment in a concentrated and local manner in the region of the low-expanding semiconductor component 90.

[0099] The first copper layer 20 covers the second layer 30 completely. In the case of a pressing bonding technology, a contour-following first copper layer 20 can be formed owing to an applied mounting pressure. In this case, a plateau may be formed, which carries the semiconductor component 90.

[0100] A further semiconductor component 100 with a further embodiment with regards to a circuit carrier 10 according to the invention is illustrated in FIG. 6. The second layer 30 of the circuit carrier 10 is formed as a rectangular frame in this exemplary embodiment. The second layer 30 made from material of low expandability and formed as a rectangular frame is embedded into the second copper layer 25. The second layer 30 is bonded to the first copper layer 20 by means of a first bonding layer 40 made from bonding material VM. The first copper layer 20 is also formed as a rectangular frame. The second layer 30 frames a copper-layer section 29, wherein the semiconductor component 90 is formed above the copper-layer section 29. At most, the edge lengths of the copper-layer section 29 should be 150% of the edge lengths of the semiconductor component 90. The width b2 of the second layer 30 of frame-like construction is at least 10% and at most 100% of the smallest edge length of the semiconductor component 90.

[0101] The circuit carrier 10 furthermore has a third copper layer 26. This third copper layer 26 is bonded to the second layer 30 and the second copper layer 25 by means of a second bonding layer 41.

[0102] The frame-like design of the second layer 30 effects an expansion reduction, wherein the copper-layer section 29, on which the semiconductor component 90 is applied by means of a contacting layer 50, effects a maximum z thermal conductivity owing to the copper material. The thermal conductivity starting from the semiconductor component 90 in the direction of the third copper layer 26 is defined as z thermal conductivity. A contour-following copper layer can be formed on the basis of a pressing bonding technology, such as e.g. on the basis of a sintering method, owing to the mounting pressure. The second layer 30 covered with the first copper layer 20 in this case forms a flat plateau lowered in the direction of the copper-layer section 29, which plateau carries the semiconductor component 90.

[0103] The circuit carrier 10 of the semiconductor module 100 of FIG. 7 likewise has a first copper layer 20, a second copper layer 25 and a third copper layer 26. The second layer 30 is embedded into the second copper layer 25. The first copper layer 20 is of square or rectangular construction and covers the second layer 30. The first copper layer 20 is bonded to the second layer 30 by means of a first bonding layer 40 made from bonding material VM and of frame-like construction. The second copper layer 25 is in turn bonded to the third copper layer 26 using a second bonding layer 41.

[0104] The extent or the size of the area of the second layer 30 made from material M2 of low expandability is in this exemplary embodiment limited to a shape adapted to the distribution of the mechanical shear stress between the semiconductor component 90 and the circuit carrier 10. The shear stress is particularly large between the semiconductor component 90 and the circuit carrier 10 along the diagonals (and beyond) of the semiconductor component 90. The shear stress distribution is substantially point-symmetrical to the centre point M of the semiconductor component 90.

[0105] A minimum possible design in this case with regards to the area of the second layer 30 therefore results in an area which extends somewhat beyond the diagonals of the semiconductor component 90. The area of the second layer 30 extends further beyond the diagonals than in the region of the coordinate axes of the semiconductor component 90. The resultant surface form (which would be visible in a plan view onto the second layer 30) is similar to a four leaf clover. To improve the thermal conductivity, a copper-layer section 29 can be formed in the second layer 30 in the region of the centre point M of the semiconductor component 90.