Mold heel crack problem reduction

Abstract

A semiconductor package is provided which addresses problems of mold cap heel cracking. The package may made by using a cavity die and a gate insertion tool. The gate insertion tool, which fits into the cavity die, has an elongated body and includes a nozzle head with an edge which is contoured in relation to a mold cap formed on a substrate. The edge defines a curved border, for the mold cap, from a plane above the substrate to a plane lying on the substrate. The nozzle head includes a slot, for admitting a cull runner tip, centered on an axis of the elongated body.

Claims

1. A semiconductor package, comprising: a substrate; a semiconductor die attached to, and electrically connected to the substrate; and a mold compound covering the semiconductor die; the mold compound contacting the substrate at an edge of the mold compound, wherein the edge includes a shape of an inverted Sigmoid function curve in a cross-sectional view of the semiconductor package.

2. The semiconductor package of claim 1, wherein the substrate includes a plurality of conductive traces on a top surface, and a plurality of electrical contacts on a bottom surface.

3. The semiconductor package of claim 2, wherein the plurality of electrical contacts is attached to a printed circuit board.

4. The semiconductor package of claim 1, wherein the semiconductor package is a plastic ball grid array (PBGA) package.

5. The semiconductor package of claim 1, wherein the semiconductor die is electrically connected to the substrate via a wire bond.

6. The semiconductor package of claim 1, wherein the edge is a contoured edge in the cross-sectional view of the semiconductor package.

7. A semiconductor package, comprising: a substrate; a semiconductor die attached to, and electrically connected to the substrate; and a mold compound covering the semiconductor die; the mold compound including a chamfered side from a cross-sectional view of the semiconductor package, wherein an end of the chamfered side substantially including a shape according to a function y=1/(1+e.sup.x), wherein y is along a height of the mold compound from the cross-sectional view, and x is along a length of the mold compound in the cross-sectional view.

8. The semiconductor package of claim 7, wherein the shape includes an inverted Sigmoid function curve.

9. The semiconductor package of claim 7, wherein the end of the chamfered side is closer to the substrate than a top surface of the mold compound.

10. The semiconductor package of claim 7, wherein the substrate includes a plurality of conductive traces on a top surface, and a plurality of electrical contacts on a bottom surface.

11. The semiconductor package of claim 10, wherein the plurality of electrical contacts is attached to a printed circuit board.

12. The semiconductor package of claim 7, wherein the semiconductor package is a plastic ball grid array (PBGA) package.

13. The semiconductor package of claim 7, wherein the semiconductor die is electrically connected to the substrate via a wire bond.

14. The semiconductor package of claim 7, wherein the end is a contoured end from the cross-sectional view of the semiconductor package.

15. The semiconductor package of claim 7, wherein the end includes a beveled from in the cross-sectional view of the semiconductor package.

16. The semiconductor package of claim 7, wherein the cross-sectional view of the semiconductor package is a cross-sectional side view of the semiconductor package.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a more complete understanding of the present disclosure, the objects and advantages thereof, reference is now made to the ensuing descriptions taken in connection with the accompanying drawings briefly described as follows:

(2) FIG. 1a illustrates a perspective drawing showing a top mold tool, a bottom mold tool and cavity die (with an exploded view).

(3) FIG. 1b is a plan view illustrating the layout of cavity die.

(4) FIG. 1c illustrates a cross-sectional view of a portion of a creased mold cap over a substrate.

(5) FIG. 2 is a drawing illustrating a cross-section view of a PBGA structure juxtaposed under a perspective view of its associated cavity die.

(6) FIG. 3a illustrates a cross-sectional drawing further showing the problem which may occur with a creased mold cap at an edge.

(7) FIG. 3b illustrates a scan, from a scanning electron microscope (SEM), showing a cap mold wall a of creased mold cap and the cavity die clamping edge resulting from where a creased mold cap insert tool engages the substrate.

(8) FIG. 3c illustrates a plan view showing the location of a gold gate relative a top mold tool having a mold insert port for receiving a gate insert tool during formation of a cap mold.

(9) FIG. 4 illustrates SEM image showing a perspective view of a semiconductor package.

(10) FIG. 5a illustrates a top perspective view of a creased mold cap, near a gold gate, having a sharp edge with respect to a substrate.

(11) FIG. 5b illustrates a raised elevation view of a creased mold cap having a sharp edge which may likely result in a mold heel crack, in a mold heel, which lies on either side of a gold gate.

(12) FIG. 5c illustrates a side view of creased mold cap clearly showing a sharp edge which may result in a mold heel crack in a mold heel.

(13) FIG. 6a illustrates a cross-sectional view of system elements for forming a mold cap over a gate.

(14) FIG. 6b illustrates a cross-sectional view of the system for forming a mold cap over a gate, as shown in FIG. 6a, along with a mold compound which has been injected into (and filling a portion of) cavity.

(15) FIG. 7a illustrates a perspective view of gate insert tool which provides a mold cap of the desired profile according to the foregoing.

(16) FIG. 7b illustrates a perspective view of a nozzle head, magnifying a portion of FIG. 7a.

(17) FIG. 7c illustrates a graph of an inverted Sigmoid function according to the equation y=1/(1+e.sup.x).

(18) FIG. 8a illustrates a cross-sectional view of a magnified portion of FIG. 6b.

(19) FIG. 8b illustrates an elevated perspective view of mold cap with mold cap edge having a chamfered contour.

(20) FIG. 8c illustrates an SEM image of an elevated cross-sectional view of a gate insert tool from a direction from a cull runner insert toward a gold gate (as shown in FIG. 8a).

(21) FIG. 9 illustrates a cross-sectional view of a PBGA structure as described herein.

(22) Applicable reference numerals have been carried forward.

DETAILED DESCRIPTION

(23) A solution to mold heel cracks made by a cavity die lies in eliminating the sharp corner which may exist on either side of a gold gate. The sharp corners may be eliminated in connection with inserting a gate insert tool having a profile that will contour the edge of a mold cap. By smoothing the mold heel of a mold cap, a mold heel crack has a much less likely chance of occurring, especially in connection with a high temperature reflow process for the solder balls of the semiconductor package.

(24) FIG. 6a illustrates a cross-sectional view of system elements for forming a mold cap over a gate. Gate insert tool 602 is shown in-place abutting an outer edge of cavity die 102 from an array of dies (not shown) coupled to top mold tool 100. Cull runner insert 603, of cull runner 604, fits between gold gate 340 and gate insert tool 602 while gate insert tool 602 is in-place against cavity die 102. Mold compound (not shown) may be pumped, using plunger 605, along path 606 through cull runner 604, into cavity 103 lying within cavity die 102 and bordered by bottom mold tool 101.

(25) FIG. 6b illustrates the side view of the system for forming a mold cap over a gate, as shown in FIG. 6a, along with mold compound 622 within (and filling a portion of) cavity 103. Gate insert tool 602 removably abuts cavity die 102.

(26) FIG. 7a illustrates a perspective view of gate insert tool 602 which provides a mold cap of the desired profile according to the foregoing. Gate insert tool 602 includes nozzle head 702 having a chamfered contour 704.

(27) FIG. 7b illustrates a perspective view of nozzle head 702, magnifying a portion of FIG. 7a. Cull runner insert 603, as shown in FIG. 6b, may be inserted into nozzle head 702 along line A-A′.

(28) FIG. 7c illustrates a graph of an inverted Sigmoid function according to the equation y=1/(1+e.sup.x). The shape of the inverted Sigmoid function provides one smoothed contour outlining the shape produced by chamfered contour 704 that will produce a mold cap of a suitable profile which is less prone to mold heel cracks.

(29) FIGS. 8a through 8c provide additional views of the gate insert tool and the resulting mold cap according to the foregoing.

(30) FIG. 8a illustrates a magnified portion of FIG. 6b. Mold cap edge 634 presents a chamfered contour which outlines the shape of an inverted Sigmoid function on mold cap 802. Likewise, gate insert tool 602 which abuts mold cap edge 634, produces mold cap edge 634 which approximately outlines the shape of an inverted Sigmoid function.

(31) FIG. 8b illustrates an SEM image of an elevated cross-sectional view an example of gate insert tool 602. Cull runner insert 603 is shown inserted into nozzle head 702 along line A-A′.

(32) FIG. 8c illustrates a SEM image showing a perspective view of mold cap 802 having mold cap edge 634 which approximately outlines the shape of an inverted Sigmoid function.

(33) Gate insert tool 602, as shown in the foregoing drawing figures, may be used to engage an epoxy overmold overlying a die, and collapse solder balls 213 (as shown in FIG. 2) in connection with pressure applied by top mold tool 100 during solder reflow to join each PBGA 217 to PCB 120 (FIG. 2). As shown in FIG. 8a, the contoured edge of gate insert tool 602 helps ensure stress-reduced corners around mold cap 802, which may be made of an epoxy overmold.

(34) FIG. 9 illustrates a cross-sectional view of a PBGA structure 900 according to the foregoing. Mold cap edge 634, of mold cap 802, is shown which approximately outlines the shape of an inverted Sigmoid function.

(35) Once the mold cap has been formed on each cavity die 102 (as shown in FIG. 1) according to the gate insert tool disclosed herein, a pick and place machine (not shown) may be used to mount a semiconductor package to a PCB. Pick and place machines ensure component body alignment, component solder ball alignment; and allow inspection of solder balls before placement. Alignment inspections may be done from the top of the PBGA package with the gold gate being used to mark the position of pin 1 of the semiconductor device and to ensure that the PBGA package is aligned with its proper position on the PC board.

(36) PBGA pick and place systems may include a computer vision system that recognizes and positions the component and a mechanical system which physically performs the pick and place operation. The PBGAs may be self-aligning during solder reflow. The computer vision system may be used to recognize and specify positioning of the PBGA package on the PCB.

(37) The foregoing has been described herein using specific embodiments for the purposes of illustration only. It will be readily apparent to one of ordinary skill in the art, however, that the principles herein can be embodied in other ways. Therefore, the foregoing should not be regarded as being limited in scope to the specific embodiments disclosed herein, but instead, as being fully commensurate in scope with the following claims.