Quantum wire resonant tunneling transistor

Abstract

A semiconductor transistor device includes an emitter region that includes a plurality of metal quantum wires and is connected to an emitter terminal, a base region that includes a plurality of metal quantum wires and is connected to a base terminal, a collector region comprising a plurality of metal quantum wires and is connected to a collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region.

Claims

1. A semiconductor transistor device, comprising: an emitter region comprising a plurality of metal quantum wires; a base region comprising a plurality of metal quantum wires; a collector region comprising a plurality of metal quantum wires; an emitter barrier region between the emitter region and the base region; and a collector barrier region between the collector region and the base region.

2. The semiconductor transistor device of claim 1, wherein the emitter region, the base region, and the collector region comprises a crystalline semiconductor that includes open channels in a crystal lattice, wherein the metal quantum wires are formed along the open channels of the crystalline semiconductor.

3. The semiconductor transistor device of claim 2, wherein the open channel direction is <110> direction for semiconductors with a diamond cubic lattice structure.

4. The semiconductor transistor device of claim 2, wherein the metal quantum wires in the emitter region, the base region, and the collector region are formed by ion implantation of metal ions respectively into the emitter region, the base region, and the collector region.

5. The semiconductor transistor device of claim 2, wherein the crystalline semiconductor is in the form of a semiconductor layer, wherein the metal quantum wires are disposed from a bottom surface of the layer to a top surface of the semiconductor layer.

6. The semiconductor transistor device of claim 5, further comprising: an emitter terminal connected to the emitter region; a base terminal connected to the base region; and a collector terminal connected to the collector region, wherein the metal quantum wires in the emitter region, the base region, and the collector region are respectively connected to the emitter terminal, the base terminal, and the collector terminal at the top surface of the semiconductor layer.

7. The semiconductor transistor device of claim 1, wherein the metal quantum wires have lengths shorter than 500 Å.

8. The semiconductor transistor device of claim 1, wherein the emitter region, the base region, and the collector region each includes a semiconductor in which the plurality of metal quantum wires are embedded.

9. The semiconductor transistor device of claim 8, wherein the semiconductor includes silicon, germanium, silicon germanium alloys, diamond, and III-V compound semiconductors.

10. The semiconductor transistor device of claim 1, wherein the plurality of metal quantum wires in the emitter region, the base region, or the collector region are substantially parallel to each other.

11. The semiconductor transistor device of claim 10, wherein the plurality of metal quantum wires in the emitter region, the base region, or the collector region are distributed periodically.

12. The semiconductor transistor device of claim 1, wherein the emitter barrier region or the collector barrier region has a width smaller than 100 Å.

13. The semiconductor transistor device of claim 1, wherein the base region is configured to produce a tunneling current through the emitter barrier region and the collector barrier region in response to a voltage applied to the base region.

14. The semiconductor transistor device of claim 1, wherein a Fermi level [work function] of the metal quantum wires is closer to the conduction band edge than to the valence band edge in at least one of the emitter barrier region or the collector barrier region, wherein a tunnel current between the emitter region and the collector region has electrons as majority carriers.

15. The semiconductor transistor device of claim 1, wherein a Fermi level [work function] of the metal quantum wires is closer to the valence band edge than to the conduction band edge in at least one of the emitter barrier region or the collector barrier region, wherein a tunnel current between the emitter region and the collector region has holes as majority carriers.

16. The semiconductor transistor device of claim 1, wherein the metal quantum wires in the emitter region, the base region, and the collector region are made of a same metal.

17. The semiconductor transistor device of claim 1, wherein the metal quantum wires in the emitter region, the base region, and the collector region are made of different metals.

18. The semiconductor transistor device of claim 1, wherein ground state energies in the metal quantum wires in the emitter region, the [emitter] base region, and the collector region have substantially a same value.

19. The semiconductor transistor device of claim 1, wherein ground state energies in the metal quantum wires in the emitter region, the [emitter] base region, and the collector region have different values.

20. A semiconductor transistor device, comprising: an emitter region comprising a plurality of metal quantum wires; a first base region comprising a plurality of metal quantum wires; a second base region comprising a plurality of metal quantum wires; a collector region comprising a plurality of metal quantum wires; an emitter barrier region between the emitter region and the first base region; an inter-base barrier region between the first base region and the second base region; and a collector barrier region between the collector region and the second base region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawing, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention:

(2) FIG. 1 shows the schematic drawing of a Quantum Wire Resonant Tunneling Transistor (QWRTT).

(3) FIG. 2a shows the band diagram of an n-type QWRTT.

(4) FIG. 2b shows the band diagram of a p-type QWRTT.

(5) FIG. 3a shows a silicon lattice structure viewed in the <110> direction.

(6) FIG. 3b shows the same silicon lattice structure after ion implantation.

(7) FIG. 4a shows the layer structure of an exemplary fabrication process at the step of ion implantation.

(8) FIG. 4b shows the layer structure of an exemplary fabrication process after a metal layer is patterned.

(9) FIG. 5 shows the ground state energy E.sub.1 vs. the number of quantum wires N of a superlattice structure.

(10) FIG. 6 shows transmission coefficient T vs. energy of an n-type QWRTT.

(11) FIG. 7 shows the electron and hole tunneling currents vs. V.sub.B of an n-type QWRTT.

(12) FIG. 8 shows the electron tunneling current vs. V.sub.C of an n-type QWRTT.

(13) FIG. 9 shows the hole and electron tunneling currents vs. V.sub.B of a p-type QWRTT.

(14) FIG. 10a shows the circuit diagram of a 2-input AND gate.

(15) FIG. 10b shows the circuit diagram of a 2-input OR gate.

(16) FIG. 11 shows a simplified structure of two stacked devices.

(17) FIG. 12 shows the electron tunneling current vs. V.sub.B of an n-type QWRTT with different N.sub.E and N.sub.C.

(18) FIG. 13 shows the electron tunneling current vs. V.sub.B of an n-type QWRTT with different qϕ.sub.bn,B.

DETAILED DESCRIPTION OF THE INVENTION

(19) Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

(20) Quantum Wire Resonant Tunneling Transistor (QWRTT) is a three-terminal device. FIG. 1 shows the schematic drawing of a QWRTT 100. The three terminals include emitter terminal 101, base terminal 102, and collector terminal 103. The device structure of the QWRTT 100 consists of emitter region 111, emitter barrier region 112, base region 113, collector barrier region 114, and collector region 115. The emitter region 111, base region 113, and collector region 115 each includes a semiconductor embedded with two or more metal quantum wires. The semiconductor in the emitter region 111, base region 113, and collector region 115 can be, for example, silicon, germanium, or silicon germanium alloys. The emitter barrier region 112 and collector barrier region 114 are made of one or more semiconductor materials such as silicon, germanium, silicon germanium alloys, diamond, or III-V compound semiconductors. The semiconductor can be undoped or lightly doped. W.sub.EB is the width of the emitter barrier region 112, and W.sub.CB is the width of the collector barrier region 114.

(21) The QWRTT has two complementary device types, i.e. n-type and p-type. The primary carriers are electrons in an n-type QWRTT, and holes in a p-type QWRTT. FIG. 2a shows the band diagram of an n-type QWRTT 200, and FIG. 2b shows the band diagram of a p-type QWRTT 210. The n-type QWRTT 200 and the p-type QWRTT 210 each includes the emitter region 201, emitter barrier region 202, base region 203, collector barrier region 204, and collector region 205. E.sub.C is the conduction band edge, and E.sub.V is the valence band edge of the semiconductor. E.sub.F is the Fermi level of the metal that forms the quantum wires. For an n-type device shown in FIG. 2a, E.sub.F is closer to E.sub.C than E.sub.V, the Schottky barrier height for electrons qϕ.sub.bn 206 is smaller than the Schottky barrier height for holes qϕ.sub.bp 207, and the primary carriers are electrons. While for a p-type device shown in FIG. 2b, E.sub.E is closer to E.sub.V than E.sub.C, qϕ.sub.bp 207 is smaller than qϕ.sub.bn 206, and the primary carriers are holes.

(22) Silicon has a diamond cubic lattice structure, which is a very open structure with an atomic packing factor of 0.34. FIG. 3a shows the silicon lattice structure viewed in the <110> direction. A honeycomb structure formed by silicon atoms 301 can be seen. The honeycomb structure has an array of hexagonal hollow cells 302. Each cell has a large opening at the center. The opening forms an open channel 303 in the ion implantation process. In the example of silicon, the open channels are oriented along the <110> direction and are substantially parallel to each other. If ions of light elements are implanted along the open channel direction, the ions will be steered along such open channels without encountering any target nuclei. The implant range can be much longer than other directions. This effect is called ion channeling. It is an undesirable effect for most semiconductor processes. However, this unfavorable ion channeling effect can be used to create quantum wires of atomic size. FIG. 3b shows the silicon lattice structure viewed in the <110> direction after ion implantation. Metal atoms 304 are embedded in the open channels 303 as shown in FIG. 3b. A quantum wire is formed when the metal atoms 304 in an open channel 303 are continuously distributed and electrically connected.

(23) An exemplary fabrication process to build the QWRTT is described below. FIG. 4a shows the layer structure at the step of ion implantation, and FIG. 4b shows the layer structure after a metal layer is patterned. The starting material is a silicon-on-insulator (SOI) (110) wafer 401. The wafer includes a top silicon layer 402 with a thickness of about 100 Å, a mid oxide layer 403, and a bottom silicon substrate 404. The top silicon layer 402 has a crystal lattice comprising open channels 303 (FIG. 3a). The thickness of the silicon layer 402 is generally less than 500 Å. A layer of SiO.sub.2 405 is deposited and patterned. SiO.sub.2 is used as a mask for ion implantation. Ions of metals with suitable work functions are implanted vertically to the silicon wafer in the <110> direction. If wafers with other crystal orientations are used, such as (100) and (111), then the implant angle needs to be tilted accordingly to the <110> direction. The implanted ions travel along the open channels 303 shown in FIG. 3b. The channels end at the silicon-oxide interface because silicon dioxide is amorphous. After the implantation, the open channels 303 (FIG. 3a) are filled with metal atoms and quantum wires 406 are formed. The implantation damages to the silicon lattice on the surface are removed by chemical etch. A metal layer 407 is deposited and patterned for interconnection.

(24) As shown in FIG. 4b, the emitter region 411, the base region 412, and the collector region 413 have metal quantum wires 406 embedded in a semiconductor 402. The emitter region 411 and the base region 412 are separated by the emitter barrier region 414. The collector region 413 and the base region 412 are separated by the collector barrier region 415. In some embodiments, the metal quantum wires 406 can be approximately perpendicular to the silicon layer 402. Thus, the lengths of the metal quantum wires 406 are generally shorter than 500 Å. The emitter region 411, the base region 412, and the collector region 413 can have the same or different numbers of metal quantum wires 406 along the emitter-base-collector direction. Moreover, the metal quantum wires 406 in the emitter region 411, the base region 412, and the collector region 413 can be formed by the same or different materials.

(25) The emitter/base/collector (E/B/C) regions 411-413 each can be considered as a superlattice, which is a periodic structure of metal and semiconductor. The electrons in a metal quantum wire are confined to a two-dimensional (2-D) potential well. Electrons can only have discrete energy values inside a potential well. The ground state energy E.sub.1 (shown in FIGS. 2a and 2b) is found to be a function of the potential barrier height and the superlattice size. FIG. 5 shows the ground state energy E.sub.1 for electrons as a function of the number of quantum wires N in a superlattice along the current flow direction (i.e., the emitter-base-collector direction). The potential barrier height qϕ.sub.bn is assumed to be 0.4 eV. The superlattice size is directly related to the number of quantum wires. E.sub.1 is smaller for a larger superlattice with more quantum wires.

(26) The device characteristics of a QWRTT can be obtained by solving the one-dimensional (1-D) time-independent Schrodinger equation

(27) $\begin{array}{cc}-\frac{{\eta }^2}{2m}\frac{d^2\psi \left(x\right)}{{\mathrm{dx}}^2}+U\left(x\right)\psi \left(x\right)=E\psi \left(x\right)& \left(1\right)\end{array}$
where ψ(x) is the wave function, U(x) is the potential energy, and E is the total energy. The general solution has the form
ψ(x)=A e.sup.iκx+Be.sup.−iκx  (2)
where κ is the wave number, and is given by

(28) $\begin{array}{cc}\frac{{\eta }^2{\kappa }^2}{2m}=E-U\left(x\right)& \left(3\right)\end{array}$
The tunneling probability or transmission coefficient T is given by

(29) $\begin{array}{cc}T={.Math.\frac{A_C}{A_E}.Math.}^2& \left(4\right)\end{array}$
where A.sub.C and A.sub.E are the coefficient A of the collector and emitter, respectively. According to Fermi's golden rule, the tunneling current from emitter to collector is proportional to the transmission coefficient multiplied by the occupied states in emitter and the unoccupied states in collector. The tunneling current from collector to emitter can be obtained correspondingly.

(30) $\begin{array}{cc}{I}_{E.fwdarw.C}\propto \frac{4\pi q}{\eta }\int T{\rho }_E{\rho }_C{F}_E\left(1-F_C\right)\mathrm{dE}& \left(5\right)\end{array}$

(31) $\begin{array}{cc}{I}_{C.fwdarw.E}\propto \frac{4\pi q}{\eta }\int T{\rho }_E{\rho }_C{F}_C\left(1-F_E\right)\mathrm{dE}& \left(6\right)\end{array}$
F.sub.E and F.sub.C are the Fermi-Dirac distribution functions in the emitter and collector, respectively. ρ.sub.E and ρ.sub.C are the densities of states in the emitter and collector, respectively. The density of states ρ of a 1-D metal quantum wire in a potential well is given below

(32) $\begin{array}{cc}\rho =\frac{1}{\mathrm{\pi \eta }}.Math.\sqrt{\frac{m}{2\left(E-E_1\right)}}& \left(7\right)\end{array}$
The net tunneling current I can be written as

(33) $\begin{array}{cc}I=I_{E.fwdarw.C}-I_{C.fwdarw.E}\propto \frac{4\pi q}{\eta }\int T{\rho }_E{\rho }_C\left(F_E-F_C\right)\mathrm{dE}& \left(8\right)\end{array}$

(34) If the E/B/C regions have the same superlattice structures (i.e., the numbers of quantum wires N and the metal work functions E.sub.F are the same in the E/B/C regions), then their E.sub.1 values are the same. E.sub.1 is said to be “in alignment” in the E/B/C regions. The number of quantum wires Nis denoted as N.sub.E, N.sub.B, and N.sub.C in the E/B/C regions, respectively. The ground state energy E.sub.1 is denoted as E.sub.1,E, E.sub.1,B, and E.sub.1,C in the E/B/C regions, respectively. The Schottky barrier height for electrons qϕ.sub.bn is denoted as qϕ.sub.bn,E, qϕ.sub.bn,B, and qϕ.sub.bn,C in the E/B/C regions, respectively. The Schottky barrier height for holes qϕ.sub.bp is denoted as qϕ.sub.bp,E, qϕ.sub.bp,B, and qϕ.sub.bp,C in the E/B/C regions, respectively.

(35) In some embodiments, the emitter region 111, base region 113, and collector region 115 each includes three metal quantum wires embedded in a semiconductor along the E-B-C direction. FIG. 6 shows the electron transmission coefficient T of an n-type QWRTT versus energy for N.sub.E=N.sub.B=N.sub.C=3, qϕ.sub.bn,E=qϕ.sub.bn,B=qϕ.sub.bn,C=0.4 eV, W.sub.EB=W.sub.CB=40 Å, and V.sub.E=V.sub.B=V.sub.C=0 V. T reaches its maximum of 100% when an injected electron has energy of E.sub.l. The device is said to be “in resonance”, and a maximum amount of current can flow through the structure if a voltage difference is present between the emitter and collector. T decreases rapidly as the energy deviates from E.sub.1.

(36) In some embodiments, FIG. 7 shows the electron and hole tunneling currents between the emitter terminal [102] 101 and the collector terminal 103 of an n-type QWRTT as functions of V.sub.B for N.sub.E=N.sub.B=N.sub.C=3, qϕ.sub.bn,E=qϕ.sub.bn,B=qϕ.sub.bn,C=0.4 eV, W.sub.EB=W.sub.CB=40 Å, V.sub.E=0 V, and V.sub.C=1 mV. I.sub.e is the electron tunneling current from emitter to collector, and I.sub.h is the hole tunneling current from collector to emitter. Because I.sub.e and I.sub.h behave differently with respect to a change in V.sub.B, the n-type device is designed so that electrons are the majority carriers and I.sub.h is always smaller than I.sub.e in the operation range. In some embodiments, the disclosed QWRTT is a normally ON transistor when E.sub.1 has about the same values in the emitter region 201, the base region 203, and the collector region 205 (i.e., E.sub.1,E=E.sub.1,B=E.sub.1,C and E.sub.1 is in alignment). The electron current is maximal and the device is at resonance when V.sub.B=0 V. The peak-to-valley current ratio (i.e., ON/OFF current ratio) is about four orders of magnitude. The current drops rapidly when V.sub.B is off 0 V. Swing S is defined as the change in V.sub.B that is required to change the device current by one decade. S is less than 2 mV/dec when V.sub.B is changed from 0 V to 5 mV.

(37) The swing is required to be small so that a transistor can be switched between ON and OFF with a small voltage change. Therefore, the power supply voltage and power consumption can be reduced. The minimal subthreshold swing for a conventional MOSFET at room temperature is 60 mV/dec (discussed by K. P. Cheung in “On the 60 mV/dec @300 K limit for MOSFET subthreshold swing,” Proceedings of 2010 International Symposium on VLSI Technology, System and Application, Hsinchu, 2010, pp. 72-73, doi: 10.1109/VTSA.2010.5488941). The QWRTT has a very small swing because (a) the current conduction mechanism is resonant tunneling and (b) the emitter and collector are 1-D quantum wire structures. The 1-D density of states (as shown in Eq. 7) plays an important role in the swing.

(38) FIG. 8 shows the electron tunneling current of an n-type QWRTT as a function of V.sub.C for N.sub.E=N.sub.B=N.sub.C=3, qϕ.sub.bn,E=qϕ.sub.bn,B=qϕ.sub.bn,C=0.4 eV, W.sub.EB=W.sub.CB=40 Å, and V.sub.E=V.sub.B=0 V. The device is ON when V.sub.B=0 V. The output characteristics show negative differential resistance (NDR). The NDR effect is due to (a) resonant tunneling and (b) 1-D density of states in the E/C regions.

(39) FIG. 9 shows the hole and electron tunneling currents of a p-type QWRTT as functions of V.sub.B for N.sub.E=N.sub.B=N.sub.C=3, qϕ.sub.bp,E=qϕ.sub.bp,B=qϕ.sub.bp,C=0.26 eV, W.sub.EB=W.sub.CB=40 Å, V.sub.E [=V.sub.B]=0 V, and V.sub.C=−1 mV. The p-type QWRTT with E.sub.1 in alignment is also a normally ON transistor. In a p-type QWRTT, the metal Fermi level E.sub.F is closer to the valance band edge than the conduction band edge, and the primary carriers are holes. The peak-to-valley current ratio is smaller than that of an n-type device because holes have a larger effective mass than electrons in silicon. The swing S is less than 2 mV/dec and about the same as that of an n-type device. Thus, both n- and p-type QWRTTs have the capability of switching transistor states by a small control voltage change, which can beneficially reduce the power supply voltage and power consumption.

(40) The common practice to improve the hole mobility in p-channel MOSFETs such as compressive stress and SiGe can also be applied to p-type QWRTTs. Simulation results show that the peak-to-valley current ratio can be improved if the hole effective mass is reduced since the effective mass is the primary difference between n- and p-type devices in simulation. Ge has a higher hole mobility and a higher conduction band edge than Si. The Ge in a SiGe alloy is found to effectively improve the peak-to-valley current ratio and reduce the electron tunneling current in a p-type QWRTT. Furthermore, simulation results show that the current gain h.sub.FE is improved and the NDR effect is reduced for an n-type device as the Ge content in a SiGe alloy increases because Ge has a smaller electron effective mass than Si. Therefore, Ge is beneficial to both n- and p-type devices. Both Si and Ge have a diamond cubic lattice structure, so as single crystal SiGe alloys. The method of creating quantum wires by ion implantation can be applied to single crystal SiGe alloys and other crystalline lattice structures with open channels.

(41) In some embodiments, the QWRTT can be configured as a normally ON transistor by having E.sub.1 in alignment. FIG. 10a shows the circuit diagram of a 2-input AND gate 1001, and FIG. 10b shows the circuit diagram of a 2-input OR gate 1002. Both gates are constructed by using n- and p-type normally ON QWRTTs disclosed in the present application. Assume a high voltage (such as the power supply voltage V.sub.cc) represents logic 1, and a low voltage (such as the ground voltage 0 V) represents logic 0. Each gate consists of a pull-up network (such as 1006 in FIGS. 10a and 1008 in FIG. 10b) and a pull-down network (such as 1005 in FIGS. 10a and 1007 in FIG. 10b). The function of the pull-up network is to provide a connection between the output and V.sub.CC when the output is logic 1. Similarly, the function of the pull-down network is to connect the output to ground when the output is logic 0. The pull-up network is constructed using p-type normally ON QWRTTs 1004, and the pull-down network is constructed using n-type normally ON QWRTTs 1003. The p-type QWRTTs 1004 are connected in series in the pull-up network 1006 of an AND gate as shown in FIG. 10a, and connected in parallel in the pull-up network 1008 of an OR gate as shown in FIG. 10b. The n-type QWRTTs 1003 are connected in parallel in the pull-down network 1005 of an AND gate as shown in FIG. 10a, and connected in series in the pull-down network 1007 of an OR gate as shown in FIG. 10b. The circuit configuration of the AND gate in FIG. 10a resembles a CMOS NOR gate, and the OR gate in FIG. 10b resembles a CMOS NAND gate.

(42) Normally ON transistors with small swings are very suitable for digital circuits. The MOSFETs used in digital circuits are typically enhancement-mode transistors. The power supply voltage V.sub.DD and threshold voltage V.sub.T are determined by the OFF state leakage current, subthreshold swing, and ON/OFF current ratio. Since the theoretical minimum of subthreshold swing is 60 mV/dec, there is very little room to scale down V.sub.DD and V.sub.T in each technology node. The dynamic power consumption of a digital circuit is proportional to f−V.sub.DD.sup.2, in which f is the clock frequency. The power consumption increases as the clock frequency increases. The circuit performance and clock frequency are eventually limited by the power consumption. The most effective way to improve the circuit performance is lowering down the power supply voltage, so the clock frequency has more room to increase. Since the QWRTT has a much smaller swing, the circuits built with QWRTTs can operate at a smaller power supply voltage and higher clock frequency than the circuits built with MOSFETs.

(43) Moreover, normally ON transistors are more suitable for stacked devices than enhancement-mode MOSFETs. For a MOSFET, the threshold voltage is increased if the source and body are reverse biased. It is called body effect. Therefore, the power supply voltage V.sub.DD needs to be sufficiently large enough to drive stacked devices. On the other hand, a normally ON transistor is fully ON when V.sub.B=0 V. There is no threshold voltage for a normally ON transistor. The power supply voltage can be small because there is no concern about the body effect. Furthermore, the device structure of stacked devices can be simplified to save device area and increase driving current. For example, FIG. 11 shows a simplified structure of a semiconductor device 1100 comprising two stacked QWRTTs. Instead of having E/B/C regions for each transistor, the two transistors in a stack can have one emitter region 1101, one collector region 1104, and two base regions 1102, 1103 in between. The emitter region 1101 and the first base region 1102 are separated by the emitter barrier region 1105. The collector region 1104 and the second base region 1103 are separated by the collector barrier region 1107. The two base regions 1102, 1103 are separated by the inter-base barrier region 1106. The emitter region 1101, the collector region 1104, and the two base regions 1102, 1103 each includes a plurality of metal quantum wires 1108.

(44) AND and OR gates can be built by using normally ON transistors. However, {AND, OR} alone is not a functionally complete set of logic operators. The QWRTT must include enhancement-mode transistors to build inverters because {AND, NOT}, {OR, NOT}, and {AND, OR, NOT} are functionally complete.

(45) In some embodiments, the QWRTT can be configured as an enhancement-mode transistor by having different values of E.sub.1 in the E/B/C regions (i.e., E.sub.1 is not in alignment). Since E.sub.1 is dependent of the superlattice size and the potential barrier height, E.sub.1 is not in alignment if the E/B/C superlattice structures are different. FIG. 12 shows the electron tunneling current of an n-type QWRTT as a function of V.sub.B for different N.sub.E and N.sub.C, in which N.sub.B=3. When (N.sub.E, N.sub.B, N.sub.C)=(2, 3, 2), E.sub.1 is not in alignment. The transistor is OFF when V.sub.B=0 V. The transistor is ON when V.sub.B=−0.05 V. FIG. 13 shows the electron tunneling current of an n-type QWRTT as a function of V.sub.B for different qϕ.sub.bn,B, in which qϕ.sub.bn,E=qϕ.sub.bn,C=0.4 eV. When (qϕ.sub.bn,E, qϕ.sub.bn,B, qϕ.sub.bn,C)=(0.4, 0.3, 0.4) eV, E.sub.1 is not in alignment. The transistor is OFF when V.sub.B=0 V, and the transistor is turned ON when V.sub.B is negative. The n-type enhancement-mode QWRTT resembles a p-channel MOSFET, in which a device is ON when V.sub.B or V.sub.G is negative. Similarly, the p-type QWRTT can also be configured as an enhancement-mode transistor if E.sub.1 is not in alignment. Therefore, the QWRTT includes the normally ON transistor family and the enhancement-mode transistor family. People can use the enhancement-mode QWRTTs to build CMOS-like logic circuits such as NAND gates and NOR gates.

(46) The presented disclosed QWRTT has distinct and beneficial properties compared to conventional transistors such as the MOSFET, bipolar junction transistor (BJT), resonant tunneling transistor (RTT), and metal base transistor (MBT) because of the following major differences. The QWRTT has 1-D metal quantum wires in the E/B/C regions. The QWRTT has very unique device characteristics, such as a very small swing. The primary current conduction mechanism is resonant tunneling. The potential wells in the E/B/C regions are formed by metal-semiconductor Schottky barriers. Typically there is only one energy state in the E/B/C potential wells. The QWRTT includes normally ON transistor family and enhancement-mode transistor family.

(47) The QWRTT has the following potential advantages over the MOSFET in digital circuit applications. (1) Lower Power Consumption—The QWRTT can operate at a lower power supply voltage and consume less energy because of its smaller swing. (2) Higher Speed—The device speed is higher because of larger driving current and smaller parasitic resistance. The intrinsic speed of a tunneling device is much faster than a device such as FET or BJT operating on drift or diffusion process. The current conducts through the whole barrier regions, while a MOSFET conducts current in a channel at the semiconductor surface. The E/B/C regions are made of metal quantum wires with low resistance. (3) Lower Manufacturing Cost—The fabrication process costs less because of a simpler device structure. Unlike the MOSFET, the QWRTT does not require a gate structure, shallow junction, lightly doped drain, silicide contact, etc. The number of process steps is much less than that of an advanced CMOS process. (4) Higher Density—The QWRTT has a smaller device size and a higher packing density because the device structure is simpler. The area spent on device isolation is smaller because of lower power supply voltage. (5) Better Reliability—The QWRTT does not have gate insulator related device reliability problems. (6) Better Uniformity—The QWRTT does not have statistical dopant fluctuation and line edge roughness, which are two major sources of device variations in the MOSFET.