Methods of forming integrated assemblies include stacked memory decks

Abstract

Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

Claims

1. A method of forming an assembly, comprising: forming a first deck having a first stack of alternating first and second tiers, and having a region extending through the first stack; a first material being within the first tiers and within the region; a second material being within the second tiers; the first material being a conductive material and the second material being an insulative material; forming an inter-deck structure over the first deck; the inter-deck structure comprising an inter-deck material; forming a second deck over the inter-deck structure; the second deck having a second stack of alternating third and fourth tiers; the third and fourth tiers comprising third and fourth materials, respectively; the fourth material being an insulative material; forming an opening which extends through the second stack and the inter-deck structure, and to the region; and removing the first material from the region with an etch selective for the first material relative to the third and fourth materials.

2. The method of claim 1 further comprising replacing the third material with conductive regions to form the conductive regions within the third tiers.

3. The method of claim 2 wherein the conductive regions include the first material.

4. The method of claim 2 further comprising forming channel material within the opening; the first deck having first memory cells which include segments of the first tiers together with segments of the channel material, and the second deck having second memory cells which include segments of the conductive regions of the third tiers together with segments of the channel material; the first and second decks being stacked one atop another, and accordingly the second memory cells being stacked atop the first memory cells.

5. The method of claim 4 wherein the channel material is one of several memory cell materials formed within the opening; the other memory cell materials including dielectric-barrier material, charge-blocking material, charge-storage material and tunneling material.

6. The method of claim 5 wherein the forming of the opening through the second stack and the inter-deck structure removes lateral regions of the inter-deck structure to form cavities under the second stack; and wherein one or more of the memory cell materials extend into said cavities to be directly under a region of the second stack.

7. The method of claim 6 comprising incorporating the stacked decks into a semiconductor package.

8. The method of claim 1 wherein the inter-deck material is a first inter-deck material, and further comprising a second inter-deck material under the first inter-deck material; the second inter-deck material being an etch-stop material; the forming of the opening through the second stack and through the inter-deck material comprising a first etch to extend the opening through the first inter-deck material to the etch-stop material, and comprising a subsequent second etch to extend the opening through the etch-stop material.

9. The method of claim 8 wherein: the first inter-deck material comprises silicon dioxide; the second inter-deck material comprises aluminum oxide; the first etch utilizes HF; and the second etch utilizes phosphoric acid.

10. The method of claim 1 wherein: the first material comprises a metal; the second and fourth materials comprise silicon dioxide; the third material comprises silicon nitride; and the inter-deck material comprises silicon dioxide which is less dense than the silicon dioxide of the third and fourth materials, and/or which has a higher concentration of one or more dopants than the silicon dioxide of the third and fourth materials.

11. The method of claim 10 wherein the silicon dioxide of the inter-deck material is less dense than the silicon dioxide of the third and fourth materials.

12. The method of claim 11 wherein the silicon dioxide of the inter-deck material is more porous than the silicon dioxide of the third and fourth materials.

13. The method of claim 10 wherein the silicon dioxide of the inter-deck material has a higher concentration of said one or more dopants than the silicon dioxide of the third and fourth materials.

14. The method of claim 13 wherein said one or more dopants are selected from the group consisting of carbon, boron and phosphorus.

15. The method of claim 10 wherein the first material consists of the metal.

16. The method of claim 10 wherein the first material consists of tungsten.

17. The method of claim 16 wherein the etch selective for the first material relative to the third and fourth materials is an etch utilizing nitric acid.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a block diagram of a prior art memory device having a memory array with memory cells.

(2) FIG. 2 shows a schematic diagram of the prior art memory array of FIG. 1 in the form of a 3D NAND memory device.

(3) FIG. 3 shows a cross-sectional view of the prior art 3D NAND memory device of FIG. 2 in an X-X′ direction.

(4) FIG. 4 is a schematic diagram of a prior art NAND memory array.

(5) FIGS. 5-8 are diagrammatic cross-sectional side views of a region of an integrated assembly at example process stages of an example method for forming an example structure.

(6) FIG. 8A is a diagrammatic top-down view of a region of the integrated assembly of FIG. 8, along the line A-A of FIG. 8.

(7) FIG. 8B is a diagrammatic three-dimensional view of vertically-offset regions of the integrated assembly of FIG. 8.

(8) FIGS. 9 and 10 are diagrammatic cross-sectional side views of the region of the example integrated assembly of FIG. 5 at example sequential process stages following process stage of FIG. 8. The process stage of FIG. 10 shows a region of an example multi-deck memory device.

(9) FIG. 10A is a diagrammatic top-down view of a region of the integrated assembly of FIG. 10, along the line A-A of FIG. 10.

(10) FIGS. 11 and 12 are diagrammatic cross-sectional side views of the example integrated assembly of FIG. 5 at example sequential process stages following the process stage of FIG. 6. The process stage of FIG. 11 may be alternative to that of FIG. 7. The process stage of FIG. 12 shows a region of an example multi-deck memory device.

(11) FIGS. 13-17 are diagrammatic cross-sectional side views of a region of an integrated assembly at example process stages of an example method for forming an example structure. The process stage of FIG. 17 shows a region of an example multi-deck memory device.

(12) FIG. 18 is a diagrammatic top-down view of an example package.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

(13) Some embodiments include methods of using some regions of a continuous conductive material of a lower deck as wordlines (routing structures) of a memory device, and using other regions of the continuous conductive material of the lower deck as sacrificial material which is removed to form openings through the lower deck. One or more memory cell materials (e.g., channel material, charge-storage material, etc.) may be formed within the opening during fabrication of memory cells of the memory device. An upper deck may be formed over the lower deck to form a multi-deck memory device. The openings formed through the lower deck may extend from openings formed through the upper deck. An inter-deck material may be provided between the upper and lower decks. The inter-deck material may be “soft”, and specifically may be relatively easy to etch as compared to other materials of the upper and lower decks. Some embodiments include integrated assemblies (e.g., multi-deck memory devices) formed utilizing the methodology described above. Example embodiments are described with reference to FIGS. 5-18.

(14) Referring to FIG. 5, an assembly 10 includes a first deck 12 having a first stack 14 of alternating first and second tiers 16 and 18. The illustrated region of the stack 14 is only a partial region of the stack, and it is to be understood that the stack may comprise more than the illustrated number of tiers 16 and 18.

(15) The first tiers 16 include first and second conductive materials 20 and 22. The conductive materials 20 and 22 have different compositions relative to one another. In some embodiments, the conductive materials 20 and 22 may be metal-containing materials. The first conductive material 20 may consist of, or consist essentially of, one or more metals (e.g., one or more of titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.). The second conductive material may comprise, consist essentially of, or consist of one or more metal-containing compositions (e.g., one or more of metal germanide, metal silicide, metal nitride, metal carbide, metal boride, etc.). In some embodiments, the first conductive material 20 may consist of, or consist essentially of, tungsten (W); and the second conductive material 22 may comprise, consist essentially of, or consist of one or more of titanium nitride (TiN), tungsten nitride (WN), and tantalum nitride (TaN), where the chemical formulas indicate primary constituents rather than specific stoichiometries.

(16) In some embodiments, the second conductive material 22 may be considered to be configured as horizontally-extending bars 24 within the first tiers 16.

(17) The second tiers 18 comprise an insulative material 26. The insulative material 26 may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide. The silicon dioxide may have a dielectric constant of about 3.9, and accordingly may be of ordinary density associated with relatively high-quality silicon dioxide.

(18) In some embodiments, the materials 20 and 26 may be referred to as first and second materials, respectively; with such first and second materials being associated with the first and second tiers 16 and 18, respectively.

(19) In some embodiments, the first tiers 16 may be considered to correspond to conductive levels, and the second tiers 18 may be considered to correspond to insulative levels; with the conductive levels and insulative levels alternating with one another within the stack 14. In the illustrated embodiment, each of the conductive levels 16 comprises two conductive materials (20 and 22). In other embodiments, each of the conductive levels may comprise only a single conductive material (e.g., only material 20) or may comprise more than two conductive materials.

(20) The deck 12 has a region 28 extending entirely through the stack 14 of the first and second tiers 16 and 18. The first conductive material 20 fills such region 28.

(21) The illustrated deck 12 may be formed with any suitable processing. In some embodiments, the materials 20, 22 and 26 may be deposited as layers stacked one atop another. Such deposition may comprise, for example, one or more of atomic layer deposition (ALD), chemical vapor deposition (CVD) and physical vapor deposition (PVD). Subsequently, an opening may be formed through the layers and filled with the conductive material 20 to form the illustrated conductive region 28 passing through the deck 12.

(22) The deck 12 may be supported by a semiconductor substrate (base). The semiconductor substrate is not shown in the figures of this disclosure in order to simplify the drawings. The semiconductor substrate may comprise any suitable semiconductor composition(s); and in some embodiments may comprise monocrystalline silicon.

(23) Referring to FIG. 6, an inter-deck structure 30 is formed over the first deck (lower deck) 14, and a second deck (upper deck) 32 is formed over the inter-deck structure.

(24) The second deck 32 comprises a second stack 34 of alternating third and fourth tiers 36 and 38. The illustrated region of the stack 34 is only a partial region of the stack, and it is to be understood that the stack may comprise more than the illustrated number of tiers 36 and 38.

(25) The third and fourth tiers 36 and 38 comprise third and fourth materials 40 and 42, respectively. The third and fourth materials are different compositions relative to one another.

(26) The fourth material 42 is an insulative material, and in some embodiments may comprise the same composition as the insulative material 26 of the first stack 14. Accordingly, in some embodiments the fourth material 42 may comprise silicon dioxide having a dielectric constant of about 3.9.

(27) The third material 40 may be a sacrificial material, and may comprise any suitable composition(s). In some embodiments, the third material 40 may comprise, consist essentially of, or consist of silicon nitride (SiN), where the chemical formula indicates primary constituents rather than a specific stoichiometry.

(28) The inter-deck structure 30 comprises a first inter-deck material 44 over a second inter-deck material 46.

(29) In some embodiments, the first inter-deck material 44 may be a relatively “soft” material, meaning that the first inter-deck material 44 may be relatively easy to selectively etch relative to the materials 40 and 42 of the second stack 34. The first inter-deck material 44 may comprise, for example, silicon dioxide which etches faster than the silicon dioxide of material 42 when exposed to a hydrofluoric-acid-containing etchant. In some embodiments, the inter-deck material 44 may comprise silicon dioxide having a lower density than the silicon dioxide of material 42 (e.g., the inter-deck material 44 may be porous silicon dioxide). Additionally, or alternatively, one or more dopants may be provided within the silicon dioxide of the inter-deck material 44 to increase an etch rate of such silicon dioxide. Suitable dopants may include, for example, one or more of carbon, boron and phosphorus.

(30) The second inter-deck material 46 may be a relatively “hard” material, meaning that the material 46 may function as an etch-stop for an etch utilized to punch through the materials 40 and 42 of the stack 34. In some embodiments, the second inter-deck material 46 may comprise, consist essentially of, or consist of aluminum oxide (AlO), where the chemical formula indicates primary constituents rather than a specific stoichiometry.

(31) Referring to FIG. 7, an opening 48 is formed through the second stack 34, and through the first inter-deck material 44. The opening 48 stops on the second inter-deck material 46 (i.e., the etch-stop material).

(32) The opening 48 may be patterned with any suitable methodology. For instance, in some embodiments a photolithographically-patterned photoresist mask (not shown) may be utilized to define a location of the opening 48, and the opening 48 may then be formed with one or more suitable etches. The etches utilized to form the opening 48 may utilize hydrofluoric acid to penetrate silicon dioxide 42 of levels 36, and phosphoric acid to penetrate silicon nitride 40 of levels 38. The hydrofluoric acid can also be utilized to penetrate silicon dioxide of the inter-deck material 44.

(33) In the illustrated embodiment, the inter-deck material 44 is recessed to form cavities 50 which extend under the second deck 32. Such recessing may be due to the material 44 being “softer” (i.e., more readily etched) than the materials of the stack 32.

(34) Referring to FIG. 8, the opening 48 is extended through the second inter-deck material 46 to the region 28 (FIG. 7) comprising the conductive material 20, and is then etched through the conductive material 20. Accordingly, the opening 48 is formed to extend through the first and second decks 12 and 32, and through the inter-deck structure 30 between the first and second decks.

(35) In embodiments in which the second inter-deck material 46 comprises aluminum oxide, the opening 48 may be extended through such second inter-deck material with an etch utilizing phosphoric acid.

(36) In some embodiments, it can be advantageous to utilize tungsten within the region 28 of FIG. 7 as tungsten may be readily removed selectively relative to the silicon-oxide-containing materials 26 and 40, and the silicon-nitride-containing material 42 (such may be accomplished with, for example, an etch utilizing nitric acid (HNO.sub.3)). The opening 48 has relatively straight vertical sidewalls passing through the decks 12 and 32, rather than having tapered sidewalls. Such may be advantageous relative to architectures formed with conventional processing, in that such architectures frequently have tapered sidewalls of openings analogous to the opening 48 which can lead to problems in subsequently forming materials within such openings.

(37) In the shown embodiment, the cavities 50 are extended under the first deck 32 as the opening 48 is passed through the second inter-deck material 46 and through the first stack 14. In some embodiments, the first inter-deck material 44 may be considered to be removed from lateral regions of the inter-deck structure 30 adjacent the opening 28 to extend the cavities laterally under the second deck 32. The removal of the first inter-deck material 44 to extend the cavities 50 may occur during the etching utilized to pass through the material 46 and/or during the etch utilized to remove material 20 from the region 28.

(38) FIG. 8A shows a top-down view along the line A-A of FIG. 8, and shows that the opening 48 has a closed-shaped when viewed from above. In the illustrated embodiment, the opening 48 is circular when viewed from above. In other embodiments, the opening may have other suitable closed shapes when viewed from above (e.g., elliptical, rectangular, etc.).

(39) FIG. 8B diagrammatically illustrates regions of the opening 48 passing through materials 40, 44 and 20 at regions labeled X, Y and Z in FIG. 8. The region Z is within the first deck 12, the region X is within the second deck 32, and the region Y is within the inter-deck region 30. The view of FIG. 8B further illustrates that the cavities 50 extend into regions between the first and second decks 12 and 32.

(40) The opening 48 may be representative of a large plurality of substantially identical openings formed through the decks 12 and 32 at the processing stage of FIG. 8; with the term “substantially identical” meaning identical to within reasonable tolerances of fabrication and measurement.

(41) Referring to FIG. 9, dielectric-barrier material 60 is formed within the opening 48, charge-blocking material 58 is formed laterally adjacent the dielectric-barrier material 60, charge-storage material 56 is formed laterally adjacent the charge-blocking material 58, tunneling material (dielectric material, gate-dielectric material) 54 is formed laterally adjacent the charge-storage material 56, and channel material 52 is formed laterally adjacent the tunneling material 54. The materials 52, 54, 56, 58 and 60 may be referred to as memory cell materials.

(42) The channel material 52 may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon, germanium, III/V semiconductor material (e.g., gallium phosphide), semiconductor oxide, etc.; with the term III/V semiconductor material referring to semiconductor materials comprising elements selected from groups III and V of the periodic table (with groups III and V being old nomenclature, and now being referred to as groups 13 and 15). In some example embodiments, the channel material 52 may comprise, consist essentially of, or consist of appropriately-doped silicon.

(43) In the illustrated embodiment, the channel material is configured as an annular ring surrounding an insulative material 62 (e.g., silicon dioxide). Such configuration of the channel material may be considered to correspond to a “hollow” channel configuration (or as a hollow channel material pillar), with the dielectric material 62 being provided within the “hollow” of the channel material configuration. In other embodiments, the channel material may be configured as a solid pillar, rather than being configured as the illustrated hollow pillar.

(44) The tunneling material 54 may comprise any suitable composition(s); and in some embodiments may comprise one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, etc.

(45) The charge-storage material 56 may comprise any suitable composition(s); and in some embodiments may comprise charge-trapping material; such as, for example, one or more of silicon nitride, silicon oxynitride, conductive nanodots, etc.

(46) The charge-blocking material 58 may comprise any suitable composition(s); and in some embodiments may comprise one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, etc.

(47) The dielectric-barrier material 60 may comprise any suitable composition(s); and in some embodiment may comprise one or more of aluminum oxide, hafnium oxide, zirconium oxide, etc.

(48) The memory cell materials 52, 54, 56, 58 and 60 may be considered to be configured as a pillar 61 which passes through the first and second decks 12 and 32. Such pillar may be representative of a plurality of substantially identical pillars that may be formed at the process stage of FIG. 9.

(49) The channel material 52 may be coupled with a conductive source structure (e.g., a source line or source plate) analogous to the source structures described above with reference to FIGS. 1-4. In some embodiments, such source structure may be under the deck 12. The source structure may be comprised by the deck 12, or may be within another deck under the deck 12.

(50) In the illustrated embodiment of FIG. 9, several of the memory cell materials 52, 54, 56, 58 and 60 extend into the cavities 50. Specifically, the dielectric-barrier material 60, the charge-blocking material 58, and the charge-storage material 56 extend into the cavities 50. In other embodiments, additional memory cell materials may extend into the cavities 50, or fewer memory cell materials may extend into the cavities 50.

(51) Referring to FIG. 10, the third material 40 (FIG. 9) is removed from the third tiers 38 and replaced with conductive regions 64. The third material 48 may be removed with any suitable processing, and in some embodiments may be removed with an etch utilizing phosphoric acid. The third material may be removed utilizing slits (not shown) provided through the second deck 32 in regions laterally adjacent to the pillars 61 of the memory cell materials 52, 54, 56, 58 and 60.

(52) The conductive regions 64 comprise a fifth material 66, and a sixth material 68 extending along an outer periphery of the fifth material.

(53) In some embodiments, the fifth material 66 may comprise a same composition as the first material 20. For instance, the materials 20 and 66 may both comprise, consist essentially of, or consist of tungsten.

(54) In some embodiments, the sixth material 68 may comprise a same composition as the second material 22. For instance, the materials 22 and 68 may both comprise, consist essentially of, or consist of one or more of titanium nitride, tungsten nitride and tantalum nitride.

(55) The tiers 36 and 38 may be referred to as conductive levels and insulative levels, respectively, at the processing stage of FIG. 10; with the conductive levels and insulative levels alternating with one another within the stack 34 of the upper deck 32. In the illustrated embodiment, each of the conductive levels 36 comprises two conductive materials (66 and 68). In other embodiments, each of the conductive levels may comprise only a single conductive material or may comprise more than two conductive materials.

(56) First memory 70 cells are within the first stack 14 of the first deck 12. The first memory cells include segments of the conductive materials 20 and 22 of the first tiers 16, and also include segments of the memory cell materials 52, 54, 56, 58 and 60.

(57) Second memory cells 72 are within the second stack 34 of the second deck 32. The second memory cells include segments of the conductive materials 66 and 68 of the third tiers 36, and also include segments of the memory cell materials 52, 54, 56, 58 and 60.

(58) The memory cells 70 and 72 may be suitable for utilization in NAND memory arrays (devices, architectures) analogous to the memory arrays described above with reference to FIGS. 1-4. The assembly 10 of FIG. 10 may be considered to be an example configuration of a memory device.

(59) In operation, the charge-storage material 56 may be configured to store information in the memory cells 70 and 72. The value (with the term “value” representing one bit or multiple bits) of information stored in an individual memory cell (70 or 72) may be based on the amount of charge (e.g., the number of electrons) stored in a charge-storage region. The amount of charge within an individual charge-storage region may be controlled (e.g., increased or decreased) at least in part, based on the value of voltage applied to an associated control gate, and/or based on the value of voltage applied to an associated channel material. The tunneling material 54 may be configured to allow desired tunneling (e.g., transportation) of charge (e.g., electrons) between the charge-storage material 56 and the channel material 52. The tunneling material may be configured (i.e., engineered) to achieve a selected criterion, such as, for example, but not limited to, an equivalent oxide thickness (EOT). The EOT quantifies the electrical properties of the tunneling material, (e.g., capacitance) in terms of a representative physical thickness. For example, EOT may be defined as the thickness of a theoretical silicon dioxide layer that would be required to have the same capacitance density as a given dielectric (e.g., tunneling material 54), ignoring leakage current and reliability considerations. The charge-blocking material 58 may provide a mechanism to block charge from flowing from the charge-storage material to the control gate. The dielectric barrier material 60 may be utilized to inhibit back-tunneling of electrons from the control gate toward the charge-storage material.

(60) The memory cells 70 are vertically stacked one atop another within the first deck 12. The number of vertically-stacked memory cells 70 may be any suitable number; and in some embodiments may be 8 memory cells, 16 memory cells, 32 memory cells, 64 memory cells, 128 memory cells, etc. Similarly, the memory cells 72 are vertically stacked one atop another within the second deck 32, and the number of vertically-stacked memory cells 72 may be any suitable number.

(61) In the shown embodiment, the second memory cells 72 are vertically stacked over the first memory cells 70.

(62) The segments of the conductive tiers 16 and 36 utilized within the memory cells 70 and 72, respectively, may be considered to be control gate regions of the memory cells. In some embodiments, the segments of the conductive tiers 16 utilized within the memory cells 70 may be referred to as first control gate regions 74, and the segments of the conductive tiers 36 utilized within the second memory cells 72 may be referred to as second control gate regions 76.

(63) In the illustrated embodiment, the first control gate regions 74 comprise the first conductive material 20 vertically between the horizontally-extending bars 24 of the second conductive material 22. The first control gate regions 74 have terminal edges 78 which are directly against the dielectric-barrier material 60; and such terminal edges comprise both the first conductive material 20 and the second conductive material 22.

(64) The second control gate regions 76 comprise the conductive material 66 (which may be referred to as a third conductive material), and the conductive material 68 (may be referred to as a fourth conductive material) along outer surfaces of the conductive material 66. The second control gate regions have terminal edges 80 which are directly against the dielectric-barrier material 60; and such terminal edges only comprise the fourth conductive material 68.

(65) The second memory cells 72 are similar to the first memory cells 70, but are not identical to the first memory cells due to the differences between the first and second control gate regions 74 and 76.

(66) The configuration of FIG. 10 may be considered to be a multi-deck memory device comprising the vertically-stacked memory cells 70 and 72. The illustrated memory cells may be comprised by a NAND string, and such NAND string may be representative of a large number of substantially identical NAND strings formed at the processing stage of FIG. 10 to assemble a NAND architecture analogous to the architectures described above with reference to FIGS. 1-4.

(67) FIG. 10A shows a top-down view along the line A-A of FIG. 10, and shows the memory cell materials 52, 54, 56, 58 and 60 arranged as concentric cylinders along the pillar 61.

(68) In some embodiments, the first deck 12 may be considered to comprise first inner lateral edges 82 along sidewalls of the pillar 61, and the second deck 32 may be considered to comprise second inner lateral edges 84 along the sidewalls of the pillar 61. The inter-deck structure 30 may be considered to comprise third inner lateral edges 86 which are laterally offset relative to the first and second lateral edges; and which are along the cavities 50. The third lateral edges 86 are associated with the first inter-deck material 44, and specifically correspond to edges where the first material 44 interfaces with the dielectric-barrier material 60.

(69) In the shown embodiment, the second inter-deck material 46 may be considered to comprise fourth lateral edges 88. The fourth lateral edges 88 are not substantially laterally offset relative to the first and second lateral edges 82 and 84; with the term “substantially” indicating to within reasonable tolerances of fabrication and measurement.

(70) In some embodiments, the cavities 50 (FIGS. 7 and 8) may be avoided by tailoring the various materials of the inter-deck structure 30 and the etching conditions utilized to form the opening 48. FIG. 11 shows a process stage analogous to that of FIG. 8, but in which the opening 48 has substantially straight vertical sidewalls, rather than comprising the cavities 50.

(71) The configuration of FIG. 11 may be subjected to processing analogous to that described above with reference to FIGS. 9 and 10 to form a multi-deck configuration analogous to that described above with reference to FIG. 10. For instance, FIG. 12 shows the assembly 10 as a multi-deck memory device analogous to the multi-deck memory device described above with reference to FIG. 10.

(72) In some embodiments, the conductive material 20 of FIG. 5 may be recessed within the region 28 prior to forming the etch-stop material 46. Such may improve subsequent etching through the etch stop material 46 and the conductive material 20 of region 28. FIG. 13 shows a process stage which may follow the process stage of FIG. 5. The conductive material 20 is recessed at a top of the region 28, and subsequently the etch-stop material 46 is formed across the upper tier 16 and across the conductive material 20 of the region 28.

(73) Referring to FIG. 14, the inter-deck material 44 is formed over the etch-stop material 46 to form the inter-deck structure 30, and then the second deck 32 is formed over the inter-deck structure 30.

(74) Referring to FIG. 15, the opening 48 is formed to extend through the upper deck 32, and through the inter-deck material 44; with the opening 48 stopping on the etch-stop material 46.

(75) Referring to FIG. 16, the opening 48 is extended through the etch-stop material 46 and through the conductive material 20 of the region 28 (FIG. 15).

(76) Referring to FIG. 17, the memory cell materials 52, 54, 56, 58 and 60 are provided within the opening 48 to form the pillar 61. Subsequently, the material 40 (FIG. 16) is replaced with conductive materials 66 and 68 to form a memory device analogous to that described above with reference to FIG. 10.

(77) The memory device configurations of FIGS. 10, 12 and 17 may be incorporated into semiconductor packages. An example semiconductor package 90 as shown in FIG. 18. The package 90 may comprise encapsulation material over a semiconductor die 92. The semiconductor die may comprise a memory device configuration formed in accordance with the embodiments described above. The die 92 is shown in dashed-line (i.e., phantom) view to indicate that the die may be under other materials. The package 90 may include pins, pads, wires, etc. (not shown) for electrically coupling circuitry of the die 92 with circuitry external of the package 90. Although the semiconductor package 90 is shown comprising only a single die, in other embodiments individual semiconductor packages may comprise multiple dies.

(78) The assemblies and structures discussed above may be utilized within integrated circuits (with the term “integrated circuit” meaning an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

(79) Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

(80) The terms “dielectric” and “insulative” may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term “dielectric” in some instances, and the term “insulative” (or “electrically insulative”) in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

(81) The terms “electrically connected” and “electrically coupled” may both be utilized in this disclosure. The terms are considered synonymous. The utilization of one term in some instances and the other in other instances may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow.

(82) The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The descriptions provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.

(83) The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings.

(84) When a structure is referred to above as being “on”, “adjacent” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on”, “directly adjacent” or “directly against” another structure, there are no intervening structures present. The terms “directly under”, “directly over”, etc., do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

(85) Structures (e.g., layers, materials, etc.) may be referred to as “extending vertically” to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

(86) Some embodiments include a method of forming an assembly. A first deck is formed to have a first stack of alternating first and second tiers, and to have a region extending through the first stack. A first material is within the first tiers and is within the region. A second material is within the second tiers. The first material is a conductive material and the second material is an insulative material. An inter-deck structure is formed over the first deck. The inter-deck structure comprises an inter-deck material. A second deck is formed over the inter-deck structure. The second deck has a second stack of alternating third and fourth tiers. The third and fourth tiers comprise third and fourth materials, respectively. The fourth material is an insulative material. An opening is formed to extend through the second stack and the inter-deck structure, and to the region. The first material is removed from the region with an etch selective for the first material relative to the third and fourth materials.

(87) Some embodiments include an integrated assembly with a first deck that has first memory cells arranged in first tiers disposed one atop another. The first deck has first inner lateral edges, A second deck is over the first deck. The second deck has second memory cells arranged in second tiers disposed one atop another. The second deck has second inner lateral edges. An inter-deck structure is between the first and second decks. The inter-deck structure has an inter-deck material with third inner lateral edges which are laterally offset relative to the first and second inner lateral edges to leave cavities between the first and second decks. A pillar passes through the first and second decks and the inter-deck structure. The pillar includes channel material, tunneling material, charge-storage material, charge-blocking material and dielectric-barrier material.

(88) Some embodiments include an integrated assembly having a first deck which has first memory cells arranged in first tiers disposed one atop another. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second conductive material is compositionally different from the first conductive material. The first control gate regions have first terminal edges which comprise both the first conductive material and the second conductive material. An inter-deck structure is over the first deck. A second deck is over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. The second memory cells have second control gate regions which include a third conductive material, and which include a fourth conductive material along an outer surface of the third conductive material. The fourth conductive material is compositionally different from the third conductive material. The second control gate regions have second terminal edges which comprise only the fourth conductive material. A pillar passes through the first and second decks and the inter-deck structure. The pillar includes channel material, tunneling material, charge-storage material, charge-blocking material and dielectric-barrier material; the dielectric barrier material laterally surrounding the channel material, the tunneling material, the charge-storage material and the charge-blocking material. The first and second terminal edges are directly against the dielectric-barrier material.

(89) In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.