High performance topological insulator transistors

Abstract

Topological insulators, such as single-crystal Bi.sub.2Se.sub.3 nanowires, can be used as the conduction channel in high-performance transistors, a basic circuit building block. Such transistors exhibit current-voltage characteristics superior to semiconductor nanowire transistors, including sharp turn-on, nearly zero cutoff current, very large On/Off current ratio, and well-saturated output current. The metallic electron transport at the surface with good effective mobility can be effectively separated from the conduction of the bulk topological insulator and adjusted by field effect at a small gate voltage. Topological insulators, such as Bi.sub.2Se.sub.3, also have a magneto-electric effect that causes transistor threshold voltage shifts with external magnetic field. These properties are desirable for numerous microelectronic and nanoelectronic circuitry applications, among other applications.

Claims

1. A transistor comprising: a source; a drain; a conduction channel comprising a topological insulator material nanowire between the source and the drain, wherein the topological insulator material nanowire has a diameter in a range from about 1 nm to about 100 nm; and a first gate over the topological insulator material nanowire, wherein applying a threshold voltage to the first gate switches the transistor from an off-state to an on-state.

2. The transistor of claim 1, wherein the topological insulator material nanowire is physically connected to the source and the drain.

3. The transistor of claim 1, wherein the first gate is spaced apart from the topological insulator material nanowire by a dielectric material.

4. The transistor of claim 3, wherein the dielectric material comprises a first oxide material.

5. The transistor of claim 1, wherein the source, the drain, and the topological insulator material nanowire are disposed over a substrate.

6. The transistor of claim 5, wherein the substrate further comprises an oxide layer.

7. The transistor of claim 6, wherein the oxide layer comprises a second oxide material.

8. The transistor of claim 1, wherein the topological insulator material nanowire is self-aligned.

9. The transistor of claim 1, wherein the topological insulator material nanowire is a single crystal nanowire.

10. The transistor of claim 1, wherein the topological insulator material nanowire comprises one or more of Bismuth and Tellurium.

11. The transistor of claim 10, wherein the topological insulator material nanowire comprises Bi.sub.2Se.sub.3.

12. A transistor comprising: a source; a drain; a conduction channel comprising a topological insulator material nanowire between the source and the drain, wherein the topological insulator material nanowire has a diameter in a range from about 50 nm to about 150 nm; and a first gate over the topological insulator material nanowire, wherein applying a threshold voltage to the first gate switches the transistor from an off-state to an on-state.

13. The transistor of claim 12, wherein as an electric field applied to the topological insulator material nanowire increases, a dominating factor of electron mobility within the topological insulator material nanowire transitions from phonon scattering to coulomb scattering.

14. The transistor of claim 1, wherein the topological insulator material nanowire functions as a metallic conductor when a positive gate voltage is applied to the topological insulator material nanowire, and wherein the topological insulator material nanowire functions as an insulator when a negative gate voltage is applied to the topological insulator material nanowire.

15. The transistor of claim 1, wherein the topological insulator material nanowire is configured to allow electrons to travel in circles surrounding the topological insulator material nanowire while traveling from the source to the drain.

16. A method, comprising: applying a first gate voltage to a topological insulator material nanowire in a device, wherein the topological insulator material nanowire is between a source and a drain of a transistor of the device, wherein the topological insulator material nanowire has a diameter in a range from about 1 nm to about 100 nm; receiving a first current characteristic of an insulator from the topological insulator material nanowire while the first gate voltage is applied to the topological insulator material nanowire; applying a second gate voltage to the topological insulator material nanowire; and receiving a second current characteristic of a metal from the topological insulator material nanowire while the second gate voltage is applied to the topological insulator material nanowire, wherein the second current characteristic represents an on-state of the transistor and the first current characteristic represents an off-state of the transistor.

17. The method of claim 1, wherein the first gate is a top-surround gate configured to at least partially surround the topological insulator material nanowire.

18. The method of claim 17, wherein a dielectric layer is disposed between the top-surround gate and the topological insulator material nanowire.

19. The method of claim 17, wherein the topological insulator material nanowire is a single crystal nanowire grown from a catalyst and integrated by using a self-alignment technique.

20. The method of claim 19, wherein the catalyst comprises Au.

Description

DESCRIPTION OF FIGURES

(1) FIG. 1 is a SEM image of Bi.sub.2Se.sub.3 nanowires.

(2) FIG. 2 shows transmission electron microscope (TEM) measurements of Bi.sub.2Se.sub.3 nanowires.

(3) FIGS. 3(a)-(d) are (a) SEM and (a) TEM of Bi.sub.2Se.sub.3, (c) schematic of a Bi.sub.2Se.sub.3 NWFET, (d) TEM cross-section of NWFET.

(4) FIG. 4 is a schematic structure of a Bi.sub.2Se.sub.3 NWFET from side view (left) and front view (right).

(5) FIG. 5 shows the output current-voltage characteristics of Bi.sub.2Se.sub.3 NWFET on a linear scale (left) and a log scale (right).

(6) FIG. 6 illustrates the transfer current-voltage characteristics of Bi.sub.2Se.sub.3 NWFET.

(7) FIG. 7(a)-(d) show the transfer current-voltage characteristics of Bi.sub.2Se.sub.3 NWFET.

(8) FIG. 8 shows the electron effective mobility of Bi.sub.2Se.sub.3 NWFET.

(9) FIG. 9(a)-(d) illustrate the transfer characteristics of Bi.sub.2Se.sub.3 NWFET at different temperatures.

(10) FIG. 10 is a schematic of a prototype Bi.sub.2Se.sub.3 NWFET with magnetic field along the axis of the nanowire illustrated.

(11) FIG. 11 shows the Aharonov-Bohm oscillation of a prototype NWFET measured at 4.0 K.

(12) FIGS. 12(a)-(h) show measurements of the drain current I.sub.DS as a function of parallel magnetic field for different V.sub.GS.

DESCRIPTION

(13) Microelectric devices based on topological insulators could be considered analogs of metal oxide semiconductor field effect transistors (MOSFETs). The MOSFET is the basic building block in complementary metal oxide semiconductor (CMOS) technology, the fundamental basis for digital and analog circuits. The surface conduction of Si in conventional CMOS devices is protected by thermal SiO.sub.2 to optimize its inversion properties for good transistor performance. This is one of the primary reasons why Si is preferred over other semiconductor materials for CMOS technology. For a topological insulator material, the gapless surface state is derived from its inherent material properties, and maintains a robust surface conduction. Therefore the integration of TI as the active conduction channel in MOSFETs is very attractive because it will leverage the advantages afforded by the novel TI materials with the vast infrastructure of current semiconductor technology.

(14) The inventors fabricated and measured surrounding-gate Bi.sub.2Se.sub.3 nanowire field-effect transistors. The nanowires were grown from Au catalyst and integrated by using a self-alignment technique. The FET current-voltage (I-V) characteristics were measured at different temperatures, exhibiting excellent performance. The separation of surface metallic conduction from bulk semiconductor conduction with gate electric field was studied at different temperatures. The activation energy of bulk conduction was found to be very close to the band gap of bulk Bi.sub.2Se.sub.3. The effective electron mobility and scattering mechanism in prototype devices was also studied.

Fabrication of Prototype Transistors

(15) Transistors as described herein may comprise a substrate, such as a Si layer, an oxide layer, a conducting channel comprising a topological insulator, and a top gate over the topological insulator. The conducting channel may be in the form of nanowires, the particular shape of which will depend on the molecular composition. Nanowires may be single crystal nanowires, such as single-crystal Bi.sub.2Se.sub.3 nanowires, and may be self-aligned. An insulating layer, comprising a dielectric material such as HfO.sub.2, may be positioned between the topological insulator and the top gate, such that the topological insulator is spaced apart from the top gate.

(16) Prototype embodiments of topological insulator transistors, and in particular self-aligned Bi.sub.2Se.sub.3 NWFETs, were fabricated on a substrate comprising a highly doped p-type Si wafer with an oxide layer comprising a 300 nm layer of thermal SiO.sub.2. One of ordinary skill should understand that this process can be modified to produce transistors using different materials, such as other stoichiometric binary compounds. For example, one of ordinary skill would understand that other nanowire fabrication methods, such as top-down defining by using electron-beam lithography, molecular beam epitaxy and physical vapor deposition, can be used to prepare binary compounds used as topological insulator materials.

(17) The thermal SiO.sub.2 oxide layer was grown by dry oxidation on a Si wafer. On the top of the wafer, the Bi.sub.2Se.sub.3 nanowires were grown from Au catalyst deposited by sputtering in pre-defined locations. The nanowire growth followed a solid-vapor-solid route. The wafers (with Au) were loaded at the downstream end in a horizontal tube furnace while Bi.sub.2Se.sub.3 source powder was located at the heat center of the furnace. Then the furnace is heated to a temperature in a range of 500° C.˜550° C. and kept in that temperature for 2 h under a flow of 50 standard cubic centimeters (sccm) Ar as carrier gas. The as-grown Bi.sub.2Se.sub.3 nanowires were about 20 μm in length and 150 nm in diameter. Then 3 nm/100 nm Ti/Pt source/drain (S/D) electrodes were patterned on the nanowires at the growth location by photolithography, forming Pt/Bi.sub.2Se.sub.3 Schottky junctions at both source and drain, thereby physically connecting the topological insulator to the source and the drain. The channel length was defined to be 2 μm. A layer of 30-nm HfO.sub.2 was then deposited at 250° C. by atomic layer deposition (ALD) with precursors of Tetrakis(ethylmethylamino)hafnium and water covering the nanowire channel and also part of S/D electrodes. Preferably, the last step is the formation of a 100 nm Pd top gate located over the topological insulator, by a suitable process such as a lift-off process. In the presence of the HfO.sub.2 layer, the gate is spaced apart from the topological insulator. Unlike the traditional nanowire harvesting and alignment methods, this self-alignment approach not only enables simultaneous batch fabrication of reproducible and homogeneous nanowire devices of high quality, but also limits the contamination of the nanowire during the fabrication process.

(18) Bi.sub.2Se.sub.3 has a layered rhombohedral crystal structure with five covalently bonded atoms in one unit cell. These quintuple layers are linked by Van der Waals interactions. The as-synthesized Bi.sub.2Se.sub.3 nanowires were examined by scanning electron microscopy (SEM). As shown in FIG. 1, the VLS-synthesized Bi.sub.2Se.sub.3 nanowires had diameters of about 100-200 nm, and lengths ranging from 100 nm to tens of micrometers. The gold nanoparticle on the end of each nanowire suggests the VLS mechanism.

(19) As shown in FIG. 2, transmission electron microscopy (TEM) measurements were used to determine the crystal structure of Bi.sub.2Se.sub.3 nanowires. Selected-area electron diffraction (SAED) patterns indicate a good single-crystal rhombohedral phase, with the growth direction of [1120]. High resolution TEM image shows the hexagonal lattice edges, confirming the single-crystalline phase.

(20) FIG. 3(a) shows a scanning electron microscopy (SEM) image of the as-synthesized Bi.sub.2Se.sub.3 nanowires which are about 50 nm to 150 nm wide and 10 μm long. Au nanoparticles (NPs) were found at the top-end of each nanowire. This indicated that Bi.sub.2Se.sub.3 vapor was first absorbed by Au catalyst to form a Bi.sub.2Se.sub.3 and Au eutectic; then Bi.sub.2Se.sub.3 diffused through Au to form the single-crystal nanowires. This process is similar to the growth of Si nanowires governed by vapor-liquid-solid (VLS) mechanism. The high-resolution transmission electron microscopy (HRTEM) image shown in FIG. 3(b) demonstrates that the Bi.sub.2Se.sub.3 nanowires are in a well-defined single-crystal rhombohedral phase and the growth direction is close to [1120]. A schematic of an embodiment of a Bi.sub.2Se.sub.3 nanowire FET is shown in FIG. 3(c) and a TEM image of the cross-section in FIG. 3(d). In the prototype embodiment shown, the hexagonal nanowire core conduction channel is surrounded first by the insulating HfO.sub.2 layer and then by the top gate over the nanowire, which is Omega-shaped in one embodiment.

(21) The Bi.sub.2Se.sub.3 NWFET embodiment shown in FIG. 3(c) comprises substrate 1 comprised of Si. The substrate has an oxide layer 2 of thermal SiO.sub.2 disposed on an upper surface of substrate 1. A Bi.sub.2Se.sub.3 nanowire 3 is formed on the surface of oxide layer 2 opposite from the upper surface of substrate 1. Separate and spaced-apart Ti/Pt source 4 and drain 5 electrodes are patterned on surface of oxide layer 2 opposite from the upper surface of substrate 1. In this embodiment, a portion of the electrodes 4 and 5 are patterned over respective portions of nanowire 3, such that nanowire 3 is in physical contact with each electrode 4 and 5, thereby forming Schottky junctions. The longitudinal ends 3a and 3b of nanowire 3 may extend beyond the portions of electrodes 4 and 5 patterned over nanowire 3, as shown in FIG. 3(c). A dielectric material layer 6 of HfO.sub.2 is deposited over at least portions of the source 4 and the drain 5, and a length of nanowire 3 between the source and the drain. The dielectric material layer 6 is positioned such that top gate 7 is spaced apart from the oxide layer 2, nanowire 3, and electrodes 4 and 5.

(22) FIG. 4 shows a schematic structure of another embodiment of a self-aligned Bi.sub.2Se.sub.3 NWFET. The device is similar to a MOSFET in that the NWFET comprises a gate, source, drain and channel. However, the NWFET embodiment, with Bi.sub.2Se.sub.3 as the topological insulator, comprises a Bi.sub.2Se.sub.3 nanowire 3 extending along a length of substrate 1 between and in physical contact with the source electrode 4 and drain electrode 5. As shown in FIG. 4, the electrodes 4 and 5 may be patterned such that a portion of each electrode is in physical contact with a respective end portion 3x and 3y of the outer circumferential surfaces (which, in the case of Bi.sub.2Se.sub.3, form a hexagonal lattice) and end surface of nanowire 3. Additionally, as shown in FIG. 4, an intermediate portion 3z of nanowire 3 between the end portions 3x and 3y is sandwiched between a HfO.sub.2 dielectric material layer 6 and SiO.sub.2 oxide layer 2. The embodiment shown includes a top gate 7 over the nanowire 3, spaced apart from the nanowire and the electrodes 4 and 5 by the dielectric material layer 6. Given the foregoing, one of ordinary skill should understand that other topological insulator materials may be used in the NWFET.

Current-Voltage Characteristics

(23) The prototype Bi.sub.2Se.sub.3 nanowire FETs are excellent transistors. The current-voltage characteristics were measured at various temperatures ranging from 77K to room temperature. The output characteristics and transfer characteristics of Bi.sub.2Se.sub.3 nanowire FETs at 77K are shown in FIGS. 5 and 6, respectively.

(24) The prototype embodiment of a NWFET device is somewhat similar to a nMOSFET, in that both have simple but effective device structures (no source/drain junction doping). However, NWFET as described herein have numerous advantageous benefits. For instance, as seen in FIGS. 5 and 6, the NWFET had negligible contact resistance. Also, the NWFET exhibited large ON/OFF ratio, around about 109. Further, the extracted subthreshold slope (SS) from the subthreshold region of IDS-VGs was as low as 35 mV/dec.

(25) The electrical characterization was carried out on a probe station inside a vacuum chamber. As shown in FIG. 7(a), the transistor has excellent drain current (I.sub.DS) vs. top gate voltage (V.sub.GS) transfer characteristics: cutoff current close to zero, strong-inversion-like on-state current and current on/off ratio larger than 108 at a V.sub.GS swing of 1.0 V. The backside Si was grounded during all the measurements. This embodiment of a transistor has unipolar current dominated by electron conduction. This is similar to a conventional long-channel Schottky-barrier MOSFET with either electron or hole conduction determined by the unipolar Schottky junctions at the source and drain. No hysteresis was observed in the I.sub.DS-V.sub.GS curves at 77 K. A hysteresis shift was observed at higher temperatures (T>240K), most likely due to the activation of traps in the HfO.sub.2. Very similar device characteristics were observed for the drain voltage (V.sub.DS) in the range 0.05 V—4.0 V used in the study.

(26) As shown in FIGS. 7(b) and (c), the Bi.sub.2Se.sub.3 nanowire FET exhibits well-saturated, smooth I.sub.DS vs. V.sub.DS curves with negligible contact resistance. The transistor output characteristics clearly demonstrate cutoff, weak, moderate and highly conductive regions at different V.sub.GS, similar to the cutoff (leakage), weak, moderate and strong inversion regions of conventional MOSFETs. I.sub.DS saturates roughly at V.sub.DS=V.sub.GS−V.sub.th in the highly conductive region but does not saturate at V.sub.DS≈3 ϕ.sub.t in the weak/moderate conductive regions (#t=kT/q). I.sub.DS keeps increasing significantly after 3ϕ.sub.t. This means that the Bi.sub.2Se.sub.3 nanowire FET does not follow the diffusion current model as described for conventional MOSFETs. I.sub.DS in the weak/moderate conductive regions appears to be dominated by drift current.

(27) Similar I.sub.DS−V.sub.DS characteristics have been obtained at different temperatures. The saturation current I.sub.Dsat at various V.sub.GS does not follow the quadratic law which predicts that I.sub.Dsat varies linearly with (V.sub.GS−V.sub.th).sup.2 as it does in conventional long-channel MOSFETs. Rather, as shown in FIG. 7(d), I.sub.Dsat varies linearly with the over-threshold voltage (V.sub.GS−V.sub.th) at different temperatures for V.sub.GS in the range −3.8 V to −1.4 V. The saturation current can be expressed by the drift current model as a product of the number of electrons and their velocity at the source end of the nanowire:

(28) $I_{\mathrm{Dsat}}={\mathrm{Aqn}}_s{v}_s=\frac{C_{\mathrm{ox}}}{L}\left(V_{\mathrm{GS}}-V_{\mathrm{th}}\right)v_s$
where A, n.sub.s, C.sub.ox, L and v.sub.s are nanowire cross-section area, electron concentration at source end, gate capacitance, channel length and electron velocity at the source end of Bi.sub.2Se.sub.3 nanowire, respectively. Therefore this linear relationship suggests that the saturation of I.sub.DS is due to electron velocity saturation at the source end of the channel instead of pinch-off at the drain end of the nanowire channel. The slope of each I.sub.Dsat vs. (V.sub.GS−V.sub.th) curve is saturation channel conductance (g.sub.dsat)—its value at different temperatures is extracted from FIG. 7(d) and plotted in the inset, showing that the electron velocity at the source end increases linearly with decreasing temperature. The capacitance per unit length C.sub.ox/L=1.3×10.sup.−9 F/m was given by numerical calculation using a Synopsis TCAD program based on the cross-section size of the TEM image in FIG. 3(d). The calculated value of v, is from 1×10.sup.6 cm/s to 2×10.sup.6 cm/s for temperatures from 240 K to 77 K, which is of the same order of magnitude as the Fermi velocity of Ti in the source and drain contacts.

Electron Mobility

(29) FIG. 8(a) shows the electron effective mobility (μ.sub.eff) of Bi.sub.2Se.sub.3 NWFET as a function of applied gate voltage at different temperatures, which is a new aspect for Bi.sub.2Se.sub.3. The electron mobility reaches up to about 5000 cm.sup.2Ns, significantly better than conventional Si-based MOSFETs which have effective mobility of as high as about 500 cm.sup.2Ns.

(30) The field effect mobility extracted from the I.sub.DS−V.sub.GS curves shows a similar result. The effective mobility values were extracted from the linear region of I.sub.DS−V.sub.DS curves by using the following equation:

(31) $\frac{\partial I_{\mathrm{DS}}}{\partial V_{\mathrm{DS}}}={\mu }_{\mathrm{eff}}\frac{C_{\mathrm{ox}}}{L^2}\left(V_{\mathrm{GS}}-V_{\mathrm{th}}\right)$

(32) The electron effective mobility decreases with increasing gate voltage in the range 200 cm.sup.2Ns to 1300 cm.sup.2Ns at 77 K. Numerically calculated gate capacitance affects the precision of effective mobility estimation, due to the top and bottom gate coupling.

(33) In FIG. 8(b), electron effective mobility as a function of temperature at different gate voltages is plotted and fitted using μ.sub.eff˜T.sup.α. The value of a is about −1.85 at small over-threshold voltage and increases to −1.0 at large over-threshold voltage. Larger over-threshold voltage will induce higher vertical electric fields. These mobility-temperature relationships suggest that electron-phonon scattering is a dominating factor in low-field conduction (optical phonon scattering for −2.0>α>−1.5, acoustic phonon scattering for α≈−1.5), and as the gate electric field increases, interface charge Columbic scattering limits electron mobility in the Bi.sub.2Se.sub.3 nanowire FETs with α˜−1.

Transfer Characteristics

(34) FIG. 9(a) shows a comparison of the transfer characteristics FIG. 4 (a) compares the transfer characteristics (I.sub.DS−V.sub.GS) of a Bi.sub.2Se.sub.3 nanowire FET at different temperatures, all of which show unipolar, n-type, field effect behaviors. The I.sub.DS−V.sub.GS curves obtained at temperatures lower than 240 K show a clear cutoff region (I.sub.DS≈0) in the subthreshold region (V.sub.GS<V.sub.th) and a large On/Off current ratio reaching 108. The Off-state current for temperatures >240 K flattens and saturates at negative voltages much below V.sub.th. The temperature dependence of currents in the On- and Off-states are summarized in FIG. 9(b). The Off-state current for temperatures above 240 K was taken from the flat region while the On-state current was taken at V.sub.GS=2.0 V. The Off-state current starts increasing rapidly as the temperature increases above 240 K, while the On-state current keeps decreasing as the temperature increases. Such temperature dependence indicates metallic conduction in the On-state and insulating behavior in the Off-state. FIG. 9(c) shows a fitting of the strongly activated temperature-dependent current to I.sub.DS,Off=I.sub.0e.sup.−E.sup.a.sup./kT where E.sub.a is the activation energy, k is Boltzmann's constant, and I.sub.0 is a constant prefactor. The fit shows that E.sub.a is about 0.33 eV, which is very close to reported bandgap value of bulk Bi.sub.2Se.sub.3.

Analysis of Prototype NWFET

(35) The following paragraphs discuss the phenomena relating to the experimental operation of the prototype embodiment of Bi.sub.2Se.sub.3 NWFET devices. In the Off-state, the gate voltage is large enough to deplete the electrons from the nanowire. The small, temperature dependent Off-state current is due to thermal excitations across the energy band gap of the bulk of Bi.sub.2Se.sub.3. It also indicates that the electric field generated by the gate voltage below the threshold is likely to be strong enough to modify the spectrum of the nanowire and destroy the surface conduction channels. Numerical simulation has demonstrated that electric field could drive a topological insulator across a quantum phase transition to become a trivial band insulator. In contrast to conventional semiconductor nanowires, the saturated current in the On-state is linear in gate voltage, indicating metallic conduction, and is most likely flowing at the surface of the nanowire. This interpretation is also consistent with the temperature dependence of the saturated conductance. These two regimes, the surface metallic conduction and the insulating switch-off, can be controlled by a surprisingly small gate voltage (a few Volts). The data do not unambiguously confirm or rule out the presence of Helical Dirac fermions.

(36) The switching performance of a FET can be characterized by its subthreshold swing (S) which is defined as the V.sub.GS swing to achieve 10 time increase of I.sub.DS in the subthreshold region. While these Bi.sub.2Se.sub.3 nanowire FETs have a larger S value than the ideal thermodynamic limit, it is still much smaller than those often reported for nanowire-FETs based on conventional semiconductors. FIG. 9(d) shows the subthreshold swing of the Bi.sub.2Se.sub.3 nanowire FET at different temperatures and its fit to:

(37) $S=\ln 10\frac{\mathrm{kT}}{q}n=\ln 10\frac{\mathrm{kT}}{q}\left(1+\frac{C_{\mathrm{ch}-\mathrm{gnd}}}{C_{\mathrm{ox}}}+\frac{C_{\mathrm{it}}}{C_{\mathrm{ox}}}\right)$
where C.sub.ch-gnd is the capacitance between the nanowire surface and ground, and C.sub.it is interface state capacitance. It should be noted that the effect of dielectric interface states is negligible at low temperature because I.sub.DS−V.sub.GS has almost zero hysteresis (see FIG. 7(a)). From the fitting which assumes C.sub.ch-gnd/C.sub.ox has no temperature dependence, C.sub.ch-gnd is about 0.56C.sub.ox or 7.3×10.sup.−10 F/m for the Bi.sub.2Se.sub.3 nanowire.

Electromagnetic Properties

(38) The top-gated Bi.sub.2Se.sub.3 nanowire field effect transistors exhibited remarkable response to the external magnetic field. The magnetic field existed in the prototype device in direction along the nanowire axis (i.e., parallel to the x-axis). FIG. 10 shows the design of an embodiment of the prototype Bi.sub.2Se.sub.3 NWFET for examining electromagnetic properties, which is generally similar to the schematic shown in FIG. 3(c).

(39) Due to the properties of the topological insulator Bi.sub.2Se.sub.3, only the nanowire surface is still conductive (the body of the nanowire is insulating) at low temperature. Theoretically, such a conductive surface will exhibit the Aharonov-Bohm solenoid effect, in which an electrically charged particle (e.g., electron) is affected by an electromagnetic field (B). One can observe the Aharonov-Bohm effect when the wave function of an electron passing around a long solenoid experiences a phase shift as a result of the enclosed magnetic field. The Aharonov-Bohm effect exists despite the magnetic field being negligible in the region through which the electron passes and the electron's wave function being negligible inside the solenoid.

(40) The surface of topological insulator Bi.sub.2Se.sub.3 nanowire acts as a solenoid. In the presence of a magnetic field perpendicular to the cross-section of the nanowire, the electrons pass along the surface from the source end to the drain end of the FET have different path. The electron can go straight from one end to another, or make circles surrounding the nanowire before reaching the drain end. The phase of the electron wave function will shift depending on the path the electrons take. Therefore, the electrons taking different paths will have interference with each other when they meet in the end of the nanowire. The interference will lead to the oscillation in the conductance (or resistance) of the Bi.sub.2Se.sub.3 nanowire FET. The Aharonov-Bohm oscillation of the Bi.sub.2Se.sub.3 nanowire FET is shown in FIG. 11.

(41) FIG. 11 shows the Aharonov-Bohm oscillation of the Bi.sub.2Se.sub.3 NWFET measured at 4.0 K. The current first increases with increasing magnetic field from 0 T to ±2.0 T (unit is Tesla). This is due to the de-localization of electron. The current (or the conductance) of the device oscillates from 2.0 T to 9.0 T. The cosine wave curve is a fitting curve used to demonstrate the oscillation period of 2.2 T.

(42) As can be seen in FIG. 11, the current of Bi.sub.2Se.sub.3 nanowire FETs changed as the external magnetic field changed. This change can be used in applications such as magnetic field sensing. In addition, the period of the Aharonov-Bohm oscillation is also dependent on the magnitude of magnetic field. The relationship is shown in the following equation:

(43) $T_B=n\frac{h}{e}/S$
where T.sub.B is the period of Aharonov-Bohm oscillation, n is an integer, h is the Planck constant, e is the electron charge, and S is the area of Bi.sub.2Se.sub.3 nanowire cross-section. This oscillation period can be used to determine the size of the nanowire. The magnitude of the current can be used to determine the magnitude of the external magnetic field.

(44) Transistor devices as described herein have potential application in magnetic sensors. FIGS. 12(a)-12(h) show drain current I.sub.DS of an embodiment prototype NWFET measured at V.sub.DS=50 mV under a varying parallel magnetic field from −9.0 V to 9.0 V for different V.sub.GS. A negative magnetic field represents that the magnetic field direction is opposite from the current direction. The magnetoresistance can be calculated by R=V.sub.DS/I.sub.DS. As seen in FIGS. 12(a)-12(h), the magnetoresistance is strongly dependent on magnetic field in the On-state of the NWFET, while it does not change with magnetic field in the Off-state. In addition, the drain current, and therefore the magnetoresistance, is oscillating under the external parallel magnetic field, with a period of about 2.1 T. As the V.sub.GS increases, this oscillation disappears. These results indicate that the Bi.sub.2Se.sub.3 NWFETs can be used for magnetic sensors.

SUMMARY

(45) In summary, topological insulator transistors, such as the exemplary Bi.sub.2Se.sub.3 nanowire field-effect transistors described above, may be fabricated, such as by using a self-alignment technique as discussed above, and embodiments have demonstrated excellent device characteristics. The NWFETs show unipolar, n-type behavior with a clear cutoff in the Off-state with only thermally activated conduction at relatively high temperatures, and a well-saturated output current indicating surface metallic conduction. The effective mobility extracted for different gate voltages and temperatures indicates phonon scattering at low gate electric fields, i.e., electric fields at a gate voltage slightly above threshold voltage, such as about 5% to 15% above threshold voltage, and surface Columbic scattering at large gate electric fields, i.e., electric fields operating above threshold voltage, such as about 50% to 95% above threshold voltage. The achievement of sharp switching from Cutoff to surface conduction and saturation current by a gate voltage of a few volts is neither expected nor has been previously reported. The different scaling behavior of the saturation current versus gate voltage in these devices relative to most conventional semiconductor nanowire FETs may lead to novel circuit applications. Because the spin and momentum are locked in the surface states of topological insulators, the results open up the possibility of electric manipulation of spin current using gate voltage. Overall, the characteristics of embodiments of Bi.sub.2Se.sub.3 NWFETs described above demonstrate that topological insulator transistors have excellent performance, and are well-suited for numerous logic, memory and sensing applications.