INTEGRATED CIRCUIT COMPRISING AN NLDMOS TRANSISTOR AND METHOD FOR MANUFACTURING SUCH AN INTEGRATED CIRCUIT

Abstract

An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

Claims

1. An integrated circuit, comprising: a P-type semiconductor substrate; an active semiconductor substrate region having P-type conductivity; a buried semiconductor region having N+-type conductivity located underneath the active semiconductor substrate region; wherein the buried semiconductor region is more heavily doped than the active semiconductor substrate region; an additional region with N-type conductivity situated between the active semiconductor substrate region and the buried semiconductor region; wherein the buried semiconductor region is situated at an interface between the P-type semiconductor substrate and the additional region; and a semiconductor well with N-type conductivity surrounding the additional region and the active semiconductor substrate region; a drain region, of an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor, contained within said semiconductor well.

2. The circuit according to claim 1, further comprising: an NPN-type bipolar transistor; and a buried semiconductor layer having N-type conductivity located underneath the NPN-type bipolar transistor; wherein the buried semiconductor layer underneath the NPN-type bipolar transistor and the buried semiconductor region underneath the NLDMOS transistor are situated at a same depth and have a same dopant concentration.

3. An integrated circuit transistor including a source region, a body region and a drain region, comprising: a semiconductor substrate doped with a first conductivity type; a semiconductor well doped with a second conductivity type over said semiconductor substrate, wherein said semiconductor well supports said drain region; an active semiconductor substrate region doped with the first conductivity type, wherein said active semiconductor substrate region provides the body region and supports the source region; a buried semiconductor region doped with the second conductivity type and located at a level of an interface between the semiconductor substrate and the semiconductor well; an additional region doped with the second conductivity type situated between the active semiconductor substrate region and the buried semiconductor region; wherein said semiconductor well surrounds the additional region and the active semiconductor substrate region.

4. The integrated circuit of claim 3, wherein the surrounding semiconductor well and the buried semiconductor region preclude direct physical contact between the additional region and the semiconductor substrate.

5. The integrated circuit of claim 3, wherein the buried semiconductor region is more heavily doped than the active semiconductor substrate region.

6. An integrated circuit, comprising: an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor comprising: an active semiconductor substrate region having P-type conductivity; a first buried semiconductor region having N+-type conductivity located underneath the active semiconductor substrate region; and a first semiconductor well surrounding the active semiconductor substrate region; wherein the first buried semiconductor region is more heavily doped than the active semiconductor substrate region. an NPN-type bipolar transistor comprising: a second semiconductor well; and a second buried semiconductor layer having N-type conductivity located underneath the second semiconductor well; wherein the first and second buried semiconductor layers are situated at a same depth and have a same dopant concentration.

7. The integrated circuit according to claim 6, further comprising: a P-type semiconductor substrate extending under the first and second buried semiconductor layers and further extending under the first semiconductor well.

8. The integrated circuit according to claim 6, further comprising an isolation region between the first and second semiconductor wells.

9. The integrated circuit according to claim 6, wherein the NLDMOS transistor further comprises: an additional region with N-type conductivity situated between the active semiconductor substrate region and the buried semiconductor region.

10. The integrated circuit according to claim 9, further comprising: a P-type semiconductor substrate; wherein the buried semiconductor region is situated at an interface between the P-type semiconductor substrate and the additional region.

11. The integrated circuit according to claim 2, further comprising: a drain region of the NLDMOS transistor within the first semiconductor well.

12. A method for manufacturing an integrated circuit, comprising: forming an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity; forming a buried semiconductor region having N-type conductivity underneath the active semiconductor substrate region; wherein the buried semiconductor region having N-type conductivity is more heavily doped than the active semiconductor substrate region.

13. The method according to claim 12, further comprising: forming a P-type semiconductor substrate; and epitaxially forming an additional N-type region situated between the active semiconductor substrate region of the NLDMOS transistor and the buried semiconductor region underneath the active substrate region of the NLDMOS transistor; wherein the buried semiconductor region is situated at an interface between the P-type semiconductor substrate and the additional N-type region.

14. The method according to claim 13, further comprising forming the buried semiconductor region through dopant implantation.

15. The method according to claim 12, further comprising: forming an NPN-type bipolar transistor; forming a buried semiconductor layer having N-type conductivity underneath the bipolar transistor; wherein forming the buried semiconductor region underneath the bipolar transistor and forming the buried semiconductor region underneath each NLDMOS transistor are performed simultaneously.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other advantages and features of the invention will become apparent on examining the detailed description of completely non-limiting modes of implementation and embodiments and the appended drawings, in which:

[0027] FIG. 1 shows a structure of a known NLDMOS transistor;

[0028] FIG. 2 shows an integrated circuit comprising an NLDMOS transistor;

[0029] FIG. 3 shows an example of a method for manufacturing an integrated circuit such as shown in FIG. 2;

[0030] FIG. 4 shows an integrated circuit comprising an NPN-type bipolar transistor and an NLDMOS transistor 21 having a structure identical to that shown in FIG. 2; and

[0031] FIG. 5 shows an example of a method for manufacturing.

DETAILED DESCRIPTION

[0032] FIG. 2 shows an integrated circuit 20 according to one embodiment comprising an N-type laterally diffused metal-oxide semiconductor transistor, called NLDMOS transistor 21.

[0033] The NLDMOS transistor 21 is formed on a semiconductor substrate 22 having P-type conductivity. For example, the semiconductor substrate 22 has a dopant concentration of the order of 10.sup.15 at./cm.sup.3.

[0034] More particularly, the NLDMOS transistor 21 is formed in a well 24 with N-type conductivity that is incorporated into the P-type semiconductor substrate 22. For example, the well 24 has a dopant concentration of the order of 10.sup.17 at./cm.sup.3. The well 24 extends downwards from a front face 23.

[0035] More particularly, the NLDMOS transistor 21 comprises a drain region 25 with N-type conductivity. The drain region 25 is heavily doped in order to make it easier to create contact.

[0036] The NLDMOS transistor 21 further comprises an N.sup.+-doped source region 29 and a P-type active substrate region (body) 27 and a P.sup.+-doped substrate contact zone 31 formed in the active substrate region 27. For example, the active substrate region 27 has a dopant concentration of the order of 10.sup.17 at./cm.sup.3. The source region 29 and substrate regions 27, 31 are connected together by a metallization 32.

[0037] The NLDMOS transistor 21 also comprises two gate regions 33, 35 on top of the front face 23.

[0038] The integrated circuit 20 also comprises an additional region 37 with N-type conductivity, situated underneath the active substrate region 27. This additional region 37 is laterally surrounded by the well 24. More particularly, this additional region 37 has a dopant concentration of the order of 10.sup.17 at./cm.sup.3.

[0039] The additional region 37 extends downwards from the active substrate region 27 of the NLDMOS transistor 21 to a buried semiconductor region 38 with N-type conductivity, situated underneath said additional region 37. The buried semiconductor region 38 is doped with a dose of the order of 2×10.sup.19 at./cm.sup.3. The buried region 38 is therefore situated at the interface between the region 37 and the substrate 22.

[0040] The buried N.sup.+-type region 38 makes it possible to increase the triggering voltage of the stray PNP bipolar transistor effect to a level high enough not to impair high-voltage operation of the NLDMOS transistor 21. In particular, the buried N.sup.+-type region 38 makes it possible to considerably reduce the current gain of the stray PNP structure (between the active substrate region 27 of the NLDMOS transistor 21 and the P-type semiconductor substrate 22). The buried N.sup.+-type region 38, due to its high doping, is thus used to reduce the stray PNP bipolar transistor effect, or even to prevent this stray PNP bipolar transistor effect from triggering when the NLDMOS transistor 21 is used in a high side driver.

[0041] FIG. 3 shows an example of a method for manufacturing an integrated circuit 20 such as the one shown in FIG. 2. This manufacturing method comprises, after forming the well 24 in the substrate 22 in a conventional and known manner, a step 50 of forming a trench 39 in the well 24 by etching until reaching the substrate 22.

[0042] The manufacturing method then comprises a step 51 of forming the buried semiconductor region 38 by implanting dopants in the substrate 22 at the bottom of the trench.

[0043] The manufacturing method then comprises a step 52 of forming the additional region 37 through epitaxy.

[0044] The manufacturing method then comprises a step 53 of forming the source, substrate and drain regions through dopant implantation.

[0045] The manufacturing method then comprises a step 54 of forming the gate regions of the NLDMOS transistor 21.

[0046] FIG. 4 shows an integrated circuit 20 comprising an NPN-type bipolar transistor 40 and an NLDMOS transistor 21 having a structure identical to the one described in FIG. 2. In particular, the bipolar transistor 40 and the NLDMOS transistor 21 are formed on the same semiconductor substrate 22 having a common region with P-type conductivity, such as the one described above. The NLDMOS transistor 21 is separated from the bipolar transistor 40 by a deep trench isolation (DTI) 48.

[0047] The bipolar transistor 40, as is conventional, has an N.sup.+-type emitter region 44, a P.sup.+-doped extrinsic base region 43, a P-doped intrinsic base region 42, an extrinsic collector region 41 and an intrinsic collector region 45.

[0048] The bipolar transistor 40 also has a buried layer 46 situated at the interface between the intrinsic collector 45 and the underlying substrate 22.

[0049] The buried layer 46 of the bipolar transistor 40 and the buried region 38 of the NLDMOS transistor 21 are situated at the same depth with respect to a front face 23 and have the same dopant concentration.

[0050] Specifically, as illustrated schematically in FIG. 5, in step 510, the buried semiconductor layer 46 underneath the bipolar transistor 40 and the buried semiconductor region 38 underneath each NLDMOS transistor 21 are formed at the same time.

[0051] Forming the buried region 38 underneath the active substrate region 27 of the NLDMOS transistor 21 therefore does not require a dedicated additional step. Forming the buried region 38 underneath the active substrate region 27 of the NLDMOS transistor 21 is therefore inexpensive.

[0052] Furthermore, the intrinsic collector region 45 of the bipolar transistor 40 and the additional region 37 situated underneath the NLDMOS transistor 21 are formed simultaneously.