ELECTRIC DEVICE WAFER

Abstract

A device wafer comprises a silicon substrate, a piezoelectric layer arranged on and bonded to the silicon substrate and a structured metallization on top of the piezoelectric layer. The metallization forms functional device structures providing device functions for a plurality of electric devices that are realized on the device wafer. Semiconductor structures realize a semiconductor element providing a semiconductor function in the semiconductor substrate. Electrically conducting connections providing e.g. ohmic contact between the semiconductor structures and functional device structures such that at least one semiconductor function is controlled by a functional device structure or that at least one device function of the functional device structures is controlled by the semiconductor structures.

Claims

1. A device wafer with functional device structures for a plurality of electric devices, comprising a semiconductor substrate (SU) a piezoelectric layer arranged on and bonded to the semiconductor substrate on top of the piezoelectric layer, a structured metallization forming the functional device structures providing device functions for the plurality of electric devices semiconductor structures (realizing a semiconductor element and) providing a semiconductor function in the semiconductor substrate, and electrically conducting connections for providing contact between semiconductor structures and functional device structures wherein at least one semiconductor function is controlled by a functional device structure, or wherein at least one device function of the functional device structures is controlled by the semiconductor structures.

2. The wafer of claim 1, wherein the semiconductor structures are realizing a switch.

3. The wafer of claim 1, wherein the device structures and the semiconductor structures are arranged facing each other at least partly (on both sides of the piezoelectric layer) to enable an contactless interaction thereof by capacitive coupling or by an electrical field.

4. The wafer of claim 1, wherein the semiconductor structures are enabled to control a charge in a chargeable surface region of the semiconductor substrate, the chargeable surface region forming a capacitance with a functional device structure.

5. The wafer of claim 1, wherein the semiconductor structures are realizing at least one semiconductor element chosen from diode, bipolar transistor and FET.

6. The wafer of claim 1, wherein the semiconductor substrate (SU) comprises a carrier wafer (CW) of a doped silicon material, and a high-ohmic epitaxial silicon layer (EL) grown on top of the carrier wafer and having a type of conductivity inverse to that of the carrier wafer wherein the semiconductor structures and elements are realized within the epitaxial silicon layer.

7. The wafer of claim 1, wherein a first and a second semiconductor element are arranged in a surface region wherein first and second semiconductor element are isolated against each other by an isolating barrier formed as isolating bar between the two semiconductor elements or as isolating frame surrounding and enclosing one both of first and second semiconductor element wherein the barrier extends from the top surface of the silicon substrate into substrate down to a depth that is at least the depth of the bottom of the semiconductor structures wherein the barrier comprises a dielectric material buried under the surface of the substrate or a zone that is doped inversely with regard to the high ohmic epitaxial silicon layer the zone is embedded in.

8. The wafer of claim 1, enabled to apply a BIAS voltage between functional device structures and the bulk material of the substrate.

9. The wafer of the foregoing claim 8, wherein a first BIAS voltage is applied to a first functional device structure and a second BIAS voltage is applied to second functional device structure wherein first and second BIAS voltage are different such that capacitive elements of different capacitance are formed.

10. An Electric electric device with functional device structures, comprising: a semiconductor substrate (SU) a piezoelectric layer arranged on and bonded to the semiconductor substrate on top of the piezoelectric layer, a structured metallization forming the functional device structures providing device functions for the plurality of electric devices semiconductor structures (realizing a semiconductor element and) providing a semiconductor function in the semiconductor substrate; and electrically conducting connections for providing contact between semiconductor structures and functional device structures; wherein at least one semiconductor function is controlled by a functional device structure, or at least one device function of the functional device structures is controlled by the semiconductor structures, and wherein the functional device structures enable operation as a SAW device, a BAW device or a piezoelectric sensor element.

11. The electric device of claim 10, comprising a functional device structure realizing an acoustic resonator in or on the piezoelectric layer, the resonator having a static capacitance, a semiconductor element that is enabled to control a charge in a chargeable surface region of the silicon substrate to form a capacitance with a functional device structure the capacitance adding to the static capacitance wherein the resonator is enabled to be tuned in its resonance frequency by controlling the capacitance.

Description

[0034] In the following the invention will be explained in more detail by reference to specific embodiments and the accompanying figures. The figures are schematic only and not drawn to scale. Therefore, no real dimension or ratio of dimension can be taken from the figures.

[0035] FIG. 1 shows a cross-sectional view through part of a device wafer according to the art;

[0036] FIG. 2 shows a device wafer with an epitaxial layer according to an embodiment of the invention;

[0037] FIG. 3 shows a device wafer with doped wells according to another embodiment;

[0038] FIG. 4 shows a device wafer of another embodiment comprising an epitaxial layer with an isolating barrier arranged in this layer;

[0039] FIG. 5 shows a cross-sectional view through a device wafer with adjacent functional device structure for a SAW device and a BAW device as well;

[0040] FIG. 6 shows a device wafer with an epitaxial layer including doped wells therein;

[0041] FIG. 7 shows, in a top view, device structures of a device wafer that are enclosed by a barrier formed by an isolating material or doped frame-like zone;

[0042] FIG. 8 shows, in a top view, the arrangement of device structures within doped wells;

[0043] FIG. 9 shows, in a top view, a relative arrangement of a frame and device structures;

[0044] FIG. 10 shows, in a top view, a device wafer where only part of the device structures are arranged within a doped well;

[0045] FIG. 11 shows a cross-sectional view through a device wafer comprising means for applying a BIAS voltage between the device structures and the bulk material of the substrate;

[0046] FIG. 12 shows a cross-sectional view through a device wafer with an integrated capacitor that is switchable by a FET transistor realized in a silicon layer of the carrier wafer;

[0047] FIG. 13 shows a cross-sectional view through similar device wafer with an integrated capacitor that is controlled by an optically switchable transistor;

[0048] FIG. 14 shows a cross-sectional view through another device wafer with a switch and a switchable integrated capacitor;

[0049] FIG. 15 shows a cross-sectional view through a device wafer with functional device structures of a SAW device facing a space charge region in a silicon layer of the carrier wafer;

[0050] FIG. 16 shows the device wafer of FIG: 16 in a top view.

[0051] FIG. 1 shows, in a schematic cross-section, a device wafer according to the art. The device wafer comprises a carrier wafer comprising a silicon substrate SU on top of which a layer system is arranged. Such a layer system may comprise a bonding layer BL and a piezoelectric layer PL. The bonding layer may be produced directly on the silicon substrate SU and usually comprises aluminium nitride and/or silicon oxide.

[0052] Before or during applying the bonding layer measures for reducing surface charges of the silicon substrate can be made. These measures can comprise a physical treatment of the silicon substrate that is used as a carrier, or applying an additional layer for discharging the surface of the silicon substrate. Such measures are known from the art and need not be explained in more detail.

[0053] A piezoelectric layer PL is wafer-bonded on top of the bonding layer BL. The piezoelectric layer PL may be a thick wafer that is wafer-bonded to the substrate and then reduced in thickness by a grinding process or by a wafer cleavage followed by a polishing process. On top of the piezoelectric layer PL metallic device structures DS may be applied. As shown in FIG. 1, the device structures may comprise interdigital transducer electrodes of a SAW device like a SAW filter, for example.

[0054] A disadvantage of the shown device wafer is insufficient electric isolation between different device structures DS. The device structures DS to be isolated against each other are interfering with each other by capacitive coupling via charge carriers within the substrate SU. To minimize such coupling, a very low doped silicon substrate SU is necessary. As the low doped silicon material is a very clean material with a very low amount of impurities, this material is expensive.

[0055] FIG. 2 shows, in a cross-sectional view, a device wafer according to a first embodiment of the invention. In contrast to the known device wafer according to FIG. 1, the device wafer comprises a silicon substrate SU that is weakly or high doped and provides a certain amount of conductivity. On top of the silicon substrate SU a high-ohmic epitaxial layer EL is applied. Any epitaxial silicon deposition may be used to manufacture this epitaxial layer.

[0056] Silicon substrate SU and high-ohmic epitaxial layer EL may comprise dopants providing the same type of conductivity. This embodiment provides improved thermal conductivity by the doped bulk silicon substrate in view of a high purity silicon wafer. Nonetheless and in cause of the high-ohmic epitaxial layer there is the possibility to integrate semiconductor elements or simply pn junctions in the epitaxial layer.

[0057] However, to provide a space charge region between epitaxial layer EL and silicon substrate SU, different doping is used for both layers. For example, the silicon substrate SU may have a n+ doping. The epitaxial layer may then be low conductive and, for example p− doped.

[0058] The piezoelectric layer PL may be a lithium tantalate layer, for example. But any other piezoelectric material is useful for the invention. The piezoelectric layer may have a relatively low thickness of about two times the acoustic wavelength the device is working with. Thicker piezoelectric layers of e.g. fpm thickness working at a frequency between 800 MHz and 2.6 GHz are possible too. The epitaxial layer thickness may be in the same order. But a higher or lower thickness or may be possible too. In the course of the pn junction between epitaxial layer EL and silicon substrate SU a space charge region forms that isolates the two layers against each other by forming a respective barrier.

[0059] FIG. 3 shows a schematic cross-section of further embodiment. In this example a very low doped silicon substrate SU is used, for example, an n− doped silicon. Near the surface and directly under a group of device structures DS a doped well DW is formed by implanting therein a dopant that provides a conductivity of the contrary type. In the example the doped wells comprise a p− doping. With these doped wells a pn junction is formed at the interface of the doped well and the silicon substrate. A space charge region forms and provides a barrier that prevents charge carriers to leave the doped well. Hence, the doped well provides a perfect isolation of the region opposite to the device structures such that device structures that have to be isolated against each other are arranged opposite to separate and different doped wells DW.

[0060] FIG. 4 shows in a cross-sectional view the method to further improve the isolation between different device structures DS that may be present in a device wafer as shown in FIG. 2. In addition to the pn junction between epitaxial layer EL and silicon substrate SU an isolating frame IF is formed as a barrier within the epitaxial layer EL. The isolating frame IF extends from the top surface of the epitaxial layer EL to the top surface of the silicon substrate SU. It may be manufactured by forming a trench, for example by etching, and then filling up the trench with an isolating material like silicon oxide for example. Any other dielectric may be possible too.

[0061] The filling of the trenches may be accomplished by applying an isolating dielectric to the entire surface of the epitaxial layer before forming the bonding layer BL. The isolating layer is applied in a thickness that is sufficient to totally fill the trenches. Then the surface may be planarized by grinding or back-etching such that a plane surface remains. Alternatively the trench can remain unfilled to provide an air-filled isolating trench. In this case, it may be advantageous to form the trench during manufacturing of the carrier wafer as a last step before bonding the piezoelectric wafer to the carrier wafer.

[0062] The isolating frame IF surrounds a surface region that faces device structures DS to be isolated against other device structures. The same isolating material filling the trench may be used in parallel to form a bonding layer BL for improving the bonding strength between carrier wafer and piezoelectric layer.

[0063] Alternatively, a bonding layer BL is applied separately on top of the carrier wafer in a usually known manner. Then the piezo layer PL is applied on top of the bonding layer BL and device structures DS are formed on top of the piezoelectric layer. In this embodiment the surface region of the epitaxial layer EL opposite to a group of device structure DL is isolated against the silicon substrate SU by the pn junction between epitaxial layer and silicon substrate. In case the surface region is embedded in a doped well a further pn junction at the periphery of the doped well provides further improved isolation. In any case, adjacent types of device structures DS are isolated against each other by the isolating frame IF.

[0064] In a variant also depicted in FIG. 4 the barrier DF comprises a doped zone DF that may be formed frame-like. Alternatively, the barrier may extend linearly between two surface regions of the substrate to be isolated against each other.

[0065] The dopant used in the doped zone DF is of contrary type to the dopant used in the remaining epitaxial layer EL such that a pn junction is formed between the low doped epitaxial layer EL and the doped frame-like zone DF. In this example, the doped zone DF may be n.sup.+ doped. The doping may comprise applying a doping mask on top of the epitaxial layer EL before diffusing in or implanting the dopant and before applying the bonding layer BL. In the doping mask only those regions are exposed where the doped zone DF is to be produced.

[0066] In a further embodiment according to FIG. 5 device structures forming two different types of devices are present on top of the piezoelectric layer PL. First device structures DS1 realize a SAW device schematically depicted as a cross-section through an interdigital transducer. Second device structures DS2 realize two top electrodes of a two series-connected BAW devices that may be arranged directly adjacent to the SAW device. The common counter electrode of the two series BAW resonators is not a metal electrode but a doped well DW within the silicon substrate or within the epitaxial layer (not shown in the figure) opposite to the second device structures DS2. The doped well may be n.sup.+ doped while the substrate is p.sup.− doped. Alternatively the epitaxial layer is p.sup.− doped while the silicon substrate is n.sup.− doped.

[0067] In an embodiment according to FIG. 6 an isolation inverse to the embodiment shown in FIG. 4 is used. While the embodiment of FIG. 5 uses doped zones as a barrier between surface regions, FIG. 6 provides doped wells formed in a surface region within the epitaxial layer EL. This is similar to the embodiment of FIG. 3 with the advantage that the weakly doped and low conductive epitaxial layer EL has only a small thickness over a silicon substrate SU that may be strongly doped. Besides the pn junction between epitaxial layer EL and silicon substrate SU, a further pn junction is formed between the doped wells and the remaining area of the epitaxial layer outside and surrounding the doped wells DW.

[0068] While in the embodiment of FIG. 4 a frame-like zone DF is doped and the epitaxial layer remains un-doped, FIG. 6 provides an embodiment where the region opposite to the device structures is conductive and the remaining epitaxial layer is low conductive.

[0069] FIG. 7 shows in a top view onto a device wafer how different device structures DS can be isolated against each other. As a device structure DS, acoustic tracks AT of a SAW device are formed. By a barrier like isolating frames IF or doped zones DF different areas of the carrier wafer may be isolated against each other. Each isolated area may comprise one or more device structures like acoustic tracks AT as shown in the embodiment. While the area shown on the left side of the figure comprises three acoustic tracks AT surrounded by an isolating frame IF or a doped zone DF, the area shown in the middle of the figure comprises two acoustic tracks AT within one enclosing barrier and in the area shown on the right side of the figure only one acoustic track each is surrounded by a respective isolating frame IF or frame-like doped zone DF.

[0070] The isolating frames are formed and arranged between device structures DS that have to be isolated against each other.

[0071] These may be for example between interdigital transducer electrodes of an input transducer and an output transducer. It is also possible to use this kind of isolation to separate parts within a track from each other, e.g. in DMS structures (IN vs. OUT), to isolate parts of MPR filters (multi-port resonator) or to separate parts of cascaded resonators (e.g. frame/trench below “bus-bar” between tracks of a cascade).

[0072] FIG. 8 is a top view onto a device wafer according to the embodiment shown in FIG. 3 or FIG. 6. The figure shows how the doped wells DW may be arranged within the surface of the silicon substrate SU or the epitaxial layer EL. Similar to the embodiment of FIG. 7, several device structures like acoustic tracks AT may be arranged within one doped well DW. Different doped wells DW may comprise a different number of device structures as shown. Accordingly, the doped wells may comprise different surface areas.

[0073] FIG. 9 shows another arrangement of isolating frames IF or doped frame-like zones DF in a top view on a device wafer according to the invention. On the left side, a frame surrounds and isolates a number of device structures like acoustic tracks AT. Two other acoustic tracks shown in the middle of the figure do not need to be surrounded by a frame, but are isolated against the acoustic tracks on the right part of the figure by a non-surrounding barrier zone that is formed linearly as a bar like barrier to isolate the not-surrounded device structures against the surrounded and non-surrounded device structures on the right side. As shown in FIG. 9, barriers formed as surrounding frames and linearly extending isolating zones may be present on the same device wafer. But it is also possible that only linearly extending isolating zones are necessary to isolate different regions on top of the silicon substrate, each region being opposite to one or more device structures that need to be isolated against other device structures.

[0074] FIG. 10 shows another possibility to arrange doped wells DW in a silicon substrate SU or an epitaxial layer EL according to the embodiments shown in FIGS. 3 and 6. In FIG. 10 two doped wells DW comprise at least one device structure that is at least one acoustic track AT. Other acoustic tracks AT are arranged outside the doped wells DW. In spite of not being arranged in the doped well, the device structures or acoustic tracks AT shown in the left part of FIG. 10 are isolated against the device structures arranged in a doped well by virtue of the pn junction between the doped well and the remaining un-doped area outside the doped well DW.

[0075] FIG. 11 shows a cross-section of a device wafer according to another embodiment. A space charge region is formed as a depletion region due to an applied DC BIAS voltage VDC. The BIAS voltage is applied between device structures DS and the bulk material of the silicon substrate SU, for example by applying a metallized area on the bottom surface of the silicon substrate SU. Because of the BIAS voltage, charge carriers enrich in a zone EZ opposite to the device structures DS the BIAS voltage is applied to. As a result, enhanced conductivity in the enriched zone EZ opposite to the device structures DS is achieved and a capacitance CAP forms between the device structures DS and the enriched region opposite thereof in the upper surface of the silicon substrate. This capacitance may add to the static capacitance of the device the device structures belong to. By varying the capacitance of the device, properties thereof may be changed. As a consequence of an enhanced static capacitance of an interdigital transducer electrode, the resonance frequency thereof may be tuned. But every other property that is dependent on a capacity may be tuned by such a DC BIAS voltage too.

[0076] Applying an inverse bias voltage may lead to a depleted zone below the device structure reducing the capacitance in this region and thus, resulting in the same effect of tuning resonance frequency.

[0077] FIG. 12 shows a cross-sectional view through a device wafer with a capacitor integrated within the epitaxial layer EL. The capacitor is switchable by a FET transistor that is also realized in the epitaxial silicon layer of the carrier wafer. Electrodes of the FET transistor for source E2, drain E1 and gate GE are formed by the structured metallization on top of the piezoelectric layer PL functioning as an isolating layer. The capacitor electrodes are formed by the drain terminal E1 and the drain region D below E1. As the drain region has no electrical connection it is a floating electrode the potential thereof being controlled by the transistor's gate electrode GE. However, source and drain may be interchanged that the capacitor is formed by the source electrode E2 and the source S itself. Transistor and capacitor are series circuited.

[0078] A bonding layer may be present at the interface between piezoelectric layer PL and epitaxial silicon layer EL that is isolating too. Hence, the electrode E2 for the source needs an ohmic contact through the isolating layer. This contact can be formed by a via, a through contact TC or any other conducting structure. Source S and drain D itself are highly doped zones in the epitaxial layer EL directly facing the respective electrodes E1 and E2. The highly doped zones may be n.sup.+ doped wells in the p.sup.− doped epitaxial layer EL. The drain electrode El is not in direct electrical contact with the drain D. Hence, a capacitor forms between electrode E1 and drain as soon as the transistor works and charges the drain D with charge carriers. Loading of the drain is enabled by applying a positive potential to the gate electrode for forming an n-conducting channel CH under the gate electrode GE.

[0079] The drain electrode E1 may be a part of the functional device structures DS of the device wafer. Then, the capacitance that is switchable by the transistor can co-operate with the device for example by adding to the static capacitance of the functional device e.g. a SAW resonator.

[0080] In the figure, the transistor is isolated by a frame-like barrier IF as shown in FIGS. 4, 7 and 9 surrounding source S, drain D and channel CH of the transistor.

[0081] FIG. 13 shows a cross-sectional view through similar device wafer having an integrated capacitor switchable by a FET transistor. Instead of applying a voltage to a gate electrode like at the transistor of FIG. 12 the conducting channel CH of FIG. 13 can be enabled by light. Absorbance of light in the region of the channel CH between source S and drain D within the epitaxial layer EL induces charge carriers, forms a conducting channel CH and allows to charge the drain D if a voltage is applied over the electrodes E1 and E2 for source and drain.

[0082] An optional optical filter OF enables the transistor to be switched by light of a selected wavelength that may pass the optical filter OF. Using different optical filters OF with a different passband frequency each allows to selectively switch a desired transistor by selecting a respective wavelength of light that can pass the respective optical filter OF.

[0083] In FIG. 13 the optical filter is embodied as a layer on top of the piezoelectric layer PL. Alternatively, the optical filter OF as well as the electrodes of the transistor may be buried at a desired depth within the device wafer. These buried contacts may be in contact with no, one or more than one electrode on the top side by vias TC.

[0084] FIG. 14 shows a cross-sectional view through another device wafer with a switch formed by an integrated FET transistor and a switchable integrated capacitor. Instead of a via to the top side the drain region D may be contacted by via or any other contact means to the bulk material of the silicon substrate SU. Hence, the silicon needs to be provided with a backside or bulk contact BC. It may be advantageous to place the bulk contact BC opposite to the transistor zone to be contacted.

[0085] FIG. 15 shows a cross-sectional view of a device wafer with functional device structures DS of a SAW device facing a space charge region SCR in a silicon layer of the carrier wafer. The space charge region forms when a DC BIAS voltage is applied between device structures DS and a bulk contact BNC at the bottom side of the silicon substrate SU as already shown and explained with reference to FIG. 11. As a further advantageous feature the space charge may be modulated by a buried contact BUR within the space charge region that is at or near the top surface of the epitaxial silicon layer EL.

[0086] The dimension of the space charge region SCR depends on the BIAS voltage between device structures DS and bulk contact BC. The buried contact may be a floating contact or may be in electrical contact the bulk contact or any metal contact at the top surface of the piezoelectric layer. The space charge region SCR and device structures DS form a capacitance for modifying a property of the functional device.

[0087] Alternatively, the space charge region may be formed by means of light the top surface is irradiated with. As explained before a wavelength that is absorbed in the epitaxial layer is chosen. Using a radiation of higher energy is possible too.

[0088] FIG. 16 shows the device wafer of FIG. 16 in a top view. The device is a SAW device and the depicted device structure DS is a SAW transducer which may be part of a SAW resonator. The space charge region SCR is located under the transducer that a capacitance there between can form.

[0089] As the depicted transducer comprises two electrodes TE1, TE2 electrically isolated against each other, the BIAS voltage may be applied to one of the two electrodes or to both electrodes. The capacitance that forms between electrode and space charge region SCR has only minor dependence onto whether one or two electrodes are biased.

[0090] The invention has been explained and depicted with reference to a limited number of embodiments and figures. However the scope of the invention and is hence not restricted to the embodiments. As in most figures only one a single aspect of the invention is shown, it is within the scope of the invention to combine different features shown in different figures. Hence, it is possible to combine a doped well and an isolating or a doped frame. Further, each lateral structuring may be done within an epitaxial layer or within the silicon substrate alternatively or additionally. But in each most cases photolithography, epitaxial deposition or doping processes or combinations of them needed before wafer bonding. Other manufacturing steps of structuring and/or doping the carrier wafer may alternatively be done after wafer bonding. E.g. ion implanting can be done through any barrier layer or other layer to form structures at a depth within the wafer that is depended on the implanting energy e.g. the ion accelerating field. Another step may use the transparency of the piezoelectric layer for a range of wavelengths such that a laser can be used to specifically form a structure that is buried under a covering layer. These buried structures can comprise isolating trenches or any other discontinuity within the carrier wafer.

LIST OF REFERENCE SYMBOLS

[0091] AT acoustic track [0092] BC bulk contact [0093] BUR buried contact [0094] CAP capacitance [0095] CH channel [0096] CW carrier wafer [0097] D drain [0098] DF barrier comprising a dielectric material [0099] DS functional device structures [0100] DW doped zone [0101] E1, E2 transistor electrode [0102] EL high-ohmic epitaxial silicon layer [0103] GE gate electrode [0104] IF isolating frame [0105] OF optical filter [0106] PL piezoelectric layer [0107] S source [0108] SCR space charge region [0109] SR surface region [0110] SU silicon substrate [0111] TC through contact, via [0112] TE transducer electrode