Small form factor pluggable unit with wireless capabilities

Abstract

The present subject matter relates to one or more devices, systems and/or methods for providing wireless telecommunication services. A Small Form Factor Pluggable Unit (SFP) incorporates wireless capabilities, and includes an integrated or an external antenna. The SFP comprises wireless circuitry for transmitting and receive multiple and distinct wireless signals, including Wi-Fi and Bluetooth for communicating with various equipment and/or devices.

Claims

1. A small form-factor pluggable SFP device comprising: an SFP housing; a printed circuit board in the SFP housing having wireless communication circuitry, wherein the wireless communication circuitry comprises a wireless SoC chip; and one of a wireless communication antenna on the printed circuit board or a wireless communication antenna connector operatively associated with the printed circuit board; wherein the wireless communication circuitry defines at least one wireless communication channel for transmission and receipt of at least one type of wireless signal.

2. The device of claim 1, wherein the antenna is an etched antenna on the printed circuit board.

3. The device of claim 1, wherein the antenna connector is a Coax connector.

4. The device of claim 1, wherein the antenna connector is a USB connector.

5. The device of claim 1, wherein the circuitry includes power supply circuitry.

6. The device of claim 1, wherein the circuitry includes at least one status indicator having a color and a cadence for providing status information on the SFP device and the at least one wireless communication channel.

7. The device of claim 6, wherein the at least one status indicator is a tri-color LED.

8. The device of claim 1, wherein the circuitry includes a microprocessor.

9. The device of claim 1, wherein the circuitry includes a memory.

10. The device of claim 1, wherein the circuitry includes a field programmable gate array (FPGA) having serializer and deserializer circuitry.

11. The device of claim 10, wherein the FPGA comprises an Ethernet MAC, an Ethernet precision timing circuitry, an Ethernet OAM circuitry, security circuitry, a wireless SoC host interface, and a processor.

12. The device of claim 1, wherein the circuitry includes clock and timing circuitry.

13. The device of claim 1, further comprising a back interface connector.

14. The device of claim 1, wherein the wireless SoC chip comprises a processor, a wireless sub-system, a Bluetooth sub-system, a wireless SoC host interface, and peripheral modules.

15. The device of claim 1, wherein the wireless SoC chip includes a wireless sub-system defining a first communication channel for the transmission and receipt of Wi-Fi signals, and a Bluetooth sub-system defining a second communication channel for the transmission and receipt of Bluetooth signals.

16. A wireless telecommunication system comprising: at least one network interface device having at least one SFP port; at least one small form-factor pluggable SFP device connected to the at least one SFP port of the at least one network interface device, the at least one SFP device having wireless communication circuitry and an associated antenna, wherein the wireless communication circuitry comprises a wireless SoC chip; wherein the wireless SoC chip defines at least one wireless communication channel for transmission and receipt of at least one type of wireless signal; and at least one communication device in wireless communication with the at least one SFP device via the at least one wireless communication channel; wherein the small form-factor pluggable device takes the place of and eliminates the need for a wireless router.

17. The system of claim 16, wherein the wireless SoC chip includes a wireless sub-system defining a first communication channel for the transmission and receipt of signals, and a Bluetooth sub-system defining a second communication channel for the transmission and receipt of Bluetooth signals.

18. The system of claim 16, wherein the wireless communication circuitry further comprises a includes a field programmable gate array (FPGA) having serializer and deserializer circuitry.

19. A method for providing a wireless communication service, comprising the steps of: providing wireless communication circuitry comprising a wireless SoC chip in a small form-factor pluggable SFP device; defining at least one wireless communication channel via at least one of a wireless sub-system and a Bluetooth sub-system on the wireless SoC chip; providing an antenna for the wireless communication circuitry; plugging the small form-factor pluggable SFP device into a network interface device; and communicating wireless signals between a wireless device and the SFP device.

20. The method of claim 19, further comprising the step of performing remote monitoring, testing and provisioning of the wireless communication service through the SFP device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The drawing figures depict one or more implementations in accord with the present teachings, by way of example only, not by way of limitation. In the drawing figures, like reference numerals refer to the same or similar elements.

(2) FIG. 1 is schematic diagram of a prior art telecommunication system for providing wireless service.

(3) FIG. 2 is a schematic diagram of a telecommunication system for providing wireless service via the wireless SFP of the present disclosure.

(4) FIG. 3A is a schematic diagram of a prior art telecommunication system using cables and connectors to communicate with equipment.

(5) FIG. 3B is a schematic diagram of a prior art telecommunication system using alternate cables and connectors to communicate with equipment.

(6) FIG. 4 is a schematic diagram of the telecommunication system of FIG. 2, illustrating the use of a secondary wireless technology to communicate with equipment.

(7) FIG. 5A is a top front perspective view of the wireless SFP of the present disclosure with an integrated antenna with the housing partially removed to illustrate internal components and internal PCB antenna.

(8) FIG. 5B is a top front perspective view of the wireless SFP of FIG. 5 with its housing.

(9) FIG. 5C is a bottom back perspective view of the wireless SFP of FIG. 5 with its housing.

(10) FIG. 6 is a perspective view of the wireless SFP of the present disclosure with a coaxial connector to attach an external antenna with a coaxial connector.

(11) FIG. 7 is a perspective view of an external antenna with a coaxial connector and a coax cable attachment for use with the wireless SFP of FIG. 6.

(12) FIG. 8 is a perspective view of the wireless SFP of the present disclosure with a USB connector to attach an external antenna with a USB connector.

(13) FIG. 9 is a perspective view of an external antenna with a USB connector for use with the wireless SFP of FIG. 8.

(14) FIG. 10 is a schematic diagram of the printed circuit board of the wireless SFP of FIG. 5A, and illustrating the wireless SFP circuitry of the present disclosure.

(15) FIG. 11 is a schematic diagram of the printed circuit board of the wireless SFP of FIG. 6, and illustrating the wireless SFP circuitry.

(16) FIG. 12 is a schematic diagram of the printed circuit board of the wireless SFP of FIG. 8, and illustrating the wireless SFP circuitry.

(17) FIG. 13 is a schematic diagram of the wireless SoC chip of FIGS. 10-12.

(18) FIG. 14 is a table describing the functionality of the wireless SFP of the present disclosure using a light emitting diode (LED).

(19) FIG. 15 is a schematic diagram of the wireless SFP field programmable gate array (FPGA) of FIGS. 10-12.

(20) FIG. 16 is a schematic diagram illustrating a method of the present disclosure of Wi-Fi triangulation and Bluetooth communications involving three wireless SFPs and mobile devices.

DETAILED DESCRIPTION

(21) The following description refers to numerous specific details which are set forth by way of examples to provide a thorough understanding of the relevant method(s), system(s) and device(s) disclosed herein. It should be apparent to those skilled in the art that the present disclosure may be practiced without such details. In other instances, well known methods, procedures, components, hardware and/or circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present disclosure. While the description refers by way of example to wireless SFP devices and methods and systems, it should be understood that the method(s), system(s) and device(s) described herein may be used in any situation where wireless telecommunication services are needed or desired.

(22) As illustrated in FIG. 2, the wireless SFP device of the present disclosure replaces the Wi-Fi router, the SFP device in the NID, and the associated cabling and mounting hardware depicted in prior art FIG. 1. Due to the wireless SFP device conformance to applicable SFF specifications, the wireless SFP device can be installed and deployed by any equipment which supports SFP devices. In doing so, this allows any SFP supported equipment the added ability to provide wireless service. Further, the wireless SFP device of the present disclosure also simplifies the deployment and installation of wireless service by simply inserting the wireless SFP device into any equipment which supports SFP devices.

(23) Unlike the wired systems of prior art FIG. 3, a method and system of the present disclosure employs the use of a secondary wireless technology to communicate with equipment, as illustrated in FIG. 4. Accordingly, the wireless SFP of the present disclosure uses wireless as additional technologies to communicate with devices. This additional wireless technology will be different than the Wi-Fi wireless technology, which Wi-Fi used as the primary data transport for the network. There may be two or more wireless technologies used to communicate with other mobile and wearable devices.

(24) Wi-Fi, Bluetooth, and Zigbee wireless technologies represent wireless technologies which one, two, or all these technologies will coexist. Bluetooth is a wireless technology standard for exchanging data over short distances using short-wavelength UHF radio waves in the ISM band from 2.4 to 2.485 GHz. Bluetooth is typically used as a secondary wireless communication method of mobile devices. The Wi-Fi and Bluetooth technologies incorporated into the wireless SFP of the present invention allows for the provision of location and tracking of the wireless SFP, such that it is readily available or accessible during wireless service outage or maintenance. The Wi-Fi and Bluetooth will also provide the infrastructure to manage and track mobile and wearable devices through indoor positioning systems.

(25) The additional wireless technology may use a single antenna for coexistence of all wireless technologies, as shown in FIG. 4. The method and systems of the present disclosure will support multiple antennas to enhance the performance of the wireless technologies.

(26) FIGS. 5A-9 illustrate a number of embodiments of the wireless SFP and associated antenna. The wireless SFP can support multiple wireless services, such as Wi-Fi, Bluetooth, Zigbee, and others. The associated antenna can be integrated in the wireless SFP device, or can be connected via a suitable connector.

(27) For example, the antenna may be etched on a printed circuit board (PCB) internal of the SFP. FIGS. 5A-5C illustrate such an integrated, internal PCB antenna. In this embodiment, a connector for an external antenna is not needed and thus is eliminated.

(28) In another embodiment, the wireless SFP includes a coax connector to support an external antenna. FIG. 6 illustrates the wireless SFP with such a coax connector. FIG. 7 illustrates an external antenna having a coaxial connector. The external antenna can be connected to the coax connector on the wireless SFP via a coax cable attachment as depicted therein.

(29) In an alternate embodiment, the wireless SFP includes a USB connector to support an external antenna. FIG. 8 illustrates the wireless SFP with such a USB connector. FIG. 9 illustrates an external antenna having a USB connector. The external antenna can be connected to the USB connector on the wireless SFP by plugging the complementary USB connector on the external antenna into the USB connector on the wireless SFP.

(30) FIG. 10 is a schematic diagram of the printed circuit board of the wireless SFP with internal antenna, and illustrating the wireless SFP circuitry. As can be seen, the wireless SFP circuitry includes (1) a wireless system on chip (SoC), (2) power supply circuitry, (3) one or more LEDs, (4) a microprocessor, (5) memory, and (6) a field programmable gate array (FPGA). The PCB also includes clock and timing circuitry, Antenna circuitry and an etched antenna. A back interface connector of the wireless SFP unit is also schematically illustrated, for connection to internal components of the network system when plugged into the chassis.

(31) FIG. 11 is a schematic diagram of the printed circuit board of the wireless SFP with external coax antenna, and illustrating the wireless SFP circuitry. As can be seen, the wireless SFP Circuitry includes (1) a wireless system on a chip (SoC), (2) power supply circuitry, (3) light emitting diode (LED), (4) microprocessor, (5) memory, and (6) a field programmable gate array (FPGA). The PCB also includes clock and liming circuitry, Antenna circuitry and external coaxial connector for connection with an external antenna. A back interface connector of the wireless SFP unit is also schematically illustrated, for connection to internal components of the network system when plugged into the chassis.

(32) FIG. 12 is a schematic diagram of the printed circuit board of the wireless SFP with external USB antenna, and illustrating the wireless SFP circuitry. As can be seen, the wireless SFP circuitry includes a (1) wireless system on a chip (SoC), (2) power supply circuitry, (3) light emitting diode (LED), (4) microprocessor, (5) memory, and (6) a field programmable gate array (FPGA). The PCB also includes clock and timing circuitry, Antenna circuitry and external USB type connector for connection with an external antenna. A back interface connector of the wireless SFP unit is also schematically illustrated, for connection to internal components of the network system when plugged into the chassis.

(33) These components of the wireless SFP are described in more detail as follows:

(1) SoC Description

(34) The wireless SFP utilizes a wireless SoC, which is a highly integrated circuit incorporating a (1a) processor, (1b) wireless sub-system, (1c) Bluetooth sub-system, (1d) host interface, and (1e) peripheral modules. The wireless SoC also includes a memory and a switch. FIG. 13 is a schematic diagram of the wireless system on a chip (SoC).

(1a) SoC Processor

(35) The wireless SoC processor is a 32-bit ARM Cortex type processor which offers high CPU performance and is optimized for low interrupt latency, low power consumption, in a very small size. The processor provides protocol processing for the Wireless and Bluetooth sub-systems. The processor also provides other general status and maintenance tasks.

(1b) SoC Wireless Sub-System

(36) The SoC wireless sub-system includes an 802.11 a/b/g/n/ac radio, physical layer interface (PHY), and media access controller (MAC). The radio is a dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz. The radio provides communications for applications operating in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands. The wireless PHY provides signal processing, modulation and decoding of the received signal from wireless medium. The wireless MAC controls the access to the wireless PHY and mediates data collisions. The wireless MAC are comprised with transmit and receive controllers, transmit and receive FIFOs to buffer sending and receiving data, and circuitry to manage the RF system and the wireless PHY. The SoC wireless sub-system will interface to the antenna either through an antenna connector or without the antenna connector by means of an antenna etched on an extended PCB. The etch PCB antenna can achieve performance of 2 dB with minimal increase in the wireless SFP size. The use of an external antenna can achieve performance of 5 dB and the flexibility to position the external antenna by mean of a coaxial cable, as discussed above.

(1c) SoC Bluetooth Sub-System

(37) The SoC Bluetooth sub-system also includes an integrated Bluetooth radio and baseband core. The Bluetooth radio and baseband core is optimized for use in 2.4 GHz to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and EDR specification and meets or exceeds the requirements to provide the highest communication link quality. Bluetooth Baseband Core (BBC) implements all of the time critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it, handles data flow control, schedules transactions, monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes packets and events. To manage wireless medium sharing for optimal performance, an external coexistence interface (switch) is provided that enables signaling between the one or two external collocated wireless devices such as Bluetooth.

(1d) SoC Host Interface

(38) The SoC host interface supports SDIO circuitry for high speed data transfer from the wireless sub-system to the wireless SFP FPGA circuitry. The invention supports SDIO version 3.0, 4-bit modes (200 Mbps). The SoC host interface may also support an Ethernet RMII/GMII/RGMII/SGMII circuitry for 10/100/1000BASE-T and XAUI 10GBASE-T high speed data transfer.

(1e) SoC Peripheral Modules

(39) The SoC peripheral modules support general purpose input and output control pins and serial communications to external devices.

(2) Power Supply Circuitry Description

(40) The wireless SFP power supply circuitry is comprised of linear dropout and switching regulators to provide power to the wireless SoC, FPGA, processor, memory, and clock timing blocks. A power supervisor circuitry ensure proper power-up sequencing for hot-insertions and power brownout conditions.

(3) LED Description

(41) FIG. 14 is a table describing the functionality of the wireless SFP using a light emitting diode (LED). The wireless SFP LED can communicate information on the wireless SFP. In this present disclosure, the wireless SFP has a single tri-color LED to communicate status information on the wireless SFP system and both wireless communication technology. The present disclosure will use Wi-Fi and Bluetooth as the first and second wireless technology, respectively. When LED is emitting a steady green color, the wireless SFP is normal. Wi-Fi is linked and Bluetooth is idle. When the LED is only emitting a blinking green color, the Wi-Fi is communicating with other wireless devices while the Bluetooth communication is idle. When the LED is emitting only a steady blue color, the Bluetooth is linked while the Wi-Fi is idle. When the LED is emitting only a blinking blue color, the Bluetooth is communicating with other wireless devices while the Wi-Fi is idle. If the LED is blinking green and blue with a 1 second cadence, the Wi-Fi and Bluetooth are both linked and communicating with their respective wireless devices. When LED is emitting a steady amber color, the wireless SFP is in test or maintenance mode, with wireless disabled. When LED is emitting a blinking amber color, the wireless SFP is in provisioning or upgrade mode. When LED is not emitting any color, there is no power or the wireless SFP is not operational. In is foreseen that the LED(s) will be able to communication data and information using very high frequency pulses such as Li-Fi technology. It is also contemplated that more than one LED may be used to indicate these and other features/status of the wireless SFP.

(4) Microprocessor Description

(42) The microprocessor is an ARM Cortex processor system with the responsibility of managing and assisting the wireless SoC, the LED, and the FPGA. Additional responsibility of the microprocessor is to communicate to the host interface the SFP digital diagnostics monitoring per SFF-8472.

(5) Memory Description

(43) The wireless SFP memory sub-system is comprised of ROM and RAM memory blocks. The ROM und RAM memory blocks will provide data software program and data storage and operation. The Flash ROM will also provide storage to mirror the software program. Mirroring will allow the wireless SFP to have remote software upgrades and provisioning.

(6) FPGA Description

(44) The wireless SFP FPGA provides the following sub-systems, an (6a) Ethernet MAC, an (6b) Ethernet precision timing circuity, an (6c) Ethernet OAM (operation, administration, maintenance) circuity, (6d) security circuity, a (6e) host interface, and a (6f) processor. The FPGA also includes a memory and seriailizer and deserializer circuitry. FIG. 15 is a schematic diagram of the wireless SFP field programmable gate array (FPGA).

(6a) Ethernet MAC Description

(45) The Ethernet MAC provides optional protocol processing of the data from the host interface. The MAC sublayer provides addressing and channel access control mechanisms. The Ethernet MAC functionality may be bypassed for customer applications, such as performing test, maintenance, or network architecture applications. The Ethernet MAC controller can transmit and receive data at 10/100/1000 Mbs. It is foreseen that the Ethernet MAC could support 10 G, 40 G, and 100 Gbs as well.

(6b) Ethernet Precision Timing Description

(46) The Ethernet precision timing block provides IEEE 1588v2 and SyncE functions. IEEE 1588v2 is a standard that defines a Precision Time Protocol (PTP) used in packet networking to precisely synchronize the real Time-of-Day (ToD) clocks and frequency sources in a distributed system to a master ToD clock, which is synchronized to a global clock source. The Ethernet precision time block provides IEEE1588 and SyncE functionality. IEEE1588 standard defines the Precision Time Protocol (PTP) that enables precise synchronization of clocks in a distributed network of devices. The PTP applies to systems communicating by local area networks supporting multicast messaging. This protocol enables heterogeneous systems that include clocks of varying inherent precision, resolution, and stability to synchronize. In both the transmit and receive directions 1588 packets are identified and timestamped with high precision. Software makes use of these timestamps to determine the time offset between the system and its timing master. Software can then correct any time error by steering the device's 1588 clock subsystem appropriately. The device provides the necessary I/O to time-synchronize with a 1588 master elsewhere in the same system or to be the master to which slave components can synchronize.

(6c) Ethernet OAM Description

(47) The Ethernet OAM provides link and service OAM functionality per MEF and ITU Y.1731. The Ethernet OAM supports the service activation test loopback of ITU Y.1564 and RFC2544. Link OAM per IEEE 802.1ag. The Ethernet OAM support latching loopback per MEF46.

(6d) Ethernet Security Description

(48) The Ethernet security implements the DES and Triple-DES (3DES) encryption standards, as described in NIST Federal Information Processing Standard (FIPS) publication 46-3, incorporated herein by reference. Each encryption type offers a compromise between service application speed, FPGA logic area, and customer application. The Data Encryption Standard (DES) is a 64-bit block cipher which uses a 56-bit key to encrypt or decrypt each block of data. Given the short key length, DES has been proven to be susceptible to brute force attacks and so is no longer considered secure for general use. Triple-DES (3DES) strengthens the security by combining three DBS operations; an encrypt, a decrypt, and a final encrypt; each using a 56-bit key. This increases the effective key length, improving security. However, latterly 3DES has been superseded by the faster Advanced Encryption Standard (AES) algorithm, although it still finds use in security protocols such as IPsec and SSL/TLS for legacy purposes.

(6e) Host Interface Description

(49) The host interface performs the data conversion from the wireless SoC sub-system to an SDIO or Ethernet media independent interface format.

(6f) Processor

(50) The processor is a dual-core ARM Cortex processor system. The processor will assist in protocol processing, data management, and system administration for all functional blocks within the FPGA. The process will assist the Ethernet MAC, the IEEE 1588, the Ethernet OAM, and the security functional blocks.

(51) The following is a description of the data flow received (Receive Data Flow) in the wireless SFPs of FIGS. 10, 11 and 12.

(52) Wireless signals are received by the wireless SFP wireless SoC's Radio through the antenna connector by means of an external antenna or without the connector by means of the etch PCB antenna. The antenna will filter and convert the wireless signal to an electrical signal, which the electrical signal will be received by the wireless SoC radio. The radio's transmit and receive sections include all on-chip filtering, mixing, and gain control functions. The wireless signals will then be processed by the wireless PHY. The wireless PHY is designed to comply with IEEE 802.11ac and IEEE 802.11a/b/g/n single-stream specifications to provide wireless LAN connectivity supporting data rates from 1 Mbps to 433.3 Mbps for low-power, high-performance applications. The PHY has been designed to work in the presence of interference, radio nonlinearity, and various other impairments. It incorporates optimized implementations of the filters, FFT and Viterbi decoder algorithms. The PHY carrier sense has been tuned to provide high throughput for IEEE802.11g/11b hybrid networks with Bluetooth coexistence. Wireless signals from the PHY circuitry are then connected to a media access controller (MAC). The wireless MAC is designed to support high-throughput operation with low-power consumption. It does so without compromising the Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several power saving modes have been implemented that allow the MAC to consume very little power while maintaining network-wide timing synchronization. The data from the MAC will then interface with the wireless SoC host interface, which will convert the data into an SDIO or Ethernet media independent format.

(53) The wireless SoC data will then interface with the FPGA. The FPGA will either convert the SDIO data format or connect directly to the FPGA Ethernet MAC. The Ethernet MAC will provide protocol processing and update the data with IEEE 1588 or SyncE information. If required, the updated data from the Ethernet MAC will be encrypted by the security functional block. The data will be serialized and transmitted differentially at compatible voltage levels per the appropriate SFF specification document to the wireless SFP PCB edge connector.

(54) The wireless data received from the Bluetooth will flow from the Bluetooth sub-system to the wireless SoC and SFP processor. The wireless SoC processor will inspect and process the data accordingly. The Bluetooth data may provide wireless mobile location, identity, status, etc., for the wireless SoC and SFP processor.

(55) The following is a description of the data flow transmitted (Transmit Data Flow) in the wireless SFPs of FIGS. 10, 11, and 12.

(56) The transmit data from the SFP PCB edge connector will interface with the FPGA. The FPGA will convert the serialized data format to the Ethernet MII format of the FPGA Ethernet MAC. The Ethernet MAC will provide protocol processing and update the data with IEEE 1588 or SyncE information. If required, the updated data from the Ethernet MAC will be encrypted by the security functional block. The transmit data from the FPGA will interface to the wireless SoC's host interface. The wireless SoC host interface will convert the transmit data to the SoC MAC for protocol processing. The transmit data will then interface to the SoC PHY and Radio. The SoC PHY and Radio will convert the transmit data RF signal to wireless using an external antenna attachment or the internal etched PCB antenna.

(57) The Bluetooth wireless data will transmit from the wireless SFP and SoC processor to the wireless SoC Bluetooth sub-system. The transmit data from the Bluetooth sub-system will be interleaved by the Wi-Fi coexistence switch to either a connector for the external antenna or directly onto an etched PCB antenna. The Bluetooth data will be transmitted to other wireless SFP and wireless mobile devices. The data will consist of location, identity, status of all wireless SFP devices or wireless mobile devices, or IoT.

(58) FIG. 16 illustrates an exemplary embodiment of a method and system of the present disclosure used for Wi-Fi triangulation and Bluetooth communications involving three wireless SFPs and mobile devices. As illustrated, the three wireless SFP devices are placed into ports in three different network interface devices, each of which is connected to a network edge switch. These three wireless SFPs selectively communicate via both wireless 1 and wireless 2 signals with various devices. The signals can be triangulated such that the location of a device with a transmitter can be determined by measuring either the radial distance, or the direction, of the received signal from two or three different points, and the geographic position of the device can be pinpointed.

(59) While the embodiment(s) disclosed herein are illustrative of the structure, function und operation of the exemplary method(s), system(s) and device(s), it should be understood that various modifications may be made thereto with departing from the teachings herein. Further, the components of the method(s), system(s) and device(s) disclosed herein can take any suitable form, including any suitable hardware, circuitry or other components capable of adequately performing their respective intended functions, as may be known in the art.

(60) It should be understood that the individual components of the circuitry illustrated in FIGS. 10-13 and 15 could be any commercially available components, respectively. For example, the wireless SoC could be a Broadcom/Cypress BCM4339, a Marvell Avastar 88W8887, a Marvell Avastar 88W8977, or any equivalent or similar SoC suitable to produce the device(s), system(s) and method(s) disclosed herein, and/or achieve the functionality of the device(s), system(s) and method(s) disclosed herein. The FPGA could be either a Microsemi SmartFusion2 SoC FPGA, an Intel/Altera Cyclone V FPGA, or any equivalent or similar FPGA suitable to produce the device(s), system(s) and method(s) disclosed herein, and/or achieve the functionality of the device(s), system(s) and method(s) disclosed herein.

(61) While the foregoing discussion presents the teachings in an exemplary fashion with respect to the disclosed method(s), system(s) and device(s) for providing wireless communication services, it will be apparent to those skilled in the art that the present disclosure may apply to other method(s) and system(s) utilizing wireless technologies. Further, while the foregoing has described what are considered to be the best mode and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the method(s), system(s) and device(s) may be applied in numerous applications, only some of which have been described herein.