Self-aligned register structure for base polysilicon and preparation method thereof

Abstract

The present invention discloses a self-aligned register structure for base polysilicon and a preparation method thereof. The self-aligned register structure comprises a silicon substrate having a partially oxidized region of SiO2 medium, a SiO2 medium protective layer is arranged at a center above the silicon substrate, base polysilicon layers are located at left and right sides of the SiO2 medium protective layer, the adjacent base polysilicon layers are symmetrical to the SiO2 medium protective layer at equal spacing, and the spacing is equal to a thickness of the base polysilicon layer. The self-aligned register structure for base polysilicon of the present invention meets an extremely high register requirement, guarantees the uniformity of electric parameters of devices, and eliminates physical or chemical damage to an intrinsic region when etching a surface of the silicon substrate during the forming of the base polysilicon, thus reducing the capacitance and enhancing the product yield; and meanwhile, the preparation method is simple, convenient, low in cost, and short in time.

Claims

1. A self-aligned register structure for base polysilicon, comprising a silicon substrate having a partially oxidized region of SiO.sub.2 medium, wherein a SiO.sub.2 medium protective layer is arranged at a center above the silicon substrate, base polysilicon layers are located at left and right sides of the SiO.sub.2 medium protective layer, the adjacent base polysilicon layers at both sides are symmetrical to the SiO.sub.2 medium protective layer at equal spacing, and the spacing is equal to a thickness of each of the base polysilicon layers.

2. The self-aligned register structure for base polysilicon according to claim 1, wherein the silicon substrate between the SiO.sub.2 medium protective layer and the adjacent base polysilicon layers at both sides is slightly etched to a depth of 0.1-0.2 μm.

3. A preparation method of a self-aligned register structure for base polysilicon, the preparation method comprising the following steps of: (1) oxidizing to form a SiO.sub.2 medium protective layer on a silicon substrate having a partially oxidized region of SiO.sub.2 medium, and depositing a polysilicon layer on the SiO.sub.2 medium protective layer; (2) photoetching the polysilicon layer and terminating the photoetching at the SiO.sub.2 medium protective layer, and removing the SiO.sub.2 medium protective layer without the polysilicon layer thereon by wet etching; (3) depositing a base polysilicon layer on the silicon substrate and the polysilicon layer after the step (2); (4) spinningly coating a photoresist on the base polysilicon layer, and then etching back the photoresist and the base polysilicon layer without the protection of the photoresist etched back to expose the polysilicon layer on the SiO.sub.2 medium protective layer; (5) keeping on etching back the polysilicon layer and terminating the etching back at the SiO.sub.2 medium protective layer; and (6) removing the photoresist to obtain the self-aligned register structure for base polysilicon, wherein the obtained self-aligned register structure for base polysilicon has the SiO.sub.2 medium protective layer arranged at a center above the silicon substrate, base polysilicon layers located at left and right sides of the SiO.sub.2medium protective layer, the adjacent base polysilicon layers at both sides are symmetrical to the SiO2 medium protective layer at equal spacing, and the spacing is equal to a thickness of each of the base polysilicon layers.

4. The preparation method according to claim 3, wherein a thickness of the SiO.sub.2 medium protective layer formed by oxidizing in the step (1) is 300 Å to 400 Å.

5. The preparation method according to claim 3, wherein a thickness of the polysilicon layer in the step (1) is 4000 Å to 5000 Å.

6. The preparation method according to claim 3, wherein a thickness of the SiO.sub.2 medium protective layer removed by wet etching in the step (2) is 300 Å to 400 Å.

7. The preparation method according to claim 3, wherein a thickness of the base polysilicon layer in the step (3) is 2000 Å to 3000 Å.

8. The preparation method according to claim 3, wherein in the step (4), the photoresist with a thickness of 0.8-1.2 μm is spinningly coated on the base polysilicon layer, and then the photoresist with a thickness of 0.4-0.6 μm is etched back.

9. The preparation method according to claim 3, wherein after terminating at the SiO.sub.2 medium protective layer in the step (5), the silicon substrate between the SiO.sub.2 medium protective layer and the base polysilicon layer is lightly etched.

10. The preparation method according to claim 9, wherein the silicon substrate is slightly etched to a depth of 0.1-0.2 μm in the step (5), and to a width equal to a thickness of the finally remained base polysilicon layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of oxidizing to form a SiO.sub.2 medium protective layer on a silicon substrate having a partially oxidized region of SiO.sub.2 medium, and depositing a polysilicon layer.

(2) FIG. 2 is a schematic diagram of removing the SiO.sub.2 medium protective layer after photoetching and etching the polysilicon layer.

(3) FIG. 3 is a schematic diagram of depositing a base polysilicon layer.

(4) FIG. 4 is a schematic diagram of spinningly coating a photoresist.

(5) FIG. 5 is a schematic diagram of etching back the photoresist.

(6) FIG. 6 is a schematic diagram of etching the polysilicon layer and terminating at the SiO.sub.2 medium protective layer.

(7) FIG. 7 is a schematic diagram of removing the photoresist, forming the base polysilicon and the SiO.sub.2 medium protective layer, and obtaining a base polysilicon self-aligned register structure.

DESCRIPTION OF THE EMBODIMENTS

(8) The present invention is further explained with reference to the embodiment and drawings hereinafter.

EMBODIMENT

(9) As shown in FIG. 1, before forming a base polysilicon, oxidizing is performed to form a SiO.sub.2 medium protective layer with a thickness of 300 Å to 400 Å on a silicon substrate 1 having a partially oxidized region of SiO.sub.2 medium 2, and a polysilicon layer 4 with a thickness of 4000 Å to 5000 Å is deposited on the SiO.sub.2 medium protective layer 3 to achieve damage-free protection of an intrinsic region of a device. As shown in FIG. 2, the polysilicon layer 4 is photoetched and the photoetching is terminated at the SiO.sub.2 medium protective layer 3, then the SiO.sub.2 medium protective layer 3 without the polysilicon layer thereon is removed by wet etching. As shown in FIG. 3, the deposited base polysilicon layer 5 is grown to a thickness of 2000 Å to 3000 Å, and a boron-doped base polysilicon layer is preferred. As shown in FIG. 4, a photoresist 6 with a thickness of 0.8-1.2 μm is spinningly coated on the base polysilicon layer 5. Preferably, the thickness of the spinningly coated is 1 μm. As shown in FIG. 5, the photoresist 6 is etched back to 0.4-0.6 μm, preferably the photoresist is etched back to 0.6 μm, so that the polysilicon layer 4 on the SiO.sub.2 medium protective layer 3 is exposed. As shown in FIG. 6, the remained polysilicon layer 4 is etched, and the etching is terminated at the SiO.sub.2 medium protective layer 3. The silicon substrate 1 between the SiO.sub.2 medium protective layer 3 and the base polysilicon layers 5 is lightly etched to a depth of 0.1-0.2 μm, and a width of the lightly etched silicon substrate is equal to a thickness of the finally remained base polysilicon layer. As shown in FIG. 7, the remained photoresist is removed to obtain a self-aligned register structure for base polysilicon.

(10) The self-aligned register structure prepared comprises a silicon substrate 1 having a partially oxidized area of SiO.sub.2 medium 2, a SiO.sub.2 medium protective layer 3 is arranged at a center above the silicon substrate 1, base polysilicon layers 5 are located at left and right sides of the SiO.sub.2 medium protective layer 3, the adjacent base polysilicon layers 5 at both sides are symmetrical to the SiO.sub.2 medium protective layer 3 at equal spacing, and the spacing is equal to a thickness of the base polysilicon layer 5. A termination position of the SiO.sub.2 medium protective layer 3 is just at the center of the base polysilicon layer 5. The silicon substrate between the SiO.sub.2 medium protective layer 3 and the adjacent base polysilicon layers 5 at both sides is lightly etched to a depth of 0.1-0.2 μm, and a width of the lightly etched silicon substrate is equal to a thickness of the finally remained base polysilicon layer. The self-aligned register structure for base polysilicon realizes self-aligned register of the base polysilicon and the SiO.sub.2 medium protective layer in the technological process of the double-polysilicon self-aligned bipolar transistors.