PACKAGE FOR ELECTRIC DEVICE AND METHOD OF MANUFACTURING THE PACKAGE

Abstract

A package for an electric device is proposed based on a substrate (SU, SU1, SU2) that comprises at least a piezoelectric layer. Device structures are enclosed in a cavity of an integrally formed package layer structure (PK) of a thin film package applied on the first surface (SI). A first contact pad (PI) is arranged on the first surface of the substrate and electrically connected to the device structures. A second contact pad (P2) is arranged on a second surface (S2) of the substrate opposite to the first surface (SI). A via (V) is guided through the substrate and interconnects first and second contact pads electrically. Packages may be stacked on one another and connected via two pads of different kind. The first substrate (SU1) is connected via its second pad (P2) on the second surface thereof to the first pad of a second substrate (SU2) by means of connection means (CM).

Claims

1. A package for an electric device, comprising: a substrate at least a piezoelectric layer operational device structures on a first surface of the piezoelectric layer an integrally formed package layer structure on the first surface comprising at least a mechanical support layer covering the first surface of the substrate and enclosing the device structures in a cavity a first contact pad on the first surface of the substrate electrically connected to the device structures a second contact pad on a second surface opposite to the first surface a via guided through the substrate and electrically interconnecting first and second pads.

2. The package claim 1, wherein: the support layer comprises a silicon oxide layer that forms domes enclosing the device structures a protection layer is applied on and covers the support layer a barrier layer covers the protection layer the first pads are exposed from the first surface side.

3. The package of claim 1, wherein the first contact pad is covered by the package layer structure wherein an external contact of the device structures is provided solely by the second contact pads.

4. The package of claim 1, wherein: a substrate with a second similar package comprises at least a first pad exposed on a first surface side or a second pad on a second surface of the substrate the first package is connected to the second package by connecting the second pad of the first package with the first or second pad of the second substrate by bonding via a solder bump, a pillar or a stud bump.

5. The package of claim 1, wherein: the device structures are part of a SAW device or a BAW device.

6. The package of claim 1, wherein first and/or second substrate are/is a wafer each wafer comprising a multitude of preformed electric devices with operational device structures.

7. A method of manufacturing a package for an electric device, comprising the steps A) providing a first wafer comprising a piezoelectric layer B) forming device structures for a multitude of electric devices in parallel on a first surface of the first wafer and first pads connected to the device structures C) applying over the device structures an integrated package layer structure that seals to the first surface and forms cavities between layer structure and first surface of wafer to enclose device structures within the cavity D) reducing the thickness of the wafer from the second surface opposite to the first surface E) forming holes in the second surface to a depth until the bottom parts of the first pads are exposed F) depositing a metallization on the second surface electrically contacting the first pad in the holes G) forming second pads on the second surface on or from the metallization.

8. The method of claim 7, wherein forming the holes in step E) comprises ablation of material from the wafer by drilling, etching or by using a laser beam.

9. The method of claim 7, wherein a second wafer is provided by performing steps A) to D) the method further comprising performing the steps E) to G) at both wafers and a step J1) arranging first and second wafer in a stack where their second surfaces are facing each other, and directly connecting the second pads of first and second wafer.

10. The method of claim 5, wherein a second wafer is provided by performing steps A) to D) the method further comprising the steps H2) exposing the first pads of the second wafer J2) arranging first and second wafer in a stack where the second surface of the first wafer faces the first surface of the second wafer and directly connecting the second pads of the first wafer and the first pads of the second wafer.

11. The method of claim 7, wherein the following steps are performed after step C) C1) forming trenches in the first surface of the first and the second wafer thereby dividing different areas of the later single devices, C2) temporarily bonding the first surfaces of the first wafer to a temporary carrier D) reducing the thickness of the first wafer from the second surface to expose the trenches from the bottom E) forming holes in the second surface of the first wafer to a depth until the bottom parts of the first pads are exposed F) depositing a metallization on the second surface of the first wafer electrically contacting the first pads in the holes G) forming second pad on the second surface on or from the metallization H2) exposing the first pads of the second wafer J2) arranging first and second wafer in a stack where the second surface of the first wafer faces the first surface of the second wafer and directly connecting the second pad of the first wafer and the first pads of the second wafer K2) reducing the thickness of the second wafer from the second surface to expose the trenches from the bottom.

12. The method of claim 7, wherein the first wafer comprises a thin piezoelectric layer on a carrier substrate wherein after step C) trenches are formed that cut only through the piezoelectric layer wherein after finally processing of the second surface a singulation step is performed using laser cutting or plasma etching.

13. The method of claim 7, wherein step C) comprises forming a barrier layer as a topmost layer of the package layer structure, wherein the barrier layer is chosen from a metal layer, a SiN layer and any other layer that can function as a barrier against humidity.

14. The method of claim 7, wherein steps F and G) comprise forming a redistribution layer in or on the metallization and forming second pads that are laterally shifted relative to the first pads wherein a conductor line of the redistribution layer electrically connects second pads to the metallization in the holes and hence to the respective first pads.

15. The method of claim 7, comprising preparing a third or a fourth wafer and bonding it on respective second pads of the already formed stack of first, second or higher numbered wafer.

16. The method of claim 7, wherein a temporary carrier is used in step C2) comprising the same material like the wafer, wherein the temporary carrier is separated from the wafer after step K2 and after completing of processing of second surface.

Description

[0060] In the following the invention is further explained by specific embodiments and the accompanying figures. The figures are schematic only and not drawn to scale such that features may be depicted enlarged or reduced in dimension such that no relative dimensions of different features can be taken from the figures.

[0061] FIG. 1 shows a first embodiment of a package in a cross-sectional view;

[0062] FIG. 2 shows the second embodiment of a package in a cross-sectional view;

[0063] FIG. 3 shows a stack of two packages;

[0064] FIG. 4 shows a stack of three packages;

[0065] FIG. 5 shows different steps of a method of manufacturing such a package;

[0066] FIG. 6 shows a stage after producing the trenches;

[0067] FIG. 7 shows a wafer with trenches that divide the total surface area into smaller areas, each for a single electric device;

[0068] FIG. 8 shows a package on wafer level after thinning of the substrate; and

[0069] FIG. 9 shows the package the second embodiment after forming a second pad and a bump thereon.

[0070] FIG. 1 shows a cross-section of a first embodiment of a package 1. A substrate SU at least comprises a piezoelectric layer or may be totally made of a piezoelectric material. On top of the substrate SU, that is on the first surface S1 thereof, device structures for an electric device are arranged and connected to a first contact pad P1. For the sake of simplicity, the device structures are not shown in the figure. The device structures as a whole or part of the devices structures are arranged in a cavity between a package layer structure PK and the first surface S1 of the substrate SU. The package layer structure PK is applied onto the first surface S1 and forms domes that enclose the cavity between the package layer structure PK and the first surface S1. The cavities allow the free operating of device structures that are sensitive to mechanical impact.

[0071] The package layer structure PK comprises at least a mechanical support layer SL, the at least one dome and may comprise further layers deposited thereon to further mechanically stabilize the package layer structure PK. An outermost layer of the package layer structure may be a barrier layer BL that forms a barrier against humidity. The barrier layer may also comprise a metal to function as a shield against electromagnetic fields.

[0072] On a second surface S2 of the substrate SU a metallization is applied forming at least a second contact pad P2. A via V is guided through the substrate SU just opposite to the first pad P1 and connects this first pad to the metallization on the second surface S2. On the metallization at least the second contact pad is formed.

[0073] In the figure, two cavities are shown. However, an electric device may comprise an arbitrary number of domes/cavities for example one or more than two domes dependent on the size and number of the device structures. The first contact pads P1 have a thickness that is higher than the thickness of a normal contact pad because during manufacturing of the package it has to function as a stopping layer when forming the holes. The device structures may require two or more electric terminals and hence are connected to two or more first pads P1. Each first pad P1 is connected to a second pad P2 on the second surface S2 by means of a via V formed through the substrate SU.

[0074] The figure shows a section of the substrate that carries device structures for one electric device. Preferably the substrate SU is a wafer carrying a multitude of such device structures each covered by a package layer structure. Alternatively, the package layer structure may be a common one for all device structures on the same wafer.

[0075] FIG. 2 shows a second embodiment of a package 1′ similar to the package 1 of the first embodiment with the exception that an opening OP is formed above the first pad P1 and exposes the surface thereof. The barrier layer BL may or may not seal to the surface of a first pad P1 at the sidewalls of the opening OP. Hence, the depicted package 1′ offers free access to a first and a second pad P1, P2 and allows connection of the package with the pads on the first surface S1 or the second surface S2.

[0076] FIG. 3 shows a third embodiment of the invention where a package of the first embodiment and a package 2 of the second embodiment are stacked on one another and connected via two pads of different kind. The first substrate SU1 is connected via its second pad P2 on the second surface S2 thereof to the first pad P1 of a second substrate SU2. The second substrate SU2 still has a freely accessible second pad P2 on a second surface. The electrical connection between first and second substrate is done by means of connection means CM that are formed as solder balls, bumps, stud bumps or pillars. The mounting of the first substrate SU1 to the second substrate SU2 is done by simultaneously connecting all second pads P2 of the first substrate SU1 to respective first pads P1 of the second substrate SU2. Hence, stacking and mounting of two packages can be done on wafer level.

[0077] The arrangement shown in FIG. 3 has the advantage that the first substrate SU1 on top of the arrangement need not expose a freely accessible first pad P1 on the topmost surface thereof. Hence, this first substrate or first package saves the surface area that would be otherwise required for an accessible solderable pad. The surface area saved on the first surface can advantageously be used for arranging there device structures or for miniaturizing the first package by a respective amount.

[0078] Deviating from the package structure of the second embodiment shown in FIG. 2, the second substrate SU2 of FIG. 3 need not necessarily have a second pad P2 and hence need not have a via V for connecting first and second pad. External contact of the arrangement can be made by another contact or contact structure.

[0079] FIG. 4 shows another arrangement where three packages, as shown in FIGS. 1 and 2, are stacked one above the other and electrically and mechanically connected by connecting means CM. The stack can be achieved by mounting the stack of FIG. 3 via the second pads of the second substrate SU2 to the first pads of a third package formed according to the second embodiment as shown in FIG. 2. Here again, the topmost package made on the first substrate SU1 does not provide an access to the first contact pad that is covered by the package layer structure PK. The arrangement of FIG. 3 provides the same benefit.

[0080] Also in this arrangement the bottom package/substrate SU3 does neither require a second pad P2 nor a via connecting a second pad to a respective first pad P1.

[0081] The stacked arrangements shown in FIGS. 3 and 4 form a system in a package and allow a three-dimensional integration of electric devices that is space-saving and can be miniaturized with respect to an arrangement comprising only laterally arranged devices.

[0082] FIG. 5 shows different stages of a method of manufacturing a package as shown in FIG. 1. The process starts from a substrate SU comprising at least a piezoelectric layer or being a piezoelectric material. On the first surface S1 thereof, device structures are arranged and connected to a first pad P1. Device structures and first pad P1 are made from different metallizations or are at least different in height as the first pad P1 has a substantially higher thickness than the metallization of the device structures.

[0083] In case of a SAW device the device structures may be covered with a layer that reduces the TCF (=thermal coefficient of frequency). Such a layer can be formed as an SiO.sub.2 layer of about 1.5 μm thickness. A trimming layer of e.g. SiN can cover the TCF reducing layer.

[0084] The structures are then covered with a sacrificial layer SC that can be applied to the entire first surface S1 and is then structured to cover only the device structures to be protected thereunder. Alternatively, the sacrificial layer SC may be applied exclusively at those locations where it is needed. FIG. 5 a shows such a structured sacrificial layer.

[0085] In a next step the structured sacrificial layer SC is covered by a mechanically stable support layer SL. The support layer can be deposited on the entire surface of the first surface of the substrate SU but may be structured to cover only the sacrificial material of the sacrificial layer SL plus a margin around these islands of sacrificial material SC. In a preferred example, the support layer SL comprises an SiO.sub.2 layer of about 3 μm thickness applied in a sputter process. The support layer SL may be structured if required by a photolithography and a dry etching process.

[0086] In the next step release holes are formed through the support layer SL and the sacrificial material is removed through the release holes, for example by wet etching. FIG. 5B shows the arrangement in this state.

[0087] In the next step the release holes are closed by applying a proper closing material on the release holes such that the cavity CV is closed. Then, further layers of the package layer structure can be applied. One of these layers may be a polymer layer like BCB of about 9 μm thickness that can easily be planarized so that a plane surface remains on top of the package layer structure PK. The topmost layer is a barrier layer BL that preferably seals to the first surface S1 of the substrate SU. The barrier layer can comprise SiN or a metal. FIG. 5C shows the arrangement at this stage.

[0088] In the next step the substrate SU may be thinned in a proper process, for example by grinding. The resulting final thickness of the substrate is chosen to provide reliable device operation and further to maintain sufficient mechanical stability to handle the substrate/package. If the substrate SU is a piezoelectric layer and device structures for a SAW or a BAW device are present, an exemplary thinned substrate thickness is chosen at 60 to 70 μm. FIG. 5D shows the arrangement with the respectively thinned substrate SU.

[0089] In the next step holes HL are formed from the second surface side S2 through the substrate to expose the bottom side of the first contact pad P1. These holes HL may be formed by a wet or dry etching process or are directly formed by using a laser beam. In the latter case, the sidewalls of the hole HL are inclined against the surface to have a smaller cross-section at the first contact pad side on the first surface S1. FIG. 5E shows the arrangement at this stage.

[0090] In the next step a metallization is applied to the second surface S2 to at least cover the sidewalls and contact the first contact pad from the bottom, respectively from the side of the second surface S2. A metallization ME may be applied to the entire second surface S2 and then structured. Alternatively, a first partial layer of the metallization can comprise a sputter deposited adhesion layer of Ti and a sputtered seed layer of copper. A photoresist mask can be applied to the entire metallized surface and then a plating process is performed to thicken the metallization in the exposed areas of the resist mask. Thereby a second contact pad P2 preferably formed of Cu and having a thickness of about 5 μm is formed on the metallization. The pad can be completed by applying an under bump metallization comprising a solderable metal as a top layer for example Au. Other solderable layers may be used instead comprising one of Ni and Ag. On such solderable layers solder bumps or copper pillars or stud bumps can be applied for making an electric contact. FIG. 5F shows the arrangement at this stage.

[0091] The metallization can comprise one or more layers and at least one of them is a conducting layer. Other useful deposition techniques comprise PVD, CVD, galvanic or chemical deposition. Another method is spraying a suspension of electrically conducting nanoparticles and subsequently vaporizing the solvent. The metallization may be applied directly in a structured form by using suitable masks applied on the surface of the substrate.

[0092] If a photoresist has been used this can be removed in a wet chemical process or in a plasma.

[0093] In the next step solder bumps, stop bumps or other connection means are applied on the second surface by means of stencil printing, for example with subsequent reflow, or via a photo-technique in a galvanic process.

[0094] Now the electric device is ready to be mounted into a desired final circuit or for being prepared for storage and transport.

[0095] FIGS. 6 to 8 show process steps that can be used to singulate single electric devices from a wafer comprising a multiple of such devices.

[0096] FIG. 6 shows part of a wafer substrate SU with a package layer structure PK applied on the first surface S1 that covers the device structure of the electrical device. As shown in this embodiment a further planarizing layer PL can applied onto the package layer structure as shown in FIG. 5F or FIG. 1, for example. To facilitate the singulation process trenches are formed from the first surface side through all layers of the package layer structure PK and through a part of the layer thickness of the substrate SU. The trenches TR follow separation lines that divide the single devices from each other. FIG. 6 shows the arrangement after forming the trenches. For the sake of simplicity only one device is shown from the whole wafer.

[0097] FIG. 7 shows a greater section from such a wafer where the package layer structure is only depicted schematically and simplified. All trenches are cut into the substrate to the same depth. Here, the further planarizing layer is omitted.

[0098] In the next step the arrangement is stabilized by bonding the arrangement to a temporary carrier TC in a suitable bonding process. FIG. 8 shows a connection by means of a thermo-adhesive layer AL. The package is embedded into the thermo-adhesive layer AL on the temporary carrier TC that has been softened in a thermal step.

[0099] A preferred temporary carrier TC is adapted to the substrate material in view of its coefficient of thermal expansion to avoid thermal stress when subjecting the arrangement to a thermal process during further processing.

[0100] In the next step the thickness of the substrate is reduced by thinning the substrate wafer from the second surface until the trenches are exposed from the bottom. This can be done by grinding followed by a possible step of chemical-mechanical polishing CMP. FIG. 8 shows the arrangement at this stage.

[0101] Alternatively, in cases where only a thin piezoelectric layer is arranged on a carrier substrate like a Si wafer the step of forming trenches may comprise forming trenches in the first surface of the substrate that cut only through the piezoelectric layer. After thinning the substrate from the second surface side these trenches are not yet exposed.

[0102] In a further alternative process variant the step of forming trenches is totally omitted in cases where only a thin piezoelectric layer is arranged on a carrier substrate.

[0103] In both alternating variants with no trenches or with trenches only through the piezoelectric layer the singulation of the substrate into single devices is done by laser cutting or plasma etching from the second surface side after complete processing of the second surface as explained later on in connection with FIG. 8. Such further processing comprises forming a redistribution layer on the second surface, further structuring of the redistribution layer and forming a UBM on the second pads. In this case further proceeding on the second surface can be done before singulation step and hence no temporary carrier or mounting foil is required.

[0104] The arrangement shown in FIG. 8 can now be subjected to process steps as shown in connection with FIGS. 5E and 5F. Thereby holes are formed through the substrate to expose first pads on the first surface from the bottom and a metallization is deposited on the second surface and second pads are formed on or in the metallization.

[0105] When the second pads P2 are completed the total wafer arrangement that is already bonded to the temporary carrier can be mounted to another wafer by connecting it to the first or second pads of the other wafer.

[0106] It is possible to attach and fix a mounting foil or another temporary carrier to the first surface before singulating the substrate from the second surface to further proceed on a “wafer level” despite the fact that the devices have already been singulated. With the help of the mounting foil a multitude of single devices can be processed in parallel the same way as with a wafer. On the mounting foil the same mutual arrangement of single devices like on a wafer is kept.

[0107] FIG. 9 shows a package according to the first embodiment after bumping or after applying a connection means to the metallization ME at the second pad. Between pad and connection means/bump an under bump metallization UBM is applied. The barrier layer may be a metal that an electromagnetic shield is formed. The barrier layer then seals and contacts to the exposed first pad.

[0108] The proposed package shows at least the following advantages: [0109] Minimal possible physical size of the devices/chips [0110] Smallest contact pad size on the first surface being the functional wafer side. [0111] Maximal possible flexibility for arranging contact pads and bump layout due to the redistribution layer RDL. [0112] Absolute hermeticity of package due to unstructured SiN or metal outer layer on top of the package or the topmost package when stacking a multiple of packages. [0113] Possibility of forming metal shield for protection from electro-magnetic field and heat transport as a topmost layer of package or stack. [0114] Compatibility with standard and 180 μm bump pitch techniques and Cu-pillar process. [0115] Possibility of enhancing of dome strength and package stability with Cu-posts or frames that are auxiliary supporting metal structures that can be formed in the same step and together with the forming of the pads. [0116] Highest standoff for existing SAW packages when contacting second pads to an external circuit like a PCB. This high stand-off is advantageous in an optional subsequent molding or underfill step. [0117] The package can be stacked with the same or similar package (DSSP, TFAP1, TFAP2). Different types of packages may be stacked on the same substrate. [0118] If the same package is used, several different layer stacks are possible with the same approach. [0119] The package can be used for any wafer material: LN, LT, Si. [0120] In case the substrate comprises a Si wafer as used for BAW or thin film SAW devices further integration with semiconductor chips is possible.

[0121] Despite having shown only a few embodiments the invention is not restricted to the embodiments and the figures. The broadest definition of the invention can be taken from the independent claims.

TABLE-US-00001 List of used reference symbols 1,1′ package AL adhesive layer BL barrier layer CM connection means CV cavity HL hole ME metallization ME metallization OP opening in PK to expose P1 P1 first contact pad P2 second contact pad PK package layer structure PL planarization layer PR protection layer RDL redistribution layer S1 first surface S2 second surface SC sacrificial layer SL mechanical support layer ST stack of first and second wafer SU substrate with piezoelectric layer TC temporary carrier TR trench V via